Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7360793 |
1 |
|
|
T21 |
1 |
|
T22 |
188 |
|
T23 |
31555 |
| auto[1] |
5158783 |
1 |
|
|
T22 |
387 |
|
T23 |
26615 |
|
T1 |
39441 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10391967 |
1 |
|
|
T21 |
1 |
|
T22 |
415 |
|
T23 |
41915 |
| auto[1] |
2127609 |
1 |
|
|
T22 |
160 |
|
T23 |
16255 |
|
T1 |
23418 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7338231 |
1 |
|
|
T21 |
1 |
|
T22 |
224 |
|
T23 |
32672 |
| auto[1] |
5181345 |
1 |
|
|
T22 |
351 |
|
T23 |
25498 |
|
T1 |
38072 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1524498 |
1 |
|
|
T22 |
60 |
|
T23 |
4652 |
|
T1 |
7038 |
| auto[1] |
auto[0] |
auto[1] |
1069855 |
1 |
|
|
T22 |
54 |
|
T23 |
8120 |
|
T1 |
11245 |
| auto[1] |
auto[1] |
auto[0] |
1529238 |
1 |
|
|
T22 |
131 |
|
T23 |
4591 |
|
T1 |
7616 |
| auto[1] |
auto[1] |
auto[1] |
1057754 |
1 |
|
|
T22 |
106 |
|
T23 |
8135 |
|
T1 |
12173 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |