Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7371882 |
1 |
|
|
T21 |
1 |
|
T22 |
191 |
|
T23 |
33282 |
auto[1] |
5147694 |
1 |
|
|
T22 |
384 |
|
T23 |
24888 |
|
T1 |
39484 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10393433 |
1 |
|
|
T21 |
1 |
|
T22 |
400 |
|
T23 |
42147 |
auto[1] |
2126143 |
1 |
|
|
T22 |
175 |
|
T23 |
16023 |
|
T1 |
23649 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7353255 |
1 |
|
|
T21 |
1 |
|
T22 |
209 |
|
T23 |
33326 |
auto[1] |
5166321 |
1 |
|
|
T22 |
366 |
|
T23 |
24844 |
|
T1 |
38833 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1519980 |
1 |
|
|
T22 |
68 |
|
T23 |
4859 |
|
T1 |
7350 |
auto[1] |
auto[0] |
auto[1] |
1067228 |
1 |
|
|
T22 |
53 |
|
T23 |
8594 |
|
T1 |
11871 |
auto[1] |
auto[1] |
auto[0] |
1520198 |
1 |
|
|
T22 |
123 |
|
T23 |
3962 |
|
T1 |
7834 |
auto[1] |
auto[1] |
auto[1] |
1058915 |
1 |
|
|
T22 |
122 |
|
T23 |
7429 |
|
T1 |
11778 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |