Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7366938 |
1 |
|
|
T21 |
1 |
|
T22 |
279 |
|
T23 |
31648 |
auto[1] |
5152638 |
1 |
|
|
T22 |
296 |
|
T23 |
26522 |
|
T1 |
37813 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10391741 |
1 |
|
|
T21 |
1 |
|
T22 |
444 |
|
T23 |
41697 |
auto[1] |
2127835 |
1 |
|
|
T22 |
131 |
|
T23 |
16473 |
|
T1 |
24869 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7359175 |
1 |
|
|
T21 |
1 |
|
T22 |
345 |
|
T23 |
31626 |
auto[1] |
5160401 |
1 |
|
|
T22 |
230 |
|
T23 |
26544 |
|
T1 |
40496 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1528404 |
1 |
|
|
T22 |
20 |
|
T23 |
4980 |
|
T1 |
8356 |
auto[1] |
auto[0] |
auto[1] |
1068423 |
1 |
|
|
T22 |
52 |
|
T23 |
8065 |
|
T1 |
13107 |
auto[1] |
auto[1] |
auto[0] |
1504162 |
1 |
|
|
T22 |
79 |
|
T23 |
5091 |
|
T1 |
7271 |
auto[1] |
auto[1] |
auto[1] |
1059412 |
1 |
|
|
T22 |
79 |
|
T23 |
8408 |
|
T1 |
11762 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |