Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7342638 |
1 |
|
|
T21 |
1 |
|
T22 |
156 |
|
T23 |
31666 |
auto[1] |
5176938 |
1 |
|
|
T22 |
419 |
|
T23 |
26504 |
|
T1 |
37297 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10395983 |
1 |
|
|
T21 |
1 |
|
T22 |
422 |
|
T23 |
41642 |
auto[1] |
2123593 |
1 |
|
|
T22 |
153 |
|
T23 |
16528 |
|
T1 |
23958 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7361199 |
1 |
|
|
T21 |
1 |
|
T22 |
278 |
|
T23 |
32243 |
auto[1] |
5158377 |
1 |
|
|
T22 |
297 |
|
T23 |
25927 |
|
T1 |
39400 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1516135 |
1 |
|
|
T22 |
38 |
|
T23 |
4539 |
|
T1 |
8314 |
auto[1] |
auto[0] |
auto[1] |
1059438 |
1 |
|
|
T22 |
49 |
|
T23 |
8044 |
|
T1 |
12604 |
auto[1] |
auto[1] |
auto[0] |
1518649 |
1 |
|
|
T22 |
106 |
|
T23 |
4860 |
|
T1 |
7128 |
auto[1] |
auto[1] |
auto[1] |
1064155 |
1 |
|
|
T22 |
104 |
|
T23 |
8484 |
|
T1 |
11354 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |