Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7326378 |
1 |
|
|
T21 |
1 |
|
T22 |
372 |
|
T23 |
31303 |
| auto[1] |
5193198 |
1 |
|
|
T22 |
203 |
|
T23 |
26867 |
|
T1 |
37838 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11863047 |
1 |
|
|
T21 |
1 |
|
T22 |
516 |
|
T23 |
55423 |
| auto[1] |
656529 |
1 |
|
|
T22 |
59 |
|
T23 |
2747 |
|
T1 |
4916 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7380361 |
1 |
|
|
T21 |
1 |
|
T22 |
262 |
|
T23 |
32271 |
| auto[1] |
5139215 |
1 |
|
|
T22 |
313 |
|
T23 |
25899 |
|
T1 |
38217 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2237518 |
1 |
|
|
T22 |
177 |
|
T23 |
11317 |
|
T1 |
17571 |
| auto[1] |
auto[0] |
auto[1] |
327673 |
1 |
|
|
T22 |
40 |
|
T23 |
1337 |
|
T1 |
2630 |
| auto[1] |
auto[1] |
auto[0] |
2245168 |
1 |
|
|
T22 |
77 |
|
T23 |
11835 |
|
T1 |
15730 |
| auto[1] |
auto[1] |
auto[1] |
328856 |
1 |
|
|
T22 |
19 |
|
T23 |
1410 |
|
T1 |
2286 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |