Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7351588 |
1 |
|
|
T21 |
1 |
|
T22 |
348 |
|
T23 |
32130 |
| auto[1] |
5167988 |
1 |
|
|
T22 |
227 |
|
T23 |
26040 |
|
T1 |
35850 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11861575 |
1 |
|
|
T21 |
1 |
|
T22 |
510 |
|
T23 |
55585 |
| auto[1] |
658001 |
1 |
|
|
T22 |
65 |
|
T23 |
2585 |
|
T1 |
5069 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7365086 |
1 |
|
|
T21 |
1 |
|
T22 |
237 |
|
T23 |
33380 |
| auto[1] |
5154490 |
1 |
|
|
T22 |
338 |
|
T23 |
24790 |
|
T1 |
38272 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2259895 |
1 |
|
|
T22 |
197 |
|
T23 |
11156 |
|
T1 |
17535 |
| auto[1] |
auto[0] |
auto[1] |
331933 |
1 |
|
|
T22 |
48 |
|
T23 |
1359 |
|
T1 |
2797 |
| auto[1] |
auto[1] |
auto[0] |
2236594 |
1 |
|
|
T22 |
76 |
|
T23 |
11049 |
|
T1 |
15668 |
| auto[1] |
auto[1] |
auto[1] |
326068 |
1 |
|
|
T22 |
17 |
|
T23 |
1226 |
|
T1 |
2272 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |