Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7368316 |
1 |
|
|
T21 |
1 |
|
T22 |
319 |
|
T23 |
32418 |
| auto[1] |
5151260 |
1 |
|
|
T22 |
256 |
|
T23 |
25752 |
|
T1 |
38420 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11863749 |
1 |
|
|
T21 |
1 |
|
T22 |
553 |
|
T23 |
55320 |
| auto[1] |
655827 |
1 |
|
|
T22 |
22 |
|
T23 |
2850 |
|
T1 |
5073 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7373477 |
1 |
|
|
T21 |
1 |
|
T22 |
478 |
|
T23 |
31698 |
| auto[1] |
5146099 |
1 |
|
|
T22 |
97 |
|
T23 |
26472 |
|
T1 |
38833 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2262740 |
1 |
|
|
T22 |
42 |
|
T23 |
11275 |
|
T1 |
17468 |
| auto[1] |
auto[0] |
auto[1] |
333111 |
1 |
|
|
T22 |
10 |
|
T23 |
1307 |
|
T1 |
2783 |
| auto[1] |
auto[1] |
auto[0] |
2227532 |
1 |
|
|
T22 |
33 |
|
T23 |
12347 |
|
T1 |
16292 |
| auto[1] |
auto[1] |
auto[1] |
322716 |
1 |
|
|
T22 |
12 |
|
T23 |
1543 |
|
T1 |
2290 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |