Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7326978 |
1 |
|
|
T21 |
1 |
|
T22 |
160 |
|
T23 |
33383 |
| auto[1] |
5192598 |
1 |
|
|
T22 |
415 |
|
T23 |
24787 |
|
T1 |
36841 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11863336 |
1 |
|
|
T21 |
1 |
|
T22 |
529 |
|
T23 |
55324 |
| auto[1] |
656240 |
1 |
|
|
T22 |
46 |
|
T23 |
2846 |
|
T1 |
5024 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7370772 |
1 |
|
|
T21 |
1 |
|
T22 |
268 |
|
T23 |
31812 |
| auto[1] |
5148804 |
1 |
|
|
T22 |
307 |
|
T23 |
26358 |
|
T1 |
37908 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2227350 |
1 |
|
|
T22 |
98 |
|
T23 |
12036 |
|
T1 |
16676 |
| auto[1] |
auto[0] |
auto[1] |
324112 |
1 |
|
|
T22 |
19 |
|
T23 |
1458 |
|
T1 |
2488 |
| auto[1] |
auto[1] |
auto[0] |
2265214 |
1 |
|
|
T22 |
163 |
|
T23 |
11476 |
|
T1 |
16208 |
| auto[1] |
auto[1] |
auto[1] |
332128 |
1 |
|
|
T22 |
27 |
|
T23 |
1388 |
|
T1 |
2536 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |