Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 946
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T765 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2509757991 Jun 27 04:21:06 PM PDT 24 Jun 27 04:21:08 PM PDT 24 14141980 ps
T83 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1363950088 Jun 27 04:20:55 PM PDT 24 Jun 27 04:20:57 PM PDT 24 128490498 ps
T766 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2728530629 Jun 27 04:22:48 PM PDT 24 Jun 27 04:22:51 PM PDT 24 13160819 ps
T767 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2343675308 Jun 27 04:21:54 PM PDT 24 Jun 27 04:21:56 PM PDT 24 526417326 ps
T768 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1790956773 Jun 27 04:22:56 PM PDT 24 Jun 27 04:22:57 PM PDT 24 47011087 ps
T769 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3584311092 Jun 27 04:23:40 PM PDT 24 Jun 27 04:23:56 PM PDT 24 11699383 ps
T770 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2441184349 Jun 27 04:21:49 PM PDT 24 Jun 27 04:21:51 PM PDT 24 61677123 ps
T771 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3435908157 Jun 27 04:19:50 PM PDT 24 Jun 27 04:19:51 PM PDT 24 45196242 ps
T772 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1725002608 Jun 27 04:22:31 PM PDT 24 Jun 27 04:22:34 PM PDT 24 29413124 ps
T773 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1631085362 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:12 PM PDT 24 45805794 ps
T36 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2879554557 Jun 27 04:18:49 PM PDT 24 Jun 27 04:18:51 PM PDT 24 215291272 ps
T774 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3972005943 Jun 27 04:22:32 PM PDT 24 Jun 27 04:22:34 PM PDT 24 32454288 ps
T70 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3176160491 Jun 27 04:22:48 PM PDT 24 Jun 27 04:22:51 PM PDT 24 34266840 ps
T39 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2590797577 Jun 27 04:18:07 PM PDT 24 Jun 27 04:18:09 PM PDT 24 390828847 ps
T775 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.734470032 Jun 27 04:21:01 PM PDT 24 Jun 27 04:21:02 PM PDT 24 28399856 ps
T776 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4091093906 Jun 27 04:23:38 PM PDT 24 Jun 27 04:23:55 PM PDT 24 61332433 ps
T777 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1906171435 Jun 27 04:21:52 PM PDT 24 Jun 27 04:21:53 PM PDT 24 13646946 ps
T778 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.911883404 Jun 27 04:22:46 PM PDT 24 Jun 27 04:22:50 PM PDT 24 16039041 ps
T779 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3669370972 Jun 27 04:22:31 PM PDT 24 Jun 27 04:22:34 PM PDT 24 146322866 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.750596184 Jun 27 04:21:23 PM PDT 24 Jun 27 04:21:25 PM PDT 24 26985494 ps
T781 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1642907565 Jun 27 04:23:39 PM PDT 24 Jun 27 04:23:54 PM PDT 24 42222516 ps
T782 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.968353888 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:34 PM PDT 24 73913455 ps
T783 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.972936626 Jun 27 04:21:24 PM PDT 24 Jun 27 04:21:26 PM PDT 24 33803972 ps
T784 /workspace/coverage/cover_reg_top/27.gpio_intr_test.3776276585 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:12 PM PDT 24 111964065 ps
T785 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2359342816 Jun 27 04:21:41 PM PDT 24 Jun 27 04:21:43 PM PDT 24 41587690 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2230117678 Jun 27 04:19:37 PM PDT 24 Jun 27 04:19:39 PM PDT 24 57923917 ps
T787 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2226413487 Jun 27 04:20:08 PM PDT 24 Jun 27 04:20:10 PM PDT 24 11390227 ps
T788 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.643242264 Jun 27 04:23:22 PM PDT 24 Jun 27 04:23:35 PM PDT 24 147114486 ps
T37 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.554532348 Jun 27 04:20:46 PM PDT 24 Jun 27 04:20:50 PM PDT 24 286120162 ps
T789 /workspace/coverage/cover_reg_top/39.gpio_intr_test.4163335430 Jun 27 04:22:41 PM PDT 24 Jun 27 04:22:44 PM PDT 24 16525700 ps
T790 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3900752694 Jun 27 04:21:40 PM PDT 24 Jun 27 04:21:44 PM PDT 24 53266455 ps
T791 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.74113180 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:34 PM PDT 24 32520352 ps
T792 /workspace/coverage/cover_reg_top/24.gpio_intr_test.4275303022 Jun 27 04:22:40 PM PDT 24 Jun 27 04:22:44 PM PDT 24 35370993 ps
T793 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2541169418 Jun 27 04:19:06 PM PDT 24 Jun 27 04:19:07 PM PDT 24 35227026 ps
T794 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.545997236 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:33 PM PDT 24 31174255 ps
T795 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2227928629 Jun 27 04:19:16 PM PDT 24 Jun 27 04:19:18 PM PDT 24 13887278 ps
T796 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2256989944 Jun 27 04:22:57 PM PDT 24 Jun 27 04:22:58 PM PDT 24 46792071 ps
T797 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2433876695 Jun 27 04:19:40 PM PDT 24 Jun 27 04:19:43 PM PDT 24 317261991 ps
T38 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3111659671 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:33 PM PDT 24 84377563 ps
T798 /workspace/coverage/cover_reg_top/15.gpio_intr_test.4098276253 Jun 27 04:21:22 PM PDT 24 Jun 27 04:21:23 PM PDT 24 42331778 ps
T799 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1387828502 Jun 27 04:19:16 PM PDT 24 Jun 27 04:19:19 PM PDT 24 168605798 ps
T800 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.126067386 Jun 27 04:21:18 PM PDT 24 Jun 27 04:21:21 PM PDT 24 1366734050 ps
T71 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2415584616 Jun 27 04:19:39 PM PDT 24 Jun 27 04:19:40 PM PDT 24 55673288 ps
T801 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2153346817 Jun 27 04:18:53 PM PDT 24 Jun 27 04:18:55 PM PDT 24 80385973 ps
T802 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.916296272 Jun 27 04:20:10 PM PDT 24 Jun 27 04:20:14 PM PDT 24 186498206 ps
T803 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2964610709 Jun 27 04:19:21 PM PDT 24 Jun 27 04:19:23 PM PDT 24 37525967 ps
T804 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3653753512 Jun 27 04:18:58 PM PDT 24 Jun 27 04:19:00 PM PDT 24 13636271 ps
T805 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2004171400 Jun 27 04:23:22 PM PDT 24 Jun 27 04:23:35 PM PDT 24 393905244 ps
T806 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.106585485 Jun 27 04:19:37 PM PDT 24 Jun 27 04:19:42 PM PDT 24 1428224263 ps
T807 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3707765090 Jun 27 04:21:26 PM PDT 24 Jun 27 04:21:29 PM PDT 24 34227642 ps
T808 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3622915262 Jun 27 04:19:21 PM PDT 24 Jun 27 04:19:22 PM PDT 24 28301672 ps
T809 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1399208575 Jun 27 04:21:06 PM PDT 24 Jun 27 04:21:08 PM PDT 24 36446829 ps
T810 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.62134321 Jun 27 04:21:12 PM PDT 24 Jun 27 04:21:13 PM PDT 24 12006603 ps
T811 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1661218026 Jun 27 04:23:06 PM PDT 24 Jun 27 04:23:09 PM PDT 24 106462507 ps
T41 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.353428225 Jun 27 04:20:39 PM PDT 24 Jun 27 04:20:43 PM PDT 24 103285022 ps
T812 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1718246550 Jun 27 04:22:26 PM PDT 24 Jun 27 04:22:28 PM PDT 24 33432740 ps
T813 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1763713432 Jun 27 04:22:23 PM PDT 24 Jun 27 04:22:25 PM PDT 24 54181115 ps
T814 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3292891323 Jun 27 04:18:07 PM PDT 24 Jun 27 04:18:09 PM PDT 24 15462253 ps
T815 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2229046750 Jun 27 04:21:37 PM PDT 24 Jun 27 04:21:38 PM PDT 24 44379676 ps
T816 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2444048626 Jun 27 04:22:31 PM PDT 24 Jun 27 04:22:34 PM PDT 24 39492541 ps
T817 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1929363028 Jun 27 04:22:48 PM PDT 24 Jun 27 04:22:51 PM PDT 24 188308739 ps
T818 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.680141372 Jun 27 04:22:30 PM PDT 24 Jun 27 04:22:34 PM PDT 24 414080337 ps
T819 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3760300390 Jun 27 04:18:30 PM PDT 24 Jun 27 04:18:32 PM PDT 24 16227709 ps
T820 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3977301930 Jun 27 04:21:53 PM PDT 24 Jun 27 04:21:55 PM PDT 24 50382635 ps
T821 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2939033167 Jun 27 04:23:20 PM PDT 24 Jun 27 04:23:32 PM PDT 24 53510592 ps
T822 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1808999031 Jun 27 04:23:05 PM PDT 24 Jun 27 04:23:09 PM PDT 24 83569250 ps
T823 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2056533515 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:11 PM PDT 24 77122744 ps
T824 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2310102884 Jun 27 04:21:31 PM PDT 24 Jun 27 04:21:32 PM PDT 24 129438176 ps
T72 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2926800278 Jun 27 04:19:24 PM PDT 24 Jun 27 04:19:26 PM PDT 24 49787872 ps
T73 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.194219968 Jun 27 04:20:08 PM PDT 24 Jun 27 04:20:10 PM PDT 24 17244199 ps
T825 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3674972192 Jun 27 04:23:34 PM PDT 24 Jun 27 04:23:49 PM PDT 24 18451499 ps
T84 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.602346310 Jun 27 04:20:23 PM PDT 24 Jun 27 04:20:26 PM PDT 24 357451070 ps
T826 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.484492796 Jun 27 04:19:46 PM PDT 24 Jun 27 04:19:49 PM PDT 24 277493625 ps
T827 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1400513790 Jun 27 04:22:46 PM PDT 24 Jun 27 04:22:49 PM PDT 24 42477815 ps
T828 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.495865516 Jun 27 04:23:39 PM PDT 24 Jun 27 04:23:55 PM PDT 24 1158929831 ps
T829 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3004142555 Jun 27 04:23:38 PM PDT 24 Jun 27 04:23:55 PM PDT 24 156931417 ps
T830 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1974736275 Jun 27 04:21:08 PM PDT 24 Jun 27 04:21:09 PM PDT 24 17471747 ps
T831 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3214087325 Jun 27 04:22:31 PM PDT 24 Jun 27 04:22:34 PM PDT 24 12634989 ps
T832 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2571855738 Jun 27 04:19:12 PM PDT 24 Jun 27 04:19:13 PM PDT 24 16550093 ps
T74 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1628405962 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:33 PM PDT 24 13286572 ps
T833 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2085821536 Jun 27 04:22:32 PM PDT 24 Jun 27 04:22:35 PM PDT 24 531256743 ps
T75 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3017098992 Jun 27 04:22:45 PM PDT 24 Jun 27 04:22:49 PM PDT 24 21581340 ps
T834 /workspace/coverage/cover_reg_top/46.gpio_intr_test.4002752620 Jun 27 04:19:21 PM PDT 24 Jun 27 04:19:22 PM PDT 24 41059759 ps
T835 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3322650418 Jun 27 04:23:39 PM PDT 24 Jun 27 04:23:55 PM PDT 24 49984424 ps
T836 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2496600312 Jun 27 04:18:38 PM PDT 24 Jun 27 04:18:39 PM PDT 24 109304824 ps
T837 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3843569647 Jun 27 04:19:05 PM PDT 24 Jun 27 04:19:07 PM PDT 24 1008857319 ps
T838 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3081335091 Jun 27 04:18:47 PM PDT 24 Jun 27 04:18:51 PM PDT 24 93846789 ps
T839 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1124228033 Jun 27 04:20:46 PM PDT 24 Jun 27 04:20:51 PM PDT 24 80971451 ps
T76 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1680619881 Jun 27 04:22:48 PM PDT 24 Jun 27 04:22:53 PM PDT 24 80675185 ps
T840 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1478847664 Jun 27 04:19:28 PM PDT 24 Jun 27 04:19:30 PM PDT 24 22750107 ps
T841 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3951191628 Jun 27 04:20:03 PM PDT 24 Jun 27 04:20:06 PM PDT 24 445307146 ps
T842 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1605866519 Jun 27 04:19:45 PM PDT 24 Jun 27 04:19:49 PM PDT 24 770114194 ps
T843 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1392934707 Jun 27 04:22:59 PM PDT 24 Jun 27 04:23:01 PM PDT 24 191777187 ps
T844 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2482408382 Jun 27 04:20:58 PM PDT 24 Jun 27 04:20:59 PM PDT 24 16182753 ps
T845 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3287708880 Jun 27 04:22:34 PM PDT 24 Jun 27 04:22:37 PM PDT 24 18571446 ps
T846 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1624180563 Jun 27 04:23:38 PM PDT 24 Jun 27 04:23:57 PM PDT 24 114788791 ps
T847 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2639259360 Jun 27 04:23:34 PM PDT 24 Jun 27 04:23:49 PM PDT 24 68192578 ps
T848 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4199563781 Jun 27 04:20:10 PM PDT 24 Jun 27 04:20:13 PM PDT 24 69697776 ps
T849 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3898423681 Jun 27 04:23:26 PM PDT 24 Jun 27 04:23:39 PM PDT 24 143442074 ps
T850 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2381799089 Jun 27 04:20:54 PM PDT 24 Jun 27 04:20:56 PM PDT 24 172486156 ps
T851 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1220080499 Jun 27 04:22:39 PM PDT 24 Jun 27 04:22:41 PM PDT 24 199930296 ps
T852 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1765784973 Jun 27 04:20:16 PM PDT 24 Jun 27 04:20:19 PM PDT 24 111046562 ps
T853 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.859334199 Jun 27 04:23:25 PM PDT 24 Jun 27 04:23:39 PM PDT 24 142730923 ps
T854 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3263029538 Jun 27 04:22:53 PM PDT 24 Jun 27 04:22:55 PM PDT 24 56097901 ps
T855 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1078146835 Jun 27 04:23:35 PM PDT 24 Jun 27 04:23:51 PM PDT 24 135917244 ps
T856 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3797832689 Jun 27 04:21:40 PM PDT 24 Jun 27 04:21:42 PM PDT 24 263306681 ps
T857 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2516679313 Jun 27 04:19:53 PM PDT 24 Jun 27 04:19:55 PM PDT 24 107324464 ps
T858 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2659201029 Jun 27 04:20:37 PM PDT 24 Jun 27 04:20:41 PM PDT 24 285872726 ps
T859 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.485148605 Jun 27 04:21:44 PM PDT 24 Jun 27 04:21:46 PM PDT 24 78552710 ps
T860 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2236565750 Jun 27 04:19:47 PM PDT 24 Jun 27 04:19:49 PM PDT 24 60693940 ps
T861 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2150187799 Jun 27 04:23:26 PM PDT 24 Jun 27 04:23:40 PM PDT 24 63636513 ps
T862 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.541847946 Jun 27 04:20:56 PM PDT 24 Jun 27 04:20:59 PM PDT 24 280728301 ps
T863 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.963834626 Jun 27 04:20:56 PM PDT 24 Jun 27 04:20:58 PM PDT 24 162227199 ps
T864 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1107098461 Jun 27 04:22:38 PM PDT 24 Jun 27 04:22:40 PM PDT 24 60973302 ps
T865 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1343205843 Jun 27 04:23:33 PM PDT 24 Jun 27 04:23:49 PM PDT 24 213723630 ps
T866 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3334783777 Jun 27 04:20:56 PM PDT 24 Jun 27 04:20:58 PM PDT 24 158522247 ps
T867 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.991708969 Jun 27 04:22:40 PM PDT 24 Jun 27 04:22:44 PM PDT 24 38537947 ps
T868 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.472582277 Jun 27 04:23:34 PM PDT 24 Jun 27 04:23:50 PM PDT 24 110244921 ps
T869 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2163160991 Jun 27 04:20:15 PM PDT 24 Jun 27 04:20:18 PM PDT 24 167148410 ps
T870 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1421322575 Jun 27 04:20:21 PM PDT 24 Jun 27 04:20:24 PM PDT 24 48575206 ps
T871 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.422416976 Jun 27 04:23:26 PM PDT 24 Jun 27 04:23:39 PM PDT 24 34186004 ps
T872 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2874908127 Jun 27 04:20:15 PM PDT 24 Jun 27 04:20:17 PM PDT 24 231789685 ps
T873 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3603856350 Jun 27 04:19:06 PM PDT 24 Jun 27 04:19:08 PM PDT 24 55927788 ps
T874 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3725836060 Jun 27 04:23:49 PM PDT 24 Jun 27 04:24:02 PM PDT 24 67365002 ps
T875 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3197684601 Jun 27 04:20:34 PM PDT 24 Jun 27 04:20:36 PM PDT 24 192238007 ps
T876 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1570769541 Jun 27 04:22:39 PM PDT 24 Jun 27 04:22:41 PM PDT 24 234271194 ps
T877 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3483629764 Jun 27 04:23:33 PM PDT 24 Jun 27 04:23:49 PM PDT 24 106775586 ps
T878 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702732767 Jun 27 04:22:38 PM PDT 24 Jun 27 04:22:40 PM PDT 24 188495674 ps
T879 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3639611059 Jun 27 04:22:53 PM PDT 24 Jun 27 04:22:55 PM PDT 24 133729509 ps
T880 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.600955163 Jun 27 04:19:52 PM PDT 24 Jun 27 04:19:55 PM PDT 24 65703841 ps
T881 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4268443937 Jun 27 04:20:00 PM PDT 24 Jun 27 04:20:02 PM PDT 24 45423471 ps
T882 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2873558425 Jun 27 04:23:34 PM PDT 24 Jun 27 04:23:49 PM PDT 24 33604521 ps
T883 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4039442798 Jun 27 04:23:30 PM PDT 24 Jun 27 04:23:45 PM PDT 24 47683758 ps
T884 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2938267437 Jun 27 04:23:38 PM PDT 24 Jun 27 04:23:55 PM PDT 24 80352168 ps
T885 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.137796963 Jun 27 04:20:33 PM PDT 24 Jun 27 04:20:35 PM PDT 24 59668157 ps
T886 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1199146941 Jun 27 04:19:25 PM PDT 24 Jun 27 04:19:28 PM PDT 24 235964249 ps
T887 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1732267627 Jun 27 04:23:33 PM PDT 24 Jun 27 04:23:48 PM PDT 24 48081138 ps
T888 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.819634300 Jun 27 04:23:17 PM PDT 24 Jun 27 04:23:27 PM PDT 24 90783599 ps
T889 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2456899480 Jun 27 04:20:21 PM PDT 24 Jun 27 04:20:24 PM PDT 24 53115678 ps
T890 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3753827591 Jun 27 04:19:42 PM PDT 24 Jun 27 04:19:45 PM PDT 24 58179902 ps
T891 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1582565781 Jun 27 04:22:56 PM PDT 24 Jun 27 04:22:57 PM PDT 24 260602898 ps
T892 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1951408223 Jun 27 04:23:26 PM PDT 24 Jun 27 04:23:39 PM PDT 24 120957585 ps
T893 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2929278224 Jun 27 04:19:21 PM PDT 24 Jun 27 04:19:23 PM PDT 24 29893481 ps
T894 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.489438199 Jun 27 04:21:59 PM PDT 24 Jun 27 04:22:01 PM PDT 24 59973061 ps
T895 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.569478204 Jun 27 04:23:27 PM PDT 24 Jun 27 04:23:41 PM PDT 24 65661372 ps
T896 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1389350813 Jun 27 04:23:26 PM PDT 24 Jun 27 04:23:39 PM PDT 24 70393400 ps
T897 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2613723216 Jun 27 04:23:24 PM PDT 24 Jun 27 04:23:37 PM PDT 24 113843711 ps
T898 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3697565096 Jun 27 04:20:06 PM PDT 24 Jun 27 04:20:09 PM PDT 24 243077482 ps
T899 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.517782910 Jun 27 04:22:39 PM PDT 24 Jun 27 04:22:42 PM PDT 24 60831874 ps
T900 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3261910424 Jun 27 04:22:41 PM PDT 24 Jun 27 04:22:46 PM PDT 24 142083190 ps
T901 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2877914033 Jun 27 04:20:15 PM PDT 24 Jun 27 04:20:18 PM PDT 24 41031371 ps
T902 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2157736053 Jun 27 04:19:26 PM PDT 24 Jun 27 04:19:28 PM PDT 24 61683269 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3549932608 Jun 27 04:19:21 PM PDT 24 Jun 27 04:19:23 PM PDT 24 250709474 ps
T904 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.429601654 Jun 27 04:21:52 PM PDT 24 Jun 27 04:21:55 PM PDT 24 85571199 ps
T905 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3577225985 Jun 27 04:23:33 PM PDT 24 Jun 27 04:23:47 PM PDT 24 24956892 ps
T906 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2786294920 Jun 27 04:19:52 PM PDT 24 Jun 27 04:19:55 PM PDT 24 52121595 ps
T907 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3663112754 Jun 27 04:21:52 PM PDT 24 Jun 27 04:21:55 PM PDT 24 175647845 ps
T908 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1713575417 Jun 27 04:22:41 PM PDT 24 Jun 27 04:22:46 PM PDT 24 42112963 ps
T909 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1411022168 Jun 27 04:21:42 PM PDT 24 Jun 27 04:21:44 PM PDT 24 38634897 ps
T910 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3288794959 Jun 27 04:21:18 PM PDT 24 Jun 27 04:21:19 PM PDT 24 135089876 ps
T911 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4145018070 Jun 27 04:23:08 PM PDT 24 Jun 27 04:23:14 PM PDT 24 72013704 ps
T912 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2538266488 Jun 27 04:21:19 PM PDT 24 Jun 27 04:21:21 PM PDT 24 263140475 ps
T913 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3350747428 Jun 27 04:23:36 PM PDT 24 Jun 27 04:23:52 PM PDT 24 369113205 ps
T914 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2071254030 Jun 27 04:23:38 PM PDT 24 Jun 27 04:23:54 PM PDT 24 37783213 ps
T915 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3884752486 Jun 27 04:23:16 PM PDT 24 Jun 27 04:23:25 PM PDT 24 339225584 ps
T916 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.755378159 Jun 27 04:23:17 PM PDT 24 Jun 27 04:23:26 PM PDT 24 27001157 ps
T917 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2509645346 Jun 27 04:23:18 PM PDT 24 Jun 27 04:23:29 PM PDT 24 249791586 ps
T918 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.83510095 Jun 27 04:23:30 PM PDT 24 Jun 27 04:23:44 PM PDT 24 83180541 ps
T919 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.815738759 Jun 27 04:23:25 PM PDT 24 Jun 27 04:23:39 PM PDT 24 623510140 ps
T920 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2554910119 Jun 27 04:23:33 PM PDT 24 Jun 27 04:23:47 PM PDT 24 109378031 ps
T921 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.185176180 Jun 27 04:22:56 PM PDT 24 Jun 27 04:22:58 PM PDT 24 53473414 ps
T922 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1401093020 Jun 27 04:23:17 PM PDT 24 Jun 27 04:23:27 PM PDT 24 67219187 ps
T923 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.804754229 Jun 27 04:20:23 PM PDT 24 Jun 27 04:20:26 PM PDT 24 156476927 ps
T924 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.17355049 Jun 27 04:19:48 PM PDT 24 Jun 27 04:19:49 PM PDT 24 198738445 ps
T925 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1366555848 Jun 27 04:22:53 PM PDT 24 Jun 27 04:22:55 PM PDT 24 77695074 ps
T926 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1476140605 Jun 27 04:22:27 PM PDT 24 Jun 27 04:22:30 PM PDT 24 59428889 ps
T927 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3393754572 Jun 27 04:21:18 PM PDT 24 Jun 27 04:21:20 PM PDT 24 89356928 ps
T928 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3334385613 Jun 27 04:20:15 PM PDT 24 Jun 27 04:20:18 PM PDT 24 839905082 ps
T929 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2845293442 Jun 27 04:20:36 PM PDT 24 Jun 27 04:20:40 PM PDT 24 191335112 ps
T930 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.220505235 Jun 27 04:22:39 PM PDT 24 Jun 27 04:22:41 PM PDT 24 42856962 ps
T931 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4259479169 Jun 27 04:23:24 PM PDT 24 Jun 27 04:23:37 PM PDT 24 184711348 ps
T932 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.871083904 Jun 27 04:23:33 PM PDT 24 Jun 27 04:23:47 PM PDT 24 35430009 ps
T933 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.12788398 Jun 27 04:23:38 PM PDT 24 Jun 27 04:23:55 PM PDT 24 51691703 ps
T934 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2877583021 Jun 27 04:23:33 PM PDT 24 Jun 27 04:23:47 PM PDT 24 37945921 ps
T935 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3718718435 Jun 27 04:23:26 PM PDT 24 Jun 27 04:23:39 PM PDT 24 29852431 ps
T936 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3012356122 Jun 27 04:20:54 PM PDT 24 Jun 27 04:20:56 PM PDT 24 324328550 ps
T937 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.286963177 Jun 27 04:23:24 PM PDT 24 Jun 27 04:23:37 PM PDT 24 32971158 ps
T938 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2658037414 Jun 27 04:23:38 PM PDT 24 Jun 27 04:23:55 PM PDT 24 178912928 ps
T939 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.319567004 Jun 27 04:20:10 PM PDT 24 Jun 27 04:20:13 PM PDT 24 171310992 ps
T940 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3644107039 Jun 27 04:22:56 PM PDT 24 Jun 27 04:22:58 PM PDT 24 285585762 ps
T941 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3445466608 Jun 27 04:20:23 PM PDT 24 Jun 27 04:20:26 PM PDT 24 78049368 ps
T942 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3459952654 Jun 27 04:23:38 PM PDT 24 Jun 27 04:23:54 PM PDT 24 106621248 ps
T943 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3054813279 Jun 27 04:22:39 PM PDT 24 Jun 27 04:22:42 PM PDT 24 50076765 ps
T944 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1940258802 Jun 27 04:19:45 PM PDT 24 Jun 27 04:19:47 PM PDT 24 83924276 ps
T945 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4221449390 Jun 27 04:21:26 PM PDT 24 Jun 27 04:21:28 PM PDT 24 24968405 ps
T946 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.714122490 Jun 27 04:20:05 PM PDT 24 Jun 27 04:20:07 PM PDT 24 81723912 ps

Test location /workspace/coverage/default/11.gpio_stress_all.2292484918
Short name T1
Test name
Test status
Simulation time 13515075825 ps
CPU time 136.7 seconds
Started Jun 27 04:23:27 PM PDT 24
Finished Jun 27 04:25:57 PM PDT 24
Peak memory 198428 kb
Host smart-5898ad30-e860-46b5-b362-d907f36633e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292484918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2292484918
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2962807897
Short name T18
Test name
Test status
Simulation time 94980045 ps
CPU time 1.88 seconds
Started Jun 27 04:23:23 PM PDT 24
Finished Jun 27 04:23:37 PM PDT 24
Peak memory 197484 kb
Host smart-461354e6-7c24-4ffe-bd97-e808dd14cb50
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962807897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2962807897
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1126225685
Short name T44
Test name
Test status
Simulation time 44573185259 ps
CPU time 824.48 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:37:04 PM PDT 24
Peak memory 198540 kb
Host smart-dce714e5-d6ba-40ee-8004-1622a93804d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1126225685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1126225685
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2103788496
Short name T21
Test name
Test status
Simulation time 143125367 ps
CPU time 0.83 seconds
Started Jun 27 04:20:58 PM PDT 24
Finished Jun 27 04:21:00 PM PDT 24
Peak memory 214036 kb
Host smart-954c35f8-e184-4626-9be2-1a62cc76db7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103788496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2103788496
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.194219968
Short name T73
Test name
Test status
Simulation time 17244199 ps
CPU time 0.7 seconds
Started Jun 27 04:20:08 PM PDT 24
Finished Jun 27 04:20:10 PM PDT 24
Peak memory 195092 kb
Host smart-7599544b-d859-42a7-a1f8-890510d6d7de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194219968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.194219968
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3111659671
Short name T38
Test name
Test status
Simulation time 84377563 ps
CPU time 1.08 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:33 PM PDT 24
Peak memory 198512 kb
Host smart-749ba68d-6409-4ced-93fe-00e6d3fcaa5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111659671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3111659671
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2170344566
Short name T62
Test name
Test status
Simulation time 18928913 ps
CPU time 0.85 seconds
Started Jun 27 04:21:12 PM PDT 24
Finished Jun 27 04:21:13 PM PDT 24
Peak memory 196744 kb
Host smart-4efe4687-146d-4e44-872b-66391e3fe890
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170344566 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2170344566
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.gpio_alert_test.346591809
Short name T35
Test name
Test status
Simulation time 12220938 ps
CPU time 0.54 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 195088 kb
Host smart-8c541a06-bbec-4352-8b16-d61e39c06596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346591809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.346591809
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.159718750
Short name T28
Test name
Test status
Simulation time 355269351 ps
CPU time 1.38 seconds
Started Jun 27 04:23:06 PM PDT 24
Finished Jun 27 04:23:10 PM PDT 24
Peak memory 197756 kb
Host smart-d3b6f487-c8ba-4645-9695-17065a25df82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159718750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.159718750
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3707765090
Short name T807
Test name
Test status
Simulation time 34227642 ps
CPU time 0.91 seconds
Started Jun 27 04:21:26 PM PDT 24
Finished Jun 27 04:21:29 PM PDT 24
Peak memory 196808 kb
Host smart-62f9f371-adff-4475-908b-bb63669c6a68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707765090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3707765090
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3081335091
Short name T838
Test name
Test status
Simulation time 93846789 ps
CPU time 3 seconds
Started Jun 27 04:18:47 PM PDT 24
Finished Jun 27 04:18:51 PM PDT 24
Peak memory 197700 kb
Host smart-0a7fade6-3172-4df4-ad3f-30bfba041d5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081335091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3081335091
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2506171705
Short name T752
Test name
Test status
Simulation time 15559643 ps
CPU time 0.57 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:33 PM PDT 24
Peak memory 194884 kb
Host smart-a1b34f19-30ec-4ea8-9127-1305aca4b340
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506171705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2506171705
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1808999031
Short name T822
Test name
Test status
Simulation time 83569250 ps
CPU time 1.05 seconds
Started Jun 27 04:23:05 PM PDT 24
Finished Jun 27 04:23:09 PM PDT 24
Peak memory 197428 kb
Host smart-ef49c7e5-6641-49bd-bb45-3143ca8456e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808999031 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1808999031
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3017098992
Short name T75
Test name
Test status
Simulation time 21581340 ps
CPU time 0.6 seconds
Started Jun 27 04:22:45 PM PDT 24
Finished Jun 27 04:22:49 PM PDT 24
Peak memory 194876 kb
Host smart-c19f1e11-f178-4086-a13c-1a3593493947
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017098992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3017098992
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3055821995
Short name T746
Test name
Test status
Simulation time 56167215 ps
CPU time 0.63 seconds
Started Jun 27 04:19:37 PM PDT 24
Finished Jun 27 04:19:39 PM PDT 24
Peak memory 193552 kb
Host smart-dcb7a390-63fd-4e84-aab5-92041ad885f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055821995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3055821995
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.680141372
Short name T818
Test name
Test status
Simulation time 414080337 ps
CPU time 2.26 seconds
Started Jun 27 04:22:30 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 197740 kb
Host smart-13f4cae5-0865-47b3-852e-c3dbfcd6b85f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680141372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.680141372
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3176160491
Short name T70
Test name
Test status
Simulation time 34266840 ps
CPU time 0.82 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 196672 kb
Host smart-a4a47ed6-0a00-461c-8cd4-f7049c60f872
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176160491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3176160491
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1680619881
Short name T76
Test name
Test status
Simulation time 80675185 ps
CPU time 2.9 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:53 PM PDT 24
Peak memory 198516 kb
Host smart-515e466d-eb95-4581-80cb-a947cd7a055c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680619881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1680619881
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.968353888
Short name T782
Test name
Test status
Simulation time 73913455 ps
CPU time 0.64 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:34 PM PDT 24
Peak memory 195188 kb
Host smart-5e007bfc-cb06-4ed4-91e6-7b1de2b6df7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968353888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.968353888
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.74113180
Short name T791
Test name
Test status
Simulation time 32520352 ps
CPU time 1.42 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:34 PM PDT 24
Peak memory 198260 kb
Host smart-1aaacb46-7187-41ac-a297-7c8183ea35b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74113180 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.74113180
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2415584616
Short name T71
Test name
Test status
Simulation time 55673288 ps
CPU time 0.66 seconds
Started Jun 27 04:19:39 PM PDT 24
Finished Jun 27 04:19:40 PM PDT 24
Peak memory 195568 kb
Host smart-c2cff7f2-d1ce-4b25-97d9-16df6443486d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415584616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2415584616
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2728530629
Short name T766
Test name
Test status
Simulation time 13160819 ps
CPU time 0.54 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 194048 kb
Host smart-84c476c6-ab87-42b4-8b46-d8e25df06045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728530629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2728530629
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3287708880
Short name T845
Test name
Test status
Simulation time 18571446 ps
CPU time 0.72 seconds
Started Jun 27 04:22:34 PM PDT 24
Finished Jun 27 04:22:37 PM PDT 24
Peak memory 194464 kb
Host smart-4ccf2544-6eee-4944-8106-70499be6f90b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287708880 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3287708880
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3843569647
Short name T837
Test name
Test status
Simulation time 1008857319 ps
CPU time 1.61 seconds
Started Jun 27 04:19:05 PM PDT 24
Finished Jun 27 04:19:07 PM PDT 24
Peak memory 198560 kb
Host smart-07a33657-cd04-4983-b0e8-c8273fe97fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843569647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3843569647
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1929363028
Short name T817
Test name
Test status
Simulation time 188308739 ps
CPU time 0.79 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 197616 kb
Host smart-c4114c6d-dd4d-46b6-90c7-a05dd4886ab0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929363028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1929363028
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.884413408
Short name T739
Test name
Test status
Simulation time 29921379 ps
CPU time 0.76 seconds
Started Jun 27 04:21:29 PM PDT 24
Finished Jun 27 04:21:31 PM PDT 24
Peak memory 198360 kb
Host smart-f85c4ed6-fd6b-43f0-9e69-84c524ada4a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884413408 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.884413408
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.482195283
Short name T736
Test name
Test status
Simulation time 42969804 ps
CPU time 0.63 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:11 PM PDT 24
Peak memory 195060 kb
Host smart-7fdcb7e3-781a-40bc-b7a3-78be303b0e28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482195283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.482195283
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3214087325
Short name T831
Test name
Test status
Simulation time 12634989 ps
CPU time 0.65 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 192328 kb
Host smart-882ee088-e165-40e4-93c0-620e87604aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214087325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3214087325
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.972936626
Short name T783
Test name
Test status
Simulation time 33803972 ps
CPU time 0.86 seconds
Started Jun 27 04:21:24 PM PDT 24
Finished Jun 27 04:21:26 PM PDT 24
Peak memory 196932 kb
Host smart-ddd14d68-75ca-4bb1-87e8-a19d08633a1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972936626 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.972936626
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1387828502
Short name T799
Test name
Test status
Simulation time 168605798 ps
CPU time 2.52 seconds
Started Jun 27 04:19:16 PM PDT 24
Finished Jun 27 04:19:19 PM PDT 24
Peak memory 198564 kb
Host smart-a54bd275-2a9b-4956-af82-2c245e2280c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387828502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1387828502
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1274243334
Short name T29
Test name
Test status
Simulation time 86298310 ps
CPU time 1.11 seconds
Started Jun 27 04:22:32 PM PDT 24
Finished Jun 27 04:22:35 PM PDT 24
Peak memory 198192 kb
Host smart-8ecf0810-e0cf-4da8-818b-b23555a1cbb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274243334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1274243334
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2359596291
Short name T763
Test name
Test status
Simulation time 166822349 ps
CPU time 0.92 seconds
Started Jun 27 04:18:27 PM PDT 24
Finished Jun 27 04:18:29 PM PDT 24
Peak memory 198444 kb
Host smart-3fd91732-1b3f-4c9d-95ab-d3c8c66fb69e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359596291 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2359596291
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.911883404
Short name T778
Test name
Test status
Simulation time 16039041 ps
CPU time 0.64 seconds
Started Jun 27 04:22:46 PM PDT 24
Finished Jun 27 04:22:50 PM PDT 24
Peak memory 195368 kb
Host smart-0384287b-f765-4c48-aa40-e31dc265f62a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911883404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.911883404
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3972005943
Short name T774
Test name
Test status
Simulation time 32454288 ps
CPU time 0.6 seconds
Started Jun 27 04:22:32 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 193136 kb
Host smart-ce26a4ea-bf51-4f52-80a8-4c153ce470a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972005943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3972005943
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1661218026
Short name T811
Test name
Test status
Simulation time 106462507 ps
CPU time 0.76 seconds
Started Jun 27 04:23:06 PM PDT 24
Finished Jun 27 04:23:09 PM PDT 24
Peak memory 195996 kb
Host smart-1f1cafe4-92a0-41a6-9d48-b4ecde1ca65d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661218026 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1661218026
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1599968787
Short name T737
Test name
Test status
Simulation time 130699873 ps
CPU time 2.09 seconds
Started Jun 27 04:18:48 PM PDT 24
Finished Jun 27 04:18:51 PM PDT 24
Peak memory 198564 kb
Host smart-4d30aba4-99f0-4598-beb3-dd40904e9039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599968787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1599968787
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.353428225
Short name T41
Test name
Test status
Simulation time 103285022 ps
CPU time 0.87 seconds
Started Jun 27 04:20:39 PM PDT 24
Finished Jun 27 04:20:43 PM PDT 24
Peak memory 197464 kb
Host smart-f4b8099f-fb09-4b6f-bab2-2a7476770194
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353428225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.353428225
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.899855475
Short name T733
Test name
Test status
Simulation time 58333168 ps
CPU time 0.8 seconds
Started Jun 27 04:22:32 PM PDT 24
Finished Jun 27 04:22:35 PM PDT 24
Peak memory 197824 kb
Host smart-85adb295-5872-499c-8691-de4eff7ec85d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899855475 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.899855475
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3435908157
Short name T771
Test name
Test status
Simulation time 45196242 ps
CPU time 0.67 seconds
Started Jun 27 04:19:50 PM PDT 24
Finished Jun 27 04:19:51 PM PDT 24
Peak memory 195608 kb
Host smart-1f993373-3e4d-4683-a378-5c2ffbb75fc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435908157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3435908157
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2923285404
Short name T720
Test name
Test status
Simulation time 12987215 ps
CPU time 0.56 seconds
Started Jun 27 04:18:28 PM PDT 24
Finished Jun 27 04:18:29 PM PDT 24
Peak memory 194260 kb
Host smart-1d7f3eca-fe7b-41c1-99cb-7ce7c75d1ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923285404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2923285404
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2773161477
Short name T79
Test name
Test status
Simulation time 42729772 ps
CPU time 0.66 seconds
Started Jun 27 04:21:05 PM PDT 24
Finished Jun 27 04:21:07 PM PDT 24
Peak memory 195508 kb
Host smart-6ded3048-43cf-4402-8684-50e433e81bb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773161477 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2773161477
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3900752694
Short name T790
Test name
Test status
Simulation time 53266455 ps
CPU time 2.88 seconds
Started Jun 27 04:21:40 PM PDT 24
Finished Jun 27 04:21:44 PM PDT 24
Peak memory 198656 kb
Host smart-dad257c8-ee62-465f-8369-a647b9030f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900752694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3900752694
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2359342816
Short name T785
Test name
Test status
Simulation time 41587690 ps
CPU time 0.81 seconds
Started Jun 27 04:21:41 PM PDT 24
Finished Jun 27 04:21:43 PM PDT 24
Peak memory 197836 kb
Host smart-a211d277-dcfb-485b-b889-669f40898761
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359342816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2359342816
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3292891323
Short name T814
Test name
Test status
Simulation time 15462253 ps
CPU time 0.74 seconds
Started Jun 27 04:18:07 PM PDT 24
Finished Jun 27 04:18:09 PM PDT 24
Peak memory 197688 kb
Host smart-8b26222b-4c5a-4613-91db-bb7ccd48862d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292891323 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3292891323
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1906171435
Short name T777
Test name
Test status
Simulation time 13646946 ps
CPU time 0.58 seconds
Started Jun 27 04:21:52 PM PDT 24
Finished Jun 27 04:21:53 PM PDT 24
Peak memory 194256 kb
Host smart-9b5ea7a7-d28f-44d4-b476-5d60b75ce847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906171435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1906171435
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1392934707
Short name T843
Test name
Test status
Simulation time 191777187 ps
CPU time 0.92 seconds
Started Jun 27 04:22:59 PM PDT 24
Finished Jun 27 04:23:01 PM PDT 24
Peak memory 196040 kb
Host smart-bd4867d0-5533-43ee-846d-cc065eb19e97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392934707 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1392934707
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.818869674
Short name T753
Test name
Test status
Simulation time 47538585 ps
CPU time 2.44 seconds
Started Jun 27 04:21:08 PM PDT 24
Finished Jun 27 04:21:12 PM PDT 24
Peak memory 198636 kb
Host smart-64fe8a88-ddeb-4941-a5d6-e03863c1d131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818869674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.818869674
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2056533515
Short name T823
Test name
Test status
Simulation time 77122744 ps
CPU time 0.82 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:11 PM PDT 24
Peak memory 197776 kb
Host smart-7534021b-8203-4cce-819c-37bada0ae941
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056533515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2056533515
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2230117678
Short name T786
Test name
Test status
Simulation time 57923917 ps
CPU time 1.26 seconds
Started Jun 27 04:19:37 PM PDT 24
Finished Jun 27 04:19:39 PM PDT 24
Peak memory 198560 kb
Host smart-28b7f8b5-fe6e-43ab-b397-60d07bb10eab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230117678 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2230117678
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.734470032
Short name T775
Test name
Test status
Simulation time 28399856 ps
CPU time 0.64 seconds
Started Jun 27 04:21:01 PM PDT 24
Finished Jun 27 04:21:02 PM PDT 24
Peak memory 195188 kb
Host smart-253ef551-53e7-42cf-851e-8d6cc1a994e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734470032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.734470032
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2571855738
Short name T832
Test name
Test status
Simulation time 16550093 ps
CPU time 0.59 seconds
Started Jun 27 04:19:12 PM PDT 24
Finished Jun 27 04:19:13 PM PDT 24
Peak memory 194316 kb
Host smart-fdae2594-768c-47a1-86e5-6a84732cd31a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571855738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2571855738
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2496600312
Short name T836
Test name
Test status
Simulation time 109304824 ps
CPU time 0.76 seconds
Started Jun 27 04:18:38 PM PDT 24
Finished Jun 27 04:18:39 PM PDT 24
Peak memory 196884 kb
Host smart-51d51b42-5967-4f3a-bc73-5a83e93101b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496600312 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2496600312
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1924683882
Short name T719
Test name
Test status
Simulation time 152553385 ps
CPU time 2.89 seconds
Started Jun 27 04:23:06 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 197232 kb
Host smart-224e9b31-54fb-4cdb-95fb-08dca18201a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924683882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1924683882
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2095146193
Short name T723
Test name
Test status
Simulation time 22671224 ps
CPU time 0.73 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 195224 kb
Host smart-54d6b2b2-6f07-436d-97c3-41ca6e5a9bd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095146193 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2095146193
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2226413487
Short name T787
Test name
Test status
Simulation time 11390227 ps
CPU time 0.63 seconds
Started Jun 27 04:20:08 PM PDT 24
Finished Jun 27 04:20:10 PM PDT 24
Peak memory 195212 kb
Host smart-86abc110-0396-42e8-8085-badb228e5738
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226413487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2226413487
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4098276253
Short name T798
Test name
Test status
Simulation time 42331778 ps
CPU time 0.64 seconds
Started Jun 27 04:21:22 PM PDT 24
Finished Jun 27 04:21:23 PM PDT 24
Peak memory 194736 kb
Host smart-26b9f8eb-caaa-4de8-8433-932931ac785a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098276253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4098276253
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.643242264
Short name T788
Test name
Test status
Simulation time 147114486 ps
CPU time 0.87 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:35 PM PDT 24
Peak memory 196860 kb
Host smart-304ef358-0561-42c2-9dc9-efd55d61d450
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643242264 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.643242264
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2964610709
Short name T803
Test name
Test status
Simulation time 37525967 ps
CPU time 1.12 seconds
Started Jun 27 04:19:21 PM PDT 24
Finished Jun 27 04:19:23 PM PDT 24
Peak memory 198776 kb
Host smart-fbf490a9-8ed0-4edb-bb7d-2bc500f1de17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964610709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2964610709
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2879554557
Short name T36
Test name
Test status
Simulation time 215291272 ps
CPU time 1.42 seconds
Started Jun 27 04:18:49 PM PDT 24
Finished Jun 27 04:18:51 PM PDT 24
Peak memory 198520 kb
Host smart-f6adde35-d5f9-4a5e-b1cb-c67eda84fa84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879554557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2879554557
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1959519651
Short name T721
Test name
Test status
Simulation time 71704982 ps
CPU time 0.87 seconds
Started Jun 27 04:23:06 PM PDT 24
Finished Jun 27 04:23:10 PM PDT 24
Peak memory 198120 kb
Host smart-df794058-4344-4522-804d-ca802f3a25ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959519651 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1959519651
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2918319220
Short name T60
Test name
Test status
Simulation time 12256653 ps
CPU time 0.63 seconds
Started Jun 27 04:19:21 PM PDT 24
Finished Jun 27 04:19:22 PM PDT 24
Peak memory 195516 kb
Host smart-064097b0-4df7-488a-810b-8e945d7b34da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918319220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2918319220
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3669370972
Short name T779
Test name
Test status
Simulation time 146322866 ps
CPU time 0.67 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 192856 kb
Host smart-9c268e56-ac21-4c56-8bef-9a91cf14674e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669370972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3669370972
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2885738826
Short name T77
Test name
Test status
Simulation time 64782804 ps
CPU time 0.81 seconds
Started Jun 27 04:19:39 PM PDT 24
Finished Jun 27 04:19:41 PM PDT 24
Peak memory 196796 kb
Host smart-3672241a-0867-4de2-a721-2cff5a184d53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885738826 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2885738826
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1763713432
Short name T813
Test name
Test status
Simulation time 54181115 ps
CPU time 1.27 seconds
Started Jun 27 04:22:23 PM PDT 24
Finished Jun 27 04:22:25 PM PDT 24
Peak memory 198272 kb
Host smart-f3dc3e9a-8bbd-4b87-b8b3-9005c0d50cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763713432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1763713432
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2085821536
Short name T833
Test name
Test status
Simulation time 531256743 ps
CPU time 1.32 seconds
Started Jun 27 04:22:32 PM PDT 24
Finished Jun 27 04:22:35 PM PDT 24
Peak memory 198148 kb
Host smart-dac44180-14b4-49c5-8ab3-de138b6a247a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085821536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2085821536
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1399208575
Short name T809
Test name
Test status
Simulation time 36446829 ps
CPU time 1.06 seconds
Started Jun 27 04:21:06 PM PDT 24
Finished Jun 27 04:21:08 PM PDT 24
Peak memory 198468 kb
Host smart-c209e2ef-c36d-4450-964c-da7af8878487
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399208575 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1399208575
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1642907565
Short name T781
Test name
Test status
Simulation time 42222516 ps
CPU time 0.56 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:54 PM PDT 24
Peak memory 194764 kb
Host smart-f53eaa85-05a1-4a40-8291-6d351c73659b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642907565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1642907565
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2149736902
Short name T738
Test name
Test status
Simulation time 21371362 ps
CPU time 0.58 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 194616 kb
Host smart-49fd4161-6487-4166-b4be-e1ae42d9096c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149736902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2149736902
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3597001306
Short name T64
Test name
Test status
Simulation time 111962171 ps
CPU time 0.74 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:28 PM PDT 24
Peak memory 196344 kb
Host smart-831df76e-d9a0-445f-b90b-c71d97dcb61a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597001306 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3597001306
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3704149872
Short name T741
Test name
Test status
Simulation time 800040604 ps
CPU time 2.88 seconds
Started Jun 27 04:18:35 PM PDT 24
Finished Jun 27 04:18:39 PM PDT 24
Peak memory 198956 kb
Host smart-2c8586c7-8a09-4613-9a70-60c5185dc615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704149872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3704149872
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2144268839
Short name T85
Test name
Test status
Simulation time 141321136 ps
CPU time 0.91 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:29 PM PDT 24
Peak memory 197548 kb
Host smart-94589868-5132-4baa-b7b0-bde7f2974630
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144268839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2144268839
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2969823496
Short name T759
Test name
Test status
Simulation time 46699304 ps
CPU time 0.99 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 198064 kb
Host smart-61f92f27-bdce-4448-b7ac-97a9029a4459
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969823496 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2969823496
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2509757991
Short name T765
Test name
Test status
Simulation time 14141980 ps
CPU time 0.61 seconds
Started Jun 27 04:21:06 PM PDT 24
Finished Jun 27 04:21:08 PM PDT 24
Peak memory 195108 kb
Host smart-05695807-e7ea-4f2c-83cf-2bdccc126061
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509757991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2509757991
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3674972192
Short name T825
Test name
Test status
Simulation time 18451499 ps
CPU time 0.57 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 193992 kb
Host smart-0fd43c17-a8d6-4e7a-a189-5454048e0e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674972192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3674972192
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1718246550
Short name T812
Test name
Test status
Simulation time 33432740 ps
CPU time 0.76 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:28 PM PDT 24
Peak memory 196928 kb
Host smart-c94babdd-3c0e-40d3-a668-17b8fe675037
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718246550 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1718246550
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1148610545
Short name T731
Test name
Test status
Simulation time 156741946 ps
CPU time 1.11 seconds
Started Jun 27 04:18:12 PM PDT 24
Finished Jun 27 04:18:14 PM PDT 24
Peak memory 198388 kb
Host smart-641f86ee-b215-47fd-9fb2-ff761c849ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148610545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1148610545
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.495865516
Short name T828
Test name
Test status
Simulation time 1158929831 ps
CPU time 1.05 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 197124 kb
Host smart-7929ff94-68e2-4120-911d-a7c64399fe98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495865516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.495865516
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3094272081
Short name T727
Test name
Test status
Simulation time 30451548 ps
CPU time 1.3 seconds
Started Jun 27 04:18:36 PM PDT 24
Finished Jun 27 04:18:38 PM PDT 24
Peak memory 198628 kb
Host smart-6038f730-e7b0-47f2-8e77-4126c6297ba3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094272081 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3094272081
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3322650418
Short name T835
Test name
Test status
Simulation time 49984424 ps
CPU time 0.6 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 194080 kb
Host smart-bf0140df-d7b9-4dcc-9638-8003883310df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322650418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3322650418
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2229046750
Short name T815
Test name
Test status
Simulation time 44379676 ps
CPU time 0.62 seconds
Started Jun 27 04:21:37 PM PDT 24
Finished Jun 27 04:21:38 PM PDT 24
Peak memory 194324 kb
Host smart-be68e07a-0128-4f27-9bf0-442e6cf3e219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229046750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2229046750
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3760300390
Short name T819
Test name
Test status
Simulation time 16227709 ps
CPU time 0.68 seconds
Started Jun 27 04:18:30 PM PDT 24
Finished Jun 27 04:18:32 PM PDT 24
Peak memory 195488 kb
Host smart-5b6e9fcd-a1c1-4ff8-acdb-73b6e0994613
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760300390 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3760300390
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1293205542
Short name T761
Test name
Test status
Simulation time 780664729 ps
CPU time 3.23 seconds
Started Jun 27 04:19:37 PM PDT 24
Finished Jun 27 04:19:41 PM PDT 24
Peak memory 197556 kb
Host smart-ddcfe46b-14a3-4dbd-b6e2-59d49c9be7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293205542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1293205542
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.602346310
Short name T84
Test name
Test status
Simulation time 357451070 ps
CPU time 1.55 seconds
Started Jun 27 04:20:23 PM PDT 24
Finished Jun 27 04:20:26 PM PDT 24
Peak memory 198372 kb
Host smart-f92cdde9-5d0a-43df-90e9-4da0573c510c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602346310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.602346310
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.696057501
Short name T69
Test name
Test status
Simulation time 134206314 ps
CPU time 0.77 seconds
Started Jun 27 04:20:04 PM PDT 24
Finished Jun 27 04:20:05 PM PDT 24
Peak memory 196464 kb
Host smart-1db47a19-dc43-4c4f-ba15-24443391a89d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696057501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.696057501
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1605866519
Short name T842
Test name
Test status
Simulation time 770114194 ps
CPU time 3.51 seconds
Started Jun 27 04:19:45 PM PDT 24
Finished Jun 27 04:19:49 PM PDT 24
Peak memory 198080 kb
Host smart-d12fd764-e28a-4f62-bae6-0078c028d27c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605866519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1605866519
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.850806374
Short name T63
Test name
Test status
Simulation time 106311563 ps
CPU time 0.66 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 193336 kb
Host smart-5f3b8c4d-6f1f-4ea6-8aee-41f15c3abc2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850806374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.850806374
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.737030862
Short name T726
Test name
Test status
Simulation time 154423420 ps
CPU time 1.75 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:35 PM PDT 24
Peak memory 198576 kb
Host smart-0d487004-e8ca-4e7e-84d9-137034a4b567
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737030862 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.737030862
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.62134321
Short name T810
Test name
Test status
Simulation time 12006603 ps
CPU time 0.61 seconds
Started Jun 27 04:21:12 PM PDT 24
Finished Jun 27 04:21:13 PM PDT 24
Peak memory 195436 kb
Host smart-e720736a-6166-4ffa-bef4-4108fb635fa4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62134321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_c
sr_rw.62134321
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3130969394
Short name T745
Test name
Test status
Simulation time 10956358 ps
CPU time 0.63 seconds
Started Jun 27 04:20:31 PM PDT 24
Finished Jun 27 04:20:32 PM PDT 24
Peak memory 194604 kb
Host smart-7551ff4f-1dde-4f37-9899-82b713799a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130969394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3130969394
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1363950088
Short name T83
Test name
Test status
Simulation time 128490498 ps
CPU time 0.83 seconds
Started Jun 27 04:20:55 PM PDT 24
Finished Jun 27 04:20:57 PM PDT 24
Peak memory 196960 kb
Host smart-85f02bfc-43c9-4c49-b31e-544e226047a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363950088 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1363950088
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2343675308
Short name T767
Test name
Test status
Simulation time 526417326 ps
CPU time 1.16 seconds
Started Jun 27 04:21:54 PM PDT 24
Finished Jun 27 04:21:56 PM PDT 24
Peak memory 198716 kb
Host smart-079e1d06-64af-4c21-9c80-d104b685b2cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343675308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2343675308
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.126067386
Short name T800
Test name
Test status
Simulation time 1366734050 ps
CPU time 1.47 seconds
Started Jun 27 04:21:18 PM PDT 24
Finished Jun 27 04:21:21 PM PDT 24
Peak memory 198936 kb
Host smart-78d89d49-8b87-4d4b-b014-7b54f51677db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126067386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.126067386
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1294476557
Short name T729
Test name
Test status
Simulation time 31278195 ps
CPU time 0.56 seconds
Started Jun 27 04:23:29 PM PDT 24
Finished Jun 27 04:23:44 PM PDT 24
Peak memory 193944 kb
Host smart-7c1bedc3-ed93-4943-ac0a-8bb589214a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294476557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1294476557
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2924630336
Short name T756
Test name
Test status
Simulation time 38528500 ps
CPU time 0.55 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 194604 kb
Host smart-f545fed4-c834-48ea-a120-6dd7b0f361c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924630336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2924630336
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1442108367
Short name T744
Test name
Test status
Simulation time 20539608 ps
CPU time 0.64 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:11 PM PDT 24
Peak memory 193216 kb
Host smart-a5d6bbc2-2668-4904-a718-a04fe6285f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442108367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1442108367
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.4194508106
Short name T743
Test name
Test status
Simulation time 70854708 ps
CPU time 0.62 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:11 PM PDT 24
Peak memory 193392 kb
Host smart-d25a8a4b-dacd-412d-8a86-26ba8475c861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194508106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.4194508106
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.4275303022
Short name T792
Test name
Test status
Simulation time 35370993 ps
CPU time 0.63 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:44 PM PDT 24
Peak memory 192936 kb
Host smart-44a6cd59-76c7-4ef3-829e-e2d11dd6dce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275303022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.4275303022
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1705617344
Short name T750
Test name
Test status
Simulation time 34715238 ps
CPU time 0.58 seconds
Started Jun 27 04:18:34 PM PDT 24
Finished Jun 27 04:18:35 PM PDT 24
Peak memory 194232 kb
Host smart-64f096f5-af59-4976-9d19-ae1663ce5ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705617344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1705617344
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1631085362
Short name T773
Test name
Test status
Simulation time 45805794 ps
CPU time 0.6 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 193528 kb
Host smart-213c0bcc-7b93-4f84-a6dd-3cb1ee2546f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631085362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1631085362
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3776276585
Short name T784
Test name
Test status
Simulation time 111964065 ps
CPU time 0.7 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 193424 kb
Host smart-ddbc621a-c607-4832-afdd-8c8d49974b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776276585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3776276585
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2939033167
Short name T821
Test name
Test status
Simulation time 53510592 ps
CPU time 0.56 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 194252 kb
Host smart-a35fb54a-7405-475a-9c6e-c74c7768e7e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939033167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2939033167
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.719756334
Short name T747
Test name
Test status
Simulation time 14226312 ps
CPU time 0.55 seconds
Started Jun 27 04:23:11 PM PDT 24
Finished Jun 27 04:23:17 PM PDT 24
Peak memory 194036 kb
Host smart-ab62e804-9f62-4439-b4a5-112216529806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719756334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.719756334
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2580793087
Short name T67
Test name
Test status
Simulation time 29959808 ps
CPU time 0.67 seconds
Started Jun 27 04:19:24 PM PDT 24
Finished Jun 27 04:19:25 PM PDT 24
Peak memory 195560 kb
Host smart-d0776ce2-4879-48f9-98b2-abc72e402fa0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580793087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2580793087
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1124228033
Short name T839
Test name
Test status
Simulation time 80971451 ps
CPU time 2.37 seconds
Started Jun 27 04:20:46 PM PDT 24
Finished Jun 27 04:20:51 PM PDT 24
Peak memory 198532 kb
Host smart-3ac089df-10c8-44df-8790-8b9dcd25ee99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124228033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1124228033
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1175693944
Short name T68
Test name
Test status
Simulation time 15656109 ps
CPU time 0.65 seconds
Started Jun 27 04:20:18 PM PDT 24
Finished Jun 27 04:20:21 PM PDT 24
Peak memory 195236 kb
Host smart-7ea7b303-3f1d-488b-8840-9ef434cdcd42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175693944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1175693944
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1297017234
Short name T732
Test name
Test status
Simulation time 128654807 ps
CPU time 1.51 seconds
Started Jun 27 04:19:54 PM PDT 24
Finished Jun 27 04:19:56 PM PDT 24
Peak memory 198636 kb
Host smart-956cd537-5357-4c8f-aa74-9f2a17daada5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297017234 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1297017234
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1822277823
Short name T58
Test name
Test status
Simulation time 13195356 ps
CPU time 0.64 seconds
Started Jun 27 04:23:05 PM PDT 24
Finished Jun 27 04:23:09 PM PDT 24
Peak memory 195020 kb
Host smart-817ede7a-7646-47ac-8a7b-1ca911a276ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822277823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1822277823
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1974736275
Short name T830
Test name
Test status
Simulation time 17471747 ps
CPU time 0.6 seconds
Started Jun 27 04:21:08 PM PDT 24
Finished Jun 27 04:21:09 PM PDT 24
Peak memory 194300 kb
Host smart-15dcb008-b43d-4a31-b0d6-03fee155d530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974736275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1974736275
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2441184349
Short name T770
Test name
Test status
Simulation time 61677123 ps
CPU time 0.82 seconds
Started Jun 27 04:21:49 PM PDT 24
Finished Jun 27 04:21:51 PM PDT 24
Peak memory 197360 kb
Host smart-c38fef2a-4aec-4b5b-9215-65716140408e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441184349 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2441184349
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1624180563
Short name T846
Test name
Test status
Simulation time 114788791 ps
CPU time 2.99 seconds
Started Jun 27 04:23:38 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 198332 kb
Host smart-41292376-309c-4b31-967a-67d3ffca127f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624180563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1624180563
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3004142555
Short name T829
Test name
Test status
Simulation time 156931417 ps
CPU time 1.09 seconds
Started Jun 27 04:23:38 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 197920 kb
Host smart-a95afc46-f6b8-4eef-8638-fc22abcd0cd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004142555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3004142555
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3926211114
Short name T754
Test name
Test status
Simulation time 12761617 ps
CPU time 0.59 seconds
Started Jun 27 04:21:31 PM PDT 24
Finished Jun 27 04:21:33 PM PDT 24
Peak memory 194256 kb
Host smart-cf16dd94-d7ea-4a71-9dad-e70fabc58e49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926211114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3926211114
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.723186744
Short name T749
Test name
Test status
Simulation time 26667934 ps
CPU time 0.59 seconds
Started Jun 27 04:18:36 PM PDT 24
Finished Jun 27 04:18:38 PM PDT 24
Peak memory 195252 kb
Host smart-4bf94cca-b3e9-46d2-b2f4-79eec887bdee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723186744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.723186744
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4014444641
Short name T755
Test name
Test status
Simulation time 62552883 ps
CPU time 0.8 seconds
Started Jun 27 04:21:06 PM PDT 24
Finished Jun 27 04:21:08 PM PDT 24
Peak memory 194124 kb
Host smart-d55875b3-4416-441e-afe7-dfd151dcd47f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014444641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4014444641
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2227928629
Short name T795
Test name
Test status
Simulation time 13887278 ps
CPU time 0.58 seconds
Started Jun 27 04:19:16 PM PDT 24
Finished Jun 27 04:19:18 PM PDT 24
Peak memory 194292 kb
Host smart-1f80acff-915e-4165-9cbb-eb51a19fa32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227928629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2227928629
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.128651618
Short name T764
Test name
Test status
Simulation time 13634394 ps
CPU time 0.56 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:22:58 PM PDT 24
Peak memory 194196 kb
Host smart-35e3acd7-a632-4cff-af5b-24f309799d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128651618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.128651618
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1478847664
Short name T840
Test name
Test status
Simulation time 22750107 ps
CPU time 0.64 seconds
Started Jun 27 04:19:28 PM PDT 24
Finished Jun 27 04:19:30 PM PDT 24
Peak memory 194352 kb
Host smart-3a373eb5-e104-4e56-8f00-51764d732a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478847664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1478847664
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2785991114
Short name T742
Test name
Test status
Simulation time 19191082 ps
CPU time 0.57 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:44 PM PDT 24
Peak memory 194064 kb
Host smart-c519f950-dc71-424d-a40a-5e1abb22df7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785991114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2785991114
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1790956773
Short name T768
Test name
Test status
Simulation time 47011087 ps
CPU time 0.61 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:22:57 PM PDT 24
Peak memory 194952 kb
Host smart-2a37c5f6-7689-4b68-8cec-05856268224d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790956773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1790956773
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.624743225
Short name T760
Test name
Test status
Simulation time 34397692 ps
CPU time 0.55 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:22:58 PM PDT 24
Peak memory 194264 kb
Host smart-5594f50c-846e-41ff-9bd1-1184e839d3f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624743225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.624743225
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.4163335430
Short name T789
Test name
Test status
Simulation time 16525700 ps
CPU time 0.6 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:44 PM PDT 24
Peak memory 194636 kb
Host smart-46b17fec-68b5-4442-94b8-4bf1ed2f6ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163335430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.4163335430
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1628405962
Short name T74
Test name
Test status
Simulation time 13286572 ps
CPU time 0.62 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:33 PM PDT 24
Peak memory 195320 kb
Host smart-694db9e6-fb37-4bff-869c-25606068419e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628405962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1628405962
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4091093906
Short name T776
Test name
Test status
Simulation time 61332433 ps
CPU time 1.28 seconds
Started Jun 27 04:23:38 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 197740 kb
Host smart-131ef8e4-322f-4565-af23-1881fbc0fcd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091093906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4091093906
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3585019192
Short name T758
Test name
Test status
Simulation time 21864662 ps
CPU time 0.62 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 195420 kb
Host smart-8a3c9b26-f3ce-49b8-a4ed-cc870370d7bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585019192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3585019192
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.750596184
Short name T780
Test name
Test status
Simulation time 26985494 ps
CPU time 0.8 seconds
Started Jun 27 04:21:23 PM PDT 24
Finished Jun 27 04:21:25 PM PDT 24
Peak memory 198412 kb
Host smart-8d53c1c9-049f-4103-af1d-57185ebb5356
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750596184 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.750596184
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1725002608
Short name T772
Test name
Test status
Simulation time 29413124 ps
CPU time 0.62 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 191864 kb
Host smart-eb95d4b2-908a-4179-97ef-9e28f0c68b68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725002608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1725002608
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2153346817
Short name T801
Test name
Test status
Simulation time 80385973 ps
CPU time 0.6 seconds
Started Jun 27 04:18:53 PM PDT 24
Finished Jun 27 04:18:55 PM PDT 24
Peak memory 194244 kb
Host smart-a7c8b054-052c-437b-8e04-e02fd831f60d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153346817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2153346817
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1869845713
Short name T78
Test name
Test status
Simulation time 47785114 ps
CPU time 0.8 seconds
Started Jun 27 04:20:19 PM PDT 24
Finished Jun 27 04:20:22 PM PDT 24
Peak memory 197216 kb
Host smart-b300c5ac-fd53-465c-87b2-9ab441d2a9e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869845713 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1869845713
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3951191628
Short name T841
Test name
Test status
Simulation time 445307146 ps
CPU time 2.32 seconds
Started Jun 27 04:20:03 PM PDT 24
Finished Jun 27 04:20:06 PM PDT 24
Peak memory 198564 kb
Host smart-eef8236b-18f9-4b1f-8b22-ffdcc6cb00ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951191628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3951191628
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2444048626
Short name T816
Test name
Test status
Simulation time 39492541 ps
CPU time 0.88 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 195276 kb
Host smart-d5ff9e9f-a955-4904-92da-852eeca71e80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444048626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2444048626
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2256989944
Short name T796
Test name
Test status
Simulation time 46792071 ps
CPU time 0.55 seconds
Started Jun 27 04:22:57 PM PDT 24
Finished Jun 27 04:22:58 PM PDT 24
Peak memory 194236 kb
Host smart-c277d175-1804-4ab1-a1d0-6e022e97886d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256989944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2256989944
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3584311092
Short name T769
Test name
Test status
Simulation time 11699383 ps
CPU time 0.55 seconds
Started Jun 27 04:23:40 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 194512 kb
Host smart-c79313f5-fa36-4f46-87f8-9b45508ff2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584311092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3584311092
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3622915262
Short name T808
Test name
Test status
Simulation time 28301672 ps
CPU time 0.58 seconds
Started Jun 27 04:19:21 PM PDT 24
Finished Jun 27 04:19:22 PM PDT 24
Peak memory 194352 kb
Host smart-9030e663-052e-4b86-bd0a-6fc8d0096efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622915262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3622915262
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3653753512
Short name T804
Test name
Test status
Simulation time 13636271 ps
CPU time 0.57 seconds
Started Jun 27 04:18:58 PM PDT 24
Finished Jun 27 04:19:00 PM PDT 24
Peak memory 195276 kb
Host smart-9203ea53-5fdb-43bd-a213-28759f3df1c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653753512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3653753512
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3237931429
Short name T728
Test name
Test status
Simulation time 21534482 ps
CPU time 0.64 seconds
Started Jun 27 04:22:39 PM PDT 24
Finished Jun 27 04:22:41 PM PDT 24
Peak memory 194148 kb
Host smart-0fbbd72a-9f8b-4f9e-af9a-dc61ad7867eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237931429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3237931429
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3160225823
Short name T725
Test name
Test status
Simulation time 18413109 ps
CPU time 0.6 seconds
Started Jun 27 04:19:28 PM PDT 24
Finished Jun 27 04:19:30 PM PDT 24
Peak memory 194300 kb
Host smart-8d050adc-2b4f-43cb-a4b7-09445ea2ba4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160225823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3160225823
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.4002752620
Short name T834
Test name
Test status
Simulation time 41059759 ps
CPU time 0.57 seconds
Started Jun 27 04:19:21 PM PDT 24
Finished Jun 27 04:19:22 PM PDT 24
Peak memory 194988 kb
Host smart-c4541393-31ff-4204-864e-3113de760f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002752620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.4002752620
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1113067970
Short name T748
Test name
Test status
Simulation time 49633544 ps
CPU time 0.63 seconds
Started Jun 27 04:20:22 PM PDT 24
Finished Jun 27 04:20:24 PM PDT 24
Peak memory 194296 kb
Host smart-844c5f75-5d07-445e-8ca4-e75a367fa38b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113067970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1113067970
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3608764661
Short name T722
Test name
Test status
Simulation time 19458640 ps
CPU time 0.57 seconds
Started Jun 27 04:19:47 PM PDT 24
Finished Jun 27 04:19:49 PM PDT 24
Peak memory 194892 kb
Host smart-39185734-f8a7-4d26-9f95-b18c9f16a43d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608764661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3608764661
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2772354556
Short name T740
Test name
Test status
Simulation time 30791033 ps
CPU time 0.61 seconds
Started Jun 27 04:19:20 PM PDT 24
Finished Jun 27 04:19:22 PM PDT 24
Peak memory 194620 kb
Host smart-11799447-0bf2-4a8b-a958-cbd0d86daaa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772354556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2772354556
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2310102884
Short name T824
Test name
Test status
Simulation time 129438176 ps
CPU time 0.93 seconds
Started Jun 27 04:21:31 PM PDT 24
Finished Jun 27 04:21:32 PM PDT 24
Peak memory 198556 kb
Host smart-11ba80c8-0b15-4b34-9605-b8b55f80c2f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310102884 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2310102884
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4133969431
Short name T59
Test name
Test status
Simulation time 14163783 ps
CPU time 0.58 seconds
Started Jun 27 04:21:50 PM PDT 24
Finished Jun 27 04:21:52 PM PDT 24
Peak memory 193748 kb
Host smart-aface71d-eaf0-4bbf-ab1d-de47bc8b5441
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133969431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4133969431
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3730558319
Short name T762
Test name
Test status
Simulation time 44597360 ps
CPU time 0.68 seconds
Started Jun 27 04:20:38 PM PDT 24
Finished Jun 27 04:20:42 PM PDT 24
Peak memory 194280 kb
Host smart-65a32e74-a658-4627-892a-01d018d5e953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730558319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3730558319
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2220327523
Short name T81
Test name
Test status
Simulation time 22180450 ps
CPU time 0.82 seconds
Started Jun 27 04:23:25 PM PDT 24
Finished Jun 27 04:23:38 PM PDT 24
Peak memory 197732 kb
Host smart-7d639eb6-6df9-434c-842b-d052e5177ad6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220327523 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2220327523
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3635638465
Short name T757
Test name
Test status
Simulation time 445258635 ps
CPU time 2.38 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 198292 kb
Host smart-3f17aa14-b082-411a-ac7b-bbc65871d47c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635638465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3635638465
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1347199177
Short name T40
Test name
Test status
Simulation time 447734391 ps
CPU time 1.13 seconds
Started Jun 27 04:19:09 PM PDT 24
Finished Jun 27 04:19:11 PM PDT 24
Peak memory 198568 kb
Host smart-8ca845c2-09c7-49cc-9b85-3d57f89b38d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347199177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1347199177
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3977301930
Short name T820
Test name
Test status
Simulation time 50382635 ps
CPU time 0.72 seconds
Started Jun 27 04:21:53 PM PDT 24
Finished Jun 27 04:21:55 PM PDT 24
Peak memory 197772 kb
Host smart-f6db7cec-8838-4bdf-923d-a5cf88e2e527
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977301930 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3977301930
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3696056917
Short name T66
Test name
Test status
Simulation time 10910016 ps
CPU time 0.58 seconds
Started Jun 27 04:20:10 PM PDT 24
Finished Jun 27 04:20:12 PM PDT 24
Peak memory 194200 kb
Host smart-134f6a59-fc99-4a34-a802-e4931662dd41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696056917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3696056917
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2482408382
Short name T844
Test name
Test status
Simulation time 16182753 ps
CPU time 0.63 seconds
Started Jun 27 04:20:58 PM PDT 24
Finished Jun 27 04:20:59 PM PDT 24
Peak memory 194424 kb
Host smart-24170ee4-914d-4ff4-aeb2-ce2841bb8716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482408382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2482408382
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1375092035
Short name T61
Test name
Test status
Simulation time 42941659 ps
CPU time 0.89 seconds
Started Jun 27 04:19:29 PM PDT 24
Finished Jun 27 04:19:31 PM PDT 24
Peak memory 196792 kb
Host smart-04109393-a25d-4de3-8e90-2b234a70acf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375092035 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1375092035
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.916296272
Short name T802
Test name
Test status
Simulation time 186498206 ps
CPU time 2.42 seconds
Started Jun 27 04:20:10 PM PDT 24
Finished Jun 27 04:20:14 PM PDT 24
Peak memory 198636 kb
Host smart-3fa8a740-3e5e-488d-8a6a-30e1f0c40bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916296272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.916296272
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2004171400
Short name T805
Test name
Test status
Simulation time 393905244 ps
CPU time 0.89 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:35 PM PDT 24
Peak memory 197640 kb
Host smart-3e5b567c-2e41-47fb-91c6-1b91dcf3d662
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004171400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2004171400
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.545997236
Short name T794
Test name
Test status
Simulation time 31174255 ps
CPU time 0.8 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:33 PM PDT 24
Peak memory 198100 kb
Host smart-397e6932-304d-44de-a87f-12bbd0937005
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545997236 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.545997236
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3675102880
Short name T65
Test name
Test status
Simulation time 44584446 ps
CPU time 0.78 seconds
Started Jun 27 04:19:39 PM PDT 24
Finished Jun 27 04:19:41 PM PDT 24
Peak memory 196384 kb
Host smart-271cd04b-9647-491c-930d-0e9c2e524951
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675102880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3675102880
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1204449622
Short name T724
Test name
Test status
Simulation time 14228063 ps
CPU time 0.6 seconds
Started Jun 27 04:22:32 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 193308 kb
Host smart-5dbb6b76-f0d6-421c-90f4-3b3827b01309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204449622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1204449622
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.848988795
Short name T80
Test name
Test status
Simulation time 28157266 ps
CPU time 0.64 seconds
Started Jun 27 04:21:45 PM PDT 24
Finished Jun 27 04:21:47 PM PDT 24
Peak memory 195560 kb
Host smart-66d8f292-6d58-4356-93f4-4b41c0c25cb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848988795 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.848988795
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.484492796
Short name T826
Test name
Test status
Simulation time 277493625 ps
CPU time 1.42 seconds
Started Jun 27 04:19:46 PM PDT 24
Finished Jun 27 04:19:49 PM PDT 24
Peak memory 198560 kb
Host smart-b9d2f211-8db9-466f-a69d-1b73ca53f426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484492796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.484492796
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2900260567
Short name T30
Test name
Test status
Simulation time 91665387 ps
CPU time 1.17 seconds
Started Jun 27 04:19:16 PM PDT 24
Finished Jun 27 04:19:18 PM PDT 24
Peak memory 198600 kb
Host smart-7e5a5df1-e2d9-4314-a9aa-89df42071ab8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900260567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2900260567
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.530598337
Short name T734
Test name
Test status
Simulation time 34592077 ps
CPU time 0.78 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:35 PM PDT 24
Peak memory 198412 kb
Host smart-a1aa024a-0fed-4132-b5d0-a6b0a35dcc71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530598337 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.530598337
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1682131749
Short name T751
Test name
Test status
Simulation time 13052197 ps
CPU time 0.61 seconds
Started Jun 27 04:21:23 PM PDT 24
Finished Jun 27 04:21:25 PM PDT 24
Peak memory 195320 kb
Host smart-f8be008e-cd2e-4e4e-bd30-d6a633960e27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682131749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1682131749
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2541169418
Short name T793
Test name
Test status
Simulation time 35227026 ps
CPU time 0.72 seconds
Started Jun 27 04:19:06 PM PDT 24
Finished Jun 27 04:19:07 PM PDT 24
Peak memory 195308 kb
Host smart-d9de6902-dbc6-4990-8221-c3e413d0f761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541169418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2541169418
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.933678135
Short name T82
Test name
Test status
Simulation time 18911195 ps
CPU time 0.87 seconds
Started Jun 27 04:19:39 PM PDT 24
Finished Jun 27 04:19:40 PM PDT 24
Peak memory 196920 kb
Host smart-30a2c898-410f-4688-a03e-6dabe79b985b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933678135 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.933678135
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.106585485
Short name T806
Test name
Test status
Simulation time 1428224263 ps
CPU time 3.23 seconds
Started Jun 27 04:19:37 PM PDT 24
Finished Jun 27 04:19:42 PM PDT 24
Peak memory 198560 kb
Host smart-7a33f95a-59a1-4b15-980f-e1ba542f60e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106585485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.106585485
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.554532348
Short name T37
Test name
Test status
Simulation time 286120162 ps
CPU time 1.22 seconds
Started Jun 27 04:20:46 PM PDT 24
Finished Jun 27 04:20:50 PM PDT 24
Peak memory 198272 kb
Host smart-f6b3d008-5444-41ac-8fd7-7bf73ecbed21
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554532348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.554532348
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2404339078
Short name T735
Test name
Test status
Simulation time 76200515 ps
CPU time 0.8 seconds
Started Jun 27 04:21:24 PM PDT 24
Finished Jun 27 04:21:26 PM PDT 24
Peak memory 198428 kb
Host smart-727b2508-f663-4e75-a30f-faf0263e4d87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404339078 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2404339078
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2926800278
Short name T72
Test name
Test status
Simulation time 49787872 ps
CPU time 0.64 seconds
Started Jun 27 04:19:24 PM PDT 24
Finished Jun 27 04:19:26 PM PDT 24
Peak memory 196384 kb
Host smart-b20401d6-c10b-4c06-8943-aa447e2f157b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926800278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2926800278
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1400513790
Short name T827
Test name
Test status
Simulation time 42477815 ps
CPU time 0.61 seconds
Started Jun 27 04:22:46 PM PDT 24
Finished Jun 27 04:22:49 PM PDT 24
Peak memory 194312 kb
Host smart-bc234ebc-ba49-4594-bdc4-6362f4c2ef9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400513790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1400513790
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2433876695
Short name T797
Test name
Test status
Simulation time 317261991 ps
CPU time 0.71 seconds
Started Jun 27 04:19:40 PM PDT 24
Finished Jun 27 04:19:43 PM PDT 24
Peak memory 195964 kb
Host smart-5fad4cf0-0e5e-433e-aeff-326bd7af65f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433876695 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2433876695
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3455438421
Short name T730
Test name
Test status
Simulation time 145039229 ps
CPU time 1.13 seconds
Started Jun 27 04:18:53 PM PDT 24
Finished Jun 27 04:18:55 PM PDT 24
Peak memory 198396 kb
Host smart-e01365f3-269b-47fd-9d36-ee31931579ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455438421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3455438421
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2590797577
Short name T39
Test name
Test status
Simulation time 390828847 ps
CPU time 1.16 seconds
Started Jun 27 04:18:07 PM PDT 24
Finished Jun 27 04:18:09 PM PDT 24
Peak memory 198564 kb
Host smart-1bff9754-8656-4862-bc93-359868123c02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590797577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2590797577
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4213471502
Short name T490
Test name
Test status
Simulation time 15365471 ps
CPU time 0.6 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 195084 kb
Host smart-59d2699d-d878-4f9c-9a1c-b145e48a0f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213471502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4213471502
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1968524438
Short name T519
Test name
Test status
Simulation time 58655155 ps
CPU time 0.8 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 197476 kb
Host smart-6d5cbb37-5ea8-44a0-9401-9e862a5c3b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968524438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1968524438
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.564211623
Short name T363
Test name
Test status
Simulation time 826954034 ps
CPU time 14.76 seconds
Started Jun 27 04:23:31 PM PDT 24
Finished Jun 27 04:24:00 PM PDT 24
Peak memory 198252 kb
Host smart-d33692f5-0244-4d21-81eb-61f9a3df5e54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564211623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.564211623
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1400966352
Short name T251
Test name
Test status
Simulation time 104450995 ps
CPU time 0.63 seconds
Started Jun 27 04:20:10 PM PDT 24
Finished Jun 27 04:20:12 PM PDT 24
Peak memory 194936 kb
Host smart-1ccd3327-a470-46c9-bff9-a30543f7c4e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400966352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1400966352
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2564549428
Short name T444
Test name
Test status
Simulation time 36122483 ps
CPU time 0.81 seconds
Started Jun 27 04:20:05 PM PDT 24
Finished Jun 27 04:20:08 PM PDT 24
Peak memory 196300 kb
Host smart-53f0037f-d214-4105-806b-808c4c1da885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564549428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2564549428
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3653839386
Short name T704
Test name
Test status
Simulation time 140621961 ps
CPU time 2.18 seconds
Started Jun 27 04:23:25 PM PDT 24
Finished Jun 27 04:23:40 PM PDT 24
Peak memory 198592 kb
Host smart-abaf6728-a9bd-4e19-bc1e-6b7d8e677b28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653839386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3653839386
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1657224743
Short name T403
Test name
Test status
Simulation time 258577732 ps
CPU time 1.16 seconds
Started Jun 27 04:20:55 PM PDT 24
Finished Jun 27 04:20:57 PM PDT 24
Peak memory 197620 kb
Host smart-9d3a6ea4-cda6-43c7-a4b6-5db1e63e5f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657224743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1657224743
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1967626890
Short name T401
Test name
Test status
Simulation time 60308812 ps
CPU time 1.22 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 197232 kb
Host smart-04997099-8178-4765-9e58-cb428b2684db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967626890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1967626890
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2363165543
Short name T284
Test name
Test status
Simulation time 422037778 ps
CPU time 1.91 seconds
Started Jun 27 04:23:18 PM PDT 24
Finished Jun 27 04:23:28 PM PDT 24
Peak memory 198244 kb
Host smart-022c5032-840a-41dc-8f7d-769a91de75b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363165543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2363165543
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.165246482
Short name T32
Test name
Test status
Simulation time 180787461 ps
CPU time 0.81 seconds
Started Jun 27 04:21:08 PM PDT 24
Finished Jun 27 04:21:10 PM PDT 24
Peak memory 214416 kb
Host smart-0b01fe61-26d3-485c-b0c2-a46c2de9ebbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165246482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.165246482
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.203694831
Short name T234
Test name
Test status
Simulation time 53641593 ps
CPU time 0.92 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:27 PM PDT 24
Peak memory 195932 kb
Host smart-67e162e3-0d74-4648-8c8a-f93f07d20bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203694831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.203694831
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2772983978
Short name T283
Test name
Test status
Simulation time 287873708 ps
CPU time 1.21 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:26 PM PDT 24
Peak memory 197080 kb
Host smart-4c4ccddb-4783-4251-a516-21e8630cb5d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772983978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2772983978
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3821593004
Short name T455
Test name
Test status
Simulation time 5848251030 ps
CPU time 128.72 seconds
Started Jun 27 04:23:25 PM PDT 24
Finished Jun 27 04:25:45 PM PDT 24
Peak memory 198500 kb
Host smart-eab799a8-0e04-4269-9489-5882b47258a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821593004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3821593004
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.31697907
Short name T48
Test name
Test status
Simulation time 418439404906 ps
CPU time 1743.8 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:52:17 PM PDT 24
Peak memory 197928 kb
Host smart-bb1a4635-36aa-4287-aa62-b3a2def05813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=31697907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.31697907
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3883881397
Short name T275
Test name
Test status
Simulation time 101512317 ps
CPU time 0.54 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:26 PM PDT 24
Peak memory 194344 kb
Host smart-6b8a37e3-faf7-4b79-a153-b1d3b920a7cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883881397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3883881397
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3688988561
Short name T195
Test name
Test status
Simulation time 52771220 ps
CPU time 0.79 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:27 PM PDT 24
Peak memory 195748 kb
Host smart-a3ba34d9-8cec-4cf7-8022-9525d47b0f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688988561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3688988561
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.11353627
Short name T643
Test name
Test status
Simulation time 1972383655 ps
CPU time 24.33 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 197292 kb
Host smart-72204595-f90a-4123-aaa4-85b5060adc11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11353627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.11353627
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3365478750
Short name T421
Test name
Test status
Simulation time 268816520 ps
CPU time 0.91 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 196924 kb
Host smart-10f5d1a9-43f8-4602-ad19-32e743e9765a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365478750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3365478750
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1227676741
Short name T605
Test name
Test status
Simulation time 105918940 ps
CPU time 1.4 seconds
Started Jun 27 04:20:07 PM PDT 24
Finished Jun 27 04:20:09 PM PDT 24
Peak memory 197312 kb
Host smart-cb9914d6-c6b2-447d-8480-d16006f2eaad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227676741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1227676741
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2626245474
Short name T241
Test name
Test status
Simulation time 254829588 ps
CPU time 1.3 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:46 PM PDT 24
Peak memory 196884 kb
Host smart-859de3c1-27db-45c6-9b9f-61e5f0853fe6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626245474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2626245474
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.503407489
Short name T87
Test name
Test status
Simulation time 900397715 ps
CPU time 2.18 seconds
Started Jun 27 04:23:25 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 197544 kb
Host smart-d596e613-cca2-459a-b597-f6838924e0b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503407489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.503407489
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3552400431
Short name T601
Test name
Test status
Simulation time 26959940 ps
CPU time 0.76 seconds
Started Jun 27 04:23:18 PM PDT 24
Finished Jun 27 04:23:28 PM PDT 24
Peak memory 196512 kb
Host smart-d15a9fb4-84e8-4a4b-b9c9-058ff77fd8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552400431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3552400431
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.588029999
Short name T288
Test name
Test status
Simulation time 32418349 ps
CPU time 0.72 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:27 PM PDT 24
Peak memory 195644 kb
Host smart-41f8c1ab-38f1-41ca-b614-d127920cb0a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588029999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.588029999
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1118091580
Short name T254
Test name
Test status
Simulation time 54213762 ps
CPU time 2.25 seconds
Started Jun 27 04:20:58 PM PDT 24
Finished Jun 27 04:21:01 PM PDT 24
Peak memory 198324 kb
Host smart-21af4485-428a-48cb-b972-450076af5918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118091580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1118091580
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2146113415
Short name T42
Test name
Test status
Simulation time 203164045 ps
CPU time 0.82 seconds
Started Jun 27 04:23:24 PM PDT 24
Finished Jun 27 04:23:37 PM PDT 24
Peak memory 214060 kb
Host smart-40d1ca8c-9275-4929-adaa-91e772498e63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146113415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2146113415
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.842225423
Short name T659
Test name
Test status
Simulation time 63279121 ps
CPU time 0.95 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:46 PM PDT 24
Peak memory 195752 kb
Host smart-e8c6307a-4a6d-49a4-8b2b-d2766edb7c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842225423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.842225423
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2731364043
Short name T224
Test name
Test status
Simulation time 320991133 ps
CPU time 1.28 seconds
Started Jun 27 04:23:25 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 196108 kb
Host smart-371f42a0-6765-4a30-885d-c83e2caa30fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731364043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2731364043
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2209524193
Short name T383
Test name
Test status
Simulation time 52909559157 ps
CPU time 186.42 seconds
Started Jun 27 04:20:05 PM PDT 24
Finished Jun 27 04:23:13 PM PDT 24
Peak memory 198628 kb
Host smart-b9b582a1-bc22-4910-94d8-894216e9379e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209524193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2209524193
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.4158126735
Short name T427
Test name
Test status
Simulation time 12756197 ps
CPU time 0.59 seconds
Started Jun 27 04:23:26 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 195320 kb
Host smart-b2864578-e134-474a-9e75-51fc79ea704e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158126735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4158126735
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3025286162
Short name T280
Test name
Test status
Simulation time 27330735 ps
CPU time 0.72 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:19 PM PDT 24
Peak memory 193164 kb
Host smart-8f69de13-175d-4033-9bef-0945701f6cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025286162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3025286162
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2437161227
Short name T656
Test name
Test status
Simulation time 495088538 ps
CPU time 23.92 seconds
Started Jun 27 04:22:59 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 195436 kb
Host smart-65122772-7fe6-4542-82fd-7d2802e3f31a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437161227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2437161227
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3220664629
Short name T633
Test name
Test status
Simulation time 258871035 ps
CPU time 0.8 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:26 PM PDT 24
Peak memory 196256 kb
Host smart-0a8b55ae-5570-45d6-a4cd-5a35eaf12cea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220664629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3220664629
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1224038569
Short name T339
Test name
Test status
Simulation time 235685909 ps
CPU time 1 seconds
Started Jun 27 04:21:38 PM PDT 24
Finished Jun 27 04:21:40 PM PDT 24
Peak memory 197660 kb
Host smart-63a25308-b255-44b5-afd5-7a12ef91411a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224038569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1224038569
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1723205271
Short name T457
Test name
Test status
Simulation time 348059787 ps
CPU time 3.51 seconds
Started Jun 27 04:21:44 PM PDT 24
Finished Jun 27 04:21:49 PM PDT 24
Peak memory 198564 kb
Host smart-8716cf3f-07d0-4f0f-a31b-fafc70ac4653
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723205271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1723205271
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1468907053
Short name T462
Test name
Test status
Simulation time 600198765 ps
CPU time 3.19 seconds
Started Jun 27 04:21:42 PM PDT 24
Finished Jun 27 04:21:46 PM PDT 24
Peak memory 197676 kb
Host smart-b750a61e-7822-46f2-a23c-a6600330be22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468907053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1468907053
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1894182340
Short name T296
Test name
Test status
Simulation time 30547619 ps
CPU time 1.05 seconds
Started Jun 27 04:23:18 PM PDT 24
Finished Jun 27 04:23:29 PM PDT 24
Peak memory 195848 kb
Host smart-bc621041-3269-44aa-b9cf-530a289ee687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894182340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1894182340
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1250824588
Short name T446
Test name
Test status
Simulation time 25298641 ps
CPU time 0.61 seconds
Started Jun 27 04:23:27 PM PDT 24
Finished Jun 27 04:23:41 PM PDT 24
Peak memory 195272 kb
Host smart-dd75890f-fdb9-45ad-89ec-836127f7cc66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250824588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1250824588
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2557582349
Short name T491
Test name
Test status
Simulation time 92353712 ps
CPU time 2.09 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:22:48 PM PDT 24
Peak memory 197692 kb
Host smart-ffbb11a7-3b19-4b32-a7e6-0a48042d77d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557582349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2557582349
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.572774722
Short name T332
Test name
Test status
Simulation time 76015073 ps
CPU time 1.02 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:21 PM PDT 24
Peak memory 195952 kb
Host smart-bdc20a04-8557-4bdb-8eef-0a3e6521a181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572774722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.572774722
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2071980113
Short name T347
Test name
Test status
Simulation time 47058462 ps
CPU time 1.13 seconds
Started Jun 27 04:21:44 PM PDT 24
Finished Jun 27 04:21:46 PM PDT 24
Peak memory 196284 kb
Host smart-eaee4346-b035-4b0a-8913-cc56437939c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071980113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2071980113
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3836850914
Short name T460
Test name
Test status
Simulation time 24124111004 ps
CPU time 62.89 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:24:21 PM PDT 24
Peak memory 196732 kb
Host smart-e80ee5fb-16c6-46b3-8238-6aee071cf820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836850914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3836850914
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3786436145
Short name T436
Test name
Test status
Simulation time 12325598 ps
CPU time 0.58 seconds
Started Jun 27 04:21:44 PM PDT 24
Finished Jun 27 04:21:45 PM PDT 24
Peak memory 195476 kb
Host smart-782d2662-a090-4dba-9f7b-e1080af4f7fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786436145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3786436145
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3952738373
Short name T666
Test name
Test status
Simulation time 42207798 ps
CPU time 0.81 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:23:30 PM PDT 24
Peak memory 196772 kb
Host smart-6f374836-39bf-467c-81cc-653d24f0ff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952738373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3952738373
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1863351750
Short name T523
Test name
Test status
Simulation time 1446582524 ps
CPU time 10.87 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 198416 kb
Host smart-a293ce07-4474-4351-8772-ddf1bb0e21ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863351750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1863351750
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2185552353
Short name T311
Test name
Test status
Simulation time 182393419 ps
CPU time 0.75 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:21 PM PDT 24
Peak memory 195916 kb
Host smart-39fda697-8978-4b7f-802c-09182dc81d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185552353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2185552353
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3859497448
Short name T313
Test name
Test status
Simulation time 85304226 ps
CPU time 1.22 seconds
Started Jun 27 04:23:04 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 196600 kb
Host smart-6a0ac619-66cc-46d0-a94d-162413efb17f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859497448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3859497448
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4034418053
Short name T207
Test name
Test status
Simulation time 163624790 ps
CPU time 3.23 seconds
Started Jun 27 04:21:37 PM PDT 24
Finished Jun 27 04:21:42 PM PDT 24
Peak memory 198628 kb
Host smart-dc57cee7-2b04-4c5a-a537-8057a1d92b35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034418053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4034418053
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1711946639
Short name T215
Test name
Test status
Simulation time 165434682 ps
CPU time 1.67 seconds
Started Jun 27 04:23:03 PM PDT 24
Finished Jun 27 04:23:08 PM PDT 24
Peak memory 195272 kb
Host smart-fab6b042-93cf-4c9d-bf27-14996e2bb572
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711946639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1711946639
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2626373548
Short name T527
Test name
Test status
Simulation time 47234242 ps
CPU time 1.01 seconds
Started Jun 27 04:21:50 PM PDT 24
Finished Jun 27 04:21:52 PM PDT 24
Peak memory 196544 kb
Host smart-0335c479-5f14-45d3-a942-eab5d1881729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626373548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2626373548
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2798014969
Short name T176
Test name
Test status
Simulation time 71549214 ps
CPU time 0.98 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 195044 kb
Host smart-40a7c68d-1c42-4558-90f1-a26dc7dd105c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798014969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2798014969
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3213942072
Short name T238
Test name
Test status
Simulation time 194190976 ps
CPU time 4.42 seconds
Started Jun 27 04:23:27 PM PDT 24
Finished Jun 27 04:23:45 PM PDT 24
Peak memory 198400 kb
Host smart-ebd59bb1-e631-4c09-b162-047bc70e0c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213942072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3213942072
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1923875525
Short name T308
Test name
Test status
Simulation time 62249219 ps
CPU time 0.76 seconds
Started Jun 27 04:23:27 PM PDT 24
Finished Jun 27 04:23:41 PM PDT 24
Peak memory 195516 kb
Host smart-c5acea79-62c0-4b72-9ee5-39210e4c4786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923875525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1923875525
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2426478552
Short name T203
Test name
Test status
Simulation time 42856377 ps
CPU time 0.99 seconds
Started Jun 27 04:21:45 PM PDT 24
Finished Jun 27 04:21:47 PM PDT 24
Peak memory 196328 kb
Host smart-8d37ede2-43dd-49bf-a8f9-e1f9c1f70be8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426478552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2426478552
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3653174854
Short name T437
Test name
Test status
Simulation time 109135056 ps
CPU time 0.86 seconds
Started Jun 27 04:21:37 PM PDT 24
Finished Jun 27 04:21:39 PM PDT 24
Peak memory 197592 kb
Host smart-68d8578d-3b3c-4eec-83c1-df3644acb2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653174854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3653174854
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3764149193
Short name T114
Test name
Test status
Simulation time 275278379 ps
CPU time 13.62 seconds
Started Jun 27 04:23:29 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 197184 kb
Host smart-898a1e35-6f17-4afd-8d6d-f6856f6fa221
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764149193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3764149193
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3612787484
Short name T268
Test name
Test status
Simulation time 316034019 ps
CPU time 0.96 seconds
Started Jun 27 04:23:23 PM PDT 24
Finished Jun 27 04:23:36 PM PDT 24
Peak memory 196956 kb
Host smart-cbd21ad8-1f17-42a1-aef8-2b37df19babb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612787484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3612787484
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.4040619686
Short name T186
Test name
Test status
Simulation time 172560767 ps
CPU time 1.21 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:20 PM PDT 24
Peak memory 195248 kb
Host smart-4bbe0f19-7594-40bb-b766-5a74f5b3f744
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040619686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.4040619686
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1778893262
Short name T147
Test name
Test status
Simulation time 48443049 ps
CPU time 1.23 seconds
Started Jun 27 04:23:27 PM PDT 24
Finished Jun 27 04:23:41 PM PDT 24
Peak memory 197704 kb
Host smart-8d305e12-8a06-4ce1-91fa-29241b03a648
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778893262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1778893262
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1359206396
Short name T360
Test name
Test status
Simulation time 34996779 ps
CPU time 1.03 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 194144 kb
Host smart-0eb1d8b6-1fe6-4c27-a69a-e7bac8d7dcbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359206396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1359206396
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1935035968
Short name T361
Test name
Test status
Simulation time 390546053 ps
CPU time 1.29 seconds
Started Jun 27 04:22:58 PM PDT 24
Finished Jun 27 04:23:01 PM PDT 24
Peak memory 196728 kb
Host smart-87dbe263-1848-4b7f-b1de-1578ec274860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935035968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1935035968
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2665058241
Short name T639
Test name
Test status
Simulation time 131970390 ps
CPU time 0.86 seconds
Started Jun 27 04:23:29 PM PDT 24
Finished Jun 27 04:23:44 PM PDT 24
Peak memory 197116 kb
Host smart-eb6d4579-f400-46da-9860-85afacb0a862
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665058241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2665058241
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3102723903
Short name T655
Test name
Test status
Simulation time 129568621 ps
CPU time 2.98 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:28 PM PDT 24
Peak memory 198372 kb
Host smart-d46239a4-8880-4492-ab7b-9d9ffc1fdc9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102723903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3102723903
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2331137783
Short name T553
Test name
Test status
Simulation time 46203681 ps
CPU time 0.86 seconds
Started Jun 27 04:22:03 PM PDT 24
Finished Jun 27 04:22:04 PM PDT 24
Peak memory 197608 kb
Host smart-83fb99ff-0900-47f7-b644-09b9e9e602c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331137783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2331137783
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1134794980
Short name T118
Test name
Test status
Simulation time 38806322 ps
CPU time 1.03 seconds
Started Jun 27 04:23:26 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 195944 kb
Host smart-b50e89d2-83e2-4929-af00-1e4637eb3de5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134794980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1134794980
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2145212583
Short name T415
Test name
Test status
Simulation time 26460146171 ps
CPU time 71.47 seconds
Started Jun 27 04:23:27 PM PDT 24
Finished Jun 27 04:24:51 PM PDT 24
Peak memory 198548 kb
Host smart-03596f86-5164-4acb-9240-5ed88e11d95b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145212583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2145212583
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2333776090
Short name T589
Test name
Test status
Simulation time 47225744 ps
CPU time 0.6 seconds
Started Jun 27 04:21:53 PM PDT 24
Finished Jun 27 04:21:55 PM PDT 24
Peak memory 195048 kb
Host smart-a655ff21-8447-49de-a3b6-6bb91c5b9765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333776090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2333776090
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.843632290
Short name T641
Test name
Test status
Simulation time 23740116 ps
CPU time 0.62 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:20 PM PDT 24
Peak memory 194056 kb
Host smart-eb3f8235-fec5-4386-9d34-68fdb443daa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843632290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.843632290
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2322914450
Short name T303
Test name
Test status
Simulation time 480453751 ps
CPU time 12.67 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:34 PM PDT 24
Peak memory 197220 kb
Host smart-5b78075e-15c5-4309-b75d-4f65ee244790
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322914450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2322914450
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3228835381
Short name T246
Test name
Test status
Simulation time 52465659 ps
CPU time 0.76 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:19 PM PDT 24
Peak memory 196280 kb
Host smart-2961693f-5899-4240-aa13-9aeb5f9ec694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228835381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3228835381
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3922071654
Short name T434
Test name
Test status
Simulation time 72724940 ps
CPU time 1.15 seconds
Started Jun 27 04:22:59 PM PDT 24
Finished Jun 27 04:23:02 PM PDT 24
Peak memory 195336 kb
Host smart-2ec565f7-9a91-419f-8636-cec3c6dbaf94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922071654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3922071654
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2745485629
Short name T715
Test name
Test status
Simulation time 89435610 ps
CPU time 3.38 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:18 PM PDT 24
Peak memory 196260 kb
Host smart-385c7a94-b793-40ab-a3f1-80c65ef5426a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745485629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2745485629
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2223013236
Short name T380
Test name
Test status
Simulation time 513591886 ps
CPU time 2.48 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 195456 kb
Host smart-52885d78-a782-4033-8519-38a84bf0049f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223013236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2223013236
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3543902652
Short name T692
Test name
Test status
Simulation time 25517597 ps
CPU time 0.63 seconds
Started Jun 27 04:21:44 PM PDT 24
Finished Jun 27 04:21:45 PM PDT 24
Peak memory 194744 kb
Host smart-78573a6c-bb46-429f-adbb-f3877cc41580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543902652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3543902652
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.896144687
Short name T144
Test name
Test status
Simulation time 52553866 ps
CPU time 1.1 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 196948 kb
Host smart-040903ec-3497-4bc7-8cc3-1d92fb5b784c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896144687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.896144687
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.703396191
Short name T292
Test name
Test status
Simulation time 567578935 ps
CPU time 1.37 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:23:30 PM PDT 24
Peak memory 198428 kb
Host smart-5f08136d-1de0-41e3-8ea4-543157b82fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703396191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.703396191
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2873707252
Short name T316
Test name
Test status
Simulation time 88863778 ps
CPU time 1.3 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 195112 kb
Host smart-4c9980c4-7b33-4489-b2fb-146221cc4663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873707252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2873707252
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.987919180
Short name T695
Test name
Test status
Simulation time 61477666 ps
CPU time 0.85 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:35 PM PDT 24
Peak memory 196680 kb
Host smart-6f51c77f-b158-48e8-8c45-08fad7c73328
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987919180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.987919180
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.4258446532
Short name T227
Test name
Test status
Simulation time 31399694996 ps
CPU time 160.98 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:26:01 PM PDT 24
Peak memory 198544 kb
Host smart-6af7c246-c3d2-4807-afdb-6ad223183278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258446532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.4258446532
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.4282217280
Short name T26
Test name
Test status
Simulation time 25916273767 ps
CPU time 366.47 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:29:38 PM PDT 24
Peak memory 198712 kb
Host smart-9ddc85a4-d52f-4f28-b470-ba14fe17ddf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4282217280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.4282217280
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3616040839
Short name T609
Test name
Test status
Simulation time 44809200 ps
CPU time 0.54 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 194572 kb
Host smart-0101f048-fc3e-44fe-8a6f-f433513c881c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616040839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3616040839
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1751882667
Short name T318
Test name
Test status
Simulation time 28378787 ps
CPU time 0.83 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:15 PM PDT 24
Peak memory 193008 kb
Host smart-3fe4786b-bc37-41fd-98ce-b7f485583e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751882667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1751882667
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2600008943
Short name T456
Test name
Test status
Simulation time 635742066 ps
CPU time 4.79 seconds
Started Jun 27 04:23:03 PM PDT 24
Finished Jun 27 04:23:11 PM PDT 24
Peak memory 197000 kb
Host smart-14ec58e0-9eba-4e8a-b736-fc2c33ec7b5a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600008943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2600008943
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.845583383
Short name T239
Test name
Test status
Simulation time 34951749 ps
CPU time 0.58 seconds
Started Jun 27 04:23:30 PM PDT 24
Finished Jun 27 04:23:44 PM PDT 24
Peak memory 194688 kb
Host smart-c60a9b9d-a3c5-4ad9-a0bc-104d9f25f001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845583383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.845583383
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1725328866
Short name T191
Test name
Test status
Simulation time 48418315 ps
CPU time 0.93 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 196284 kb
Host smart-265ca991-1f28-4361-b441-61300d733fcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725328866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1725328866
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1881373709
Short name T518
Test name
Test status
Simulation time 240909870 ps
CPU time 2.54 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:17 PM PDT 24
Peak memory 195592 kb
Host smart-40f96666-866a-4edc-b50c-cafba05ff9c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881373709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1881373709
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.342808227
Short name T668
Test name
Test status
Simulation time 44654738 ps
CPU time 0.89 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:15 PM PDT 24
Peak memory 195716 kb
Host smart-c49e1919-a0f2-4d5b-846b-c69a6ff79d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342808227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
342808227
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2387546347
Short name T660
Test name
Test status
Simulation time 226899189 ps
CPU time 0.8 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:19 PM PDT 24
Peak memory 196896 kb
Host smart-d611654b-cbfa-4fa6-8b36-ff263a29bc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387546347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2387546347
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2063976420
Short name T614
Test name
Test status
Simulation time 396626058 ps
CPU time 0.72 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:23 PM PDT 24
Peak memory 195756 kb
Host smart-80018c4c-771a-403f-800b-a8ac5d6d9119
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063976420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2063976420
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4118018781
Short name T6
Test name
Test status
Simulation time 467659899 ps
CPU time 1.66 seconds
Started Jun 27 04:21:51 PM PDT 24
Finished Jun 27 04:21:54 PM PDT 24
Peak memory 197792 kb
Host smart-4899f054-467c-40ce-ae3e-971d12958f07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118018781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4118018781
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.4012871372
Short name T674
Test name
Test status
Simulation time 110160454 ps
CPU time 0.91 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 196908 kb
Host smart-9b538d27-58aa-4e31-bbaa-4efe76add48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012871372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.4012871372
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2580992940
Short name T167
Test name
Test status
Simulation time 156272875 ps
CPU time 1.12 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 196712 kb
Host smart-977e965d-7a7b-4901-acf6-43d852ff3933
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580992940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2580992940
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3651503996
Short name T498
Test name
Test status
Simulation time 31687399804 ps
CPU time 78.44 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:24:42 PM PDT 24
Peak memory 198492 kb
Host smart-2e70c698-3e85-4579-9ed8-9b7783e77501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651503996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3651503996
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2850762068
Short name T9
Test name
Test status
Simulation time 72170176090 ps
CPU time 526.04 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:32:04 PM PDT 24
Peak memory 198720 kb
Host smart-8b7fd6ff-e954-4e7e-975f-99c50701a69b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2850762068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2850762068
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3775418319
Short name T578
Test name
Test status
Simulation time 154662702 ps
CPU time 0.67 seconds
Started Jun 27 04:23:00 PM PDT 24
Finished Jun 27 04:23:04 PM PDT 24
Peak memory 193912 kb
Host smart-02d36371-250c-433a-bd28-686f17773db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775418319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3775418319
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3725106440
Short name T714
Test name
Test status
Simulation time 32288441 ps
CPU time 0.79 seconds
Started Jun 27 04:23:29 PM PDT 24
Finished Jun 27 04:23:44 PM PDT 24
Peak memory 195500 kb
Host smart-ba87ee47-0582-4c12-8b64-c8d97d811ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725106440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3725106440
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3930817626
Short name T145
Test name
Test status
Simulation time 541467316 ps
CPU time 15.15 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:29 PM PDT 24
Peak memory 196404 kb
Host smart-61f38c26-7f4e-4367-8896-bdb1b817ff25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930817626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3930817626
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2173629902
Short name T216
Test name
Test status
Simulation time 28593692 ps
CPU time 0.65 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 195032 kb
Host smart-c145ee03-145c-421d-b1bb-a35b9b6b0d9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173629902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2173629902
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.320704795
Short name T367
Test name
Test status
Simulation time 22250062 ps
CPU time 0.8 seconds
Started Jun 27 04:23:00 PM PDT 24
Finished Jun 27 04:23:04 PM PDT 24
Peak memory 193568 kb
Host smart-84497bce-3e90-4fab-affe-f4e479c9f7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320704795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.320704795
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1281885691
Short name T310
Test name
Test status
Simulation time 68594945 ps
CPU time 2.78 seconds
Started Jun 27 04:22:59 PM PDT 24
Finished Jun 27 04:23:03 PM PDT 24
Peak memory 196820 kb
Host smart-b5222690-661c-4adc-a488-037b359b9ade
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281885691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1281885691
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2426474163
Short name T95
Test name
Test status
Simulation time 114114983 ps
CPU time 1.67 seconds
Started Jun 27 04:23:29 PM PDT 24
Finished Jun 27 04:23:45 PM PDT 24
Peak memory 196864 kb
Host smart-05820482-9ab7-4cd1-b38e-62ecb5784246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426474163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2426474163
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2451563073
Short name T113
Test name
Test status
Simulation time 69686541 ps
CPU time 0.71 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:15 PM PDT 24
Peak memory 192600 kb
Host smart-8ebb94f0-dc57-4fa2-84c4-7e115a003a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451563073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2451563073
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1754318737
Short name T365
Test name
Test status
Simulation time 44564432 ps
CPU time 1 seconds
Started Jun 27 04:21:51 PM PDT 24
Finished Jun 27 04:21:53 PM PDT 24
Peak memory 196536 kb
Host smart-d24b396b-b7c8-46fa-95a3-1d983979d20b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754318737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1754318737
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3059079022
Short name T525
Test name
Test status
Simulation time 434829447 ps
CPU time 1.99 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:21 PM PDT 24
Peak memory 197020 kb
Host smart-9dad68d2-9e56-4e45-80a2-a522dad1c6f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059079022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3059079022
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1211296281
Short name T159
Test name
Test status
Simulation time 60905013 ps
CPU time 0.96 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:20 PM PDT 24
Peak memory 195464 kb
Host smart-75434ba1-505e-4a04-a9ef-ddece39bace1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211296281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1211296281
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4240837132
Short name T547
Test name
Test status
Simulation time 97196475 ps
CPU time 1.48 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:16 PM PDT 24
Peak memory 198132 kb
Host smart-61b2c541-17a5-4592-b625-0409fe7064d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240837132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4240837132
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3971323612
Short name T307
Test name
Test status
Simulation time 44792100374 ps
CPU time 148.72 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:25:49 PM PDT 24
Peak memory 198548 kb
Host smart-8d5d05b2-58ea-459b-927e-0ccba1ef7609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971323612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3971323612
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2158571518
Short name T665
Test name
Test status
Simulation time 42713347 ps
CPU time 0.68 seconds
Started Jun 27 04:23:03 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 192932 kb
Host smart-d0545c04-d746-41e6-88a0-20a09774776c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158571518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2158571518
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1960572773
Short name T314
Test name
Test status
Simulation time 59008682 ps
CPU time 0.71 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:20 PM PDT 24
Peak memory 195652 kb
Host smart-d067da94-7c37-43b1-862e-cc4824d06530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960572773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1960572773
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2279577942
Short name T323
Test name
Test status
Simulation time 1061524884 ps
CPU time 26.29 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:40 PM PDT 24
Peak memory 195432 kb
Host smart-5327e392-faf8-47b7-81af-1132d6462500
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279577942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2279577942
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3763389379
Short name T200
Test name
Test status
Simulation time 54204316 ps
CPU time 0.89 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:15 PM PDT 24
Peak memory 193428 kb
Host smart-c14f47d6-9390-4e8a-8b41-4582a74e4b51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763389379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3763389379
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.202588489
Short name T644
Test name
Test status
Simulation time 203202199 ps
CPU time 1.27 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:23 PM PDT 24
Peak memory 197460 kb
Host smart-79d7be0d-d1aa-41cf-a3dc-d1384d5f54e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202588489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.202588489
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2020914233
Short name T135
Test name
Test status
Simulation time 361462056 ps
CPU time 3.22 seconds
Started Jun 27 04:23:18 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 196904 kb
Host smart-14628bd7-7e59-4f3f-a15e-bd01c9cbc319
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020914233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2020914233
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.440918551
Short name T556
Test name
Test status
Simulation time 495784310 ps
CPU time 1.66 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:21 PM PDT 24
Peak memory 195292 kb
Host smart-8ee20cb1-0314-4dae-8e87-fa4af8f54735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440918551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
440918551
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.519261727
Short name T121
Test name
Test status
Simulation time 213830447 ps
CPU time 1.19 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:21 PM PDT 24
Peak memory 197488 kb
Host smart-1e507fac-b9e4-4ece-83b5-143b61b536b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519261727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.519261727
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3065075587
Short name T141
Test name
Test status
Simulation time 116929316 ps
CPU time 0.86 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 196252 kb
Host smart-eaf7fa44-7d9e-4bdf-9100-c3496a24741f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065075587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3065075587
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4174081602
Short name T4
Test name
Test status
Simulation time 2020961106 ps
CPU time 5.73 seconds
Started Jun 27 04:21:51 PM PDT 24
Finished Jun 27 04:21:57 PM PDT 24
Peak memory 198516 kb
Host smart-85f14725-e983-49b6-a2ab-f7cd67c3ff52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174081602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4174081602
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2327650229
Short name T636
Test name
Test status
Simulation time 151445653 ps
CPU time 1.19 seconds
Started Jun 27 04:23:09 PM PDT 24
Finished Jun 27 04:23:15 PM PDT 24
Peak memory 194328 kb
Host smart-f67fd03e-e383-4de8-bf5c-2cef608ab769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327650229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2327650229
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1360308913
Short name T477
Test name
Test status
Simulation time 60510510 ps
CPU time 0.88 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 196212 kb
Host smart-1d917e0a-d4f9-4491-909f-0ba31f6a592c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360308913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1360308913
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1610898865
Short name T388
Test name
Test status
Simulation time 30882326905 ps
CPU time 188.19 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:26:30 PM PDT 24
Peak memory 198532 kb
Host smart-5aaaf313-a3fa-411b-9d2c-1fcaa89ca7af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610898865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1610898865
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2884577357
Short name T438
Test name
Test status
Simulation time 14812564 ps
CPU time 0.61 seconds
Started Jun 27 04:22:12 PM PDT 24
Finished Jun 27 04:22:14 PM PDT 24
Peak memory 194448 kb
Host smart-48c498a0-6e39-4f0f-8652-8294e548e447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884577357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2884577357
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2491484842
Short name T473
Test name
Test status
Simulation time 26473684 ps
CPU time 0.68 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 196356 kb
Host smart-6ebdffa6-e29f-465b-9716-9d4916e1b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491484842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2491484842
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.582942689
Short name T341
Test name
Test status
Simulation time 506065327 ps
CPU time 25.73 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:24:22 PM PDT 24
Peak memory 195808 kb
Host smart-f8e0beee-c93b-4515-956d-50854df916bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582942689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.582942689
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1647278205
Short name T597
Test name
Test status
Simulation time 41534370 ps
CPU time 0.8 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:34 PM PDT 24
Peak memory 195548 kb
Host smart-6bcc8864-a216-43a7-b133-72d5e8b24b76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647278205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1647278205
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.4280313350
Short name T416
Test name
Test status
Simulation time 202664135 ps
CPU time 1.29 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:21 PM PDT 24
Peak memory 197476 kb
Host smart-e0dd0755-a39c-47c9-b139-bcf2e217da23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280313350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.4280313350
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1023317829
Short name T173
Test name
Test status
Simulation time 217289720 ps
CPU time 2.17 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:48 PM PDT 24
Peak memory 198396 kb
Host smart-851c9298-12df-4f72-af91-1a641388bcdc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023317829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1023317829
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.970315633
Short name T638
Test name
Test status
Simulation time 70439036 ps
CPU time 1.96 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:27 PM PDT 24
Peak memory 197340 kb
Host smart-1b76138f-a8fd-43b4-b5f6-ced5bba82bc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970315633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
970315633
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.71326963
Short name T703
Test name
Test status
Simulation time 237453508 ps
CPU time 1.02 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 196260 kb
Host smart-a9a117ef-a875-4d43-9601-1d866d176b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71326963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.71326963
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.724994475
Short name T324
Test name
Test status
Simulation time 120353096 ps
CPU time 1.22 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:33 PM PDT 24
Peak memory 196284 kb
Host smart-b5d6aba3-256d-4262-8354-a65c25f472d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724994475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.724994475
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2626083296
Short name T583
Test name
Test status
Simulation time 235952354 ps
CPU time 3.62 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 197768 kb
Host smart-633ef2ea-df3e-41e8-84e6-90c1e43fd6b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626083296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2626083296
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.201859051
Short name T14
Test name
Test status
Simulation time 27631462 ps
CPU time 0.75 seconds
Started Jun 27 04:23:14 PM PDT 24
Finished Jun 27 04:23:19 PM PDT 24
Peak memory 195672 kb
Host smart-907d3d87-5528-45a7-a2e8-485fbe83b053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201859051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.201859051
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1216676455
Short name T290
Test name
Test status
Simulation time 59080628 ps
CPU time 1.07 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:23:30 PM PDT 24
Peak memory 196292 kb
Host smart-5238504e-787c-4eb6-8e5d-ef9c78cf149e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216676455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1216676455
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.285441720
Short name T511
Test name
Test status
Simulation time 4016815868 ps
CPU time 51.21 seconds
Started Jun 27 04:23:41 PM PDT 24
Finished Jun 27 04:24:47 PM PDT 24
Peak memory 198352 kb
Host smart-ef63666d-1606-46ea-a667-a5a1bedc2baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285441720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.285441720
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.114468253
Short name T549
Test name
Test status
Simulation time 11811962 ps
CPU time 0.56 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 194932 kb
Host smart-e1ee93ae-97e2-49f7-ba70-c46d2089f069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114468253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.114468253
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2361701530
Short name T493
Test name
Test status
Simulation time 152555903 ps
CPU time 0.82 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 196272 kb
Host smart-703a8a74-68c4-4db6-9e75-8f2c3fb02c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361701530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2361701530
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4250459726
Short name T201
Test name
Test status
Simulation time 253019147 ps
CPU time 12.01 seconds
Started Jun 27 04:22:15 PM PDT 24
Finished Jun 27 04:22:28 PM PDT 24
Peak memory 197508 kb
Host smart-064eaa79-e7cb-4352-8075-d408309b3bb0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250459726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4250459726
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2532030980
Short name T150
Test name
Test status
Simulation time 92031435 ps
CPU time 1.25 seconds
Started Jun 27 04:22:09 PM PDT 24
Finished Jun 27 04:22:10 PM PDT 24
Peak memory 197240 kb
Host smart-a5423666-1322-480d-a18f-0905e1e2ff92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532030980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2532030980
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3258619212
Short name T464
Test name
Test status
Simulation time 577418980 ps
CPU time 0.85 seconds
Started Jun 27 04:22:04 PM PDT 24
Finished Jun 27 04:22:05 PM PDT 24
Peak memory 197388 kb
Host smart-3482ceff-3b53-4a4d-ad91-acadfa6e70ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258619212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3258619212
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3003117494
Short name T504
Test name
Test status
Simulation time 204390624 ps
CPU time 2.89 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:51 PM PDT 24
Peak memory 197056 kb
Host smart-42351ccf-47df-4f8d-bd9e-65c481e3953f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003117494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3003117494
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2043673419
Short name T233
Test name
Test status
Simulation time 63218648 ps
CPU time 0.92 seconds
Started Jun 27 04:23:41 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 196524 kb
Host smart-5962fda0-96fc-4a03-ad7b-9c0b33ced0f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043673419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2043673419
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.795790765
Short name T645
Test name
Test status
Simulation time 146517036 ps
CPU time 0.86 seconds
Started Jun 27 04:22:07 PM PDT 24
Finished Jun 27 04:22:09 PM PDT 24
Peak memory 196588 kb
Host smart-b61d1a63-680c-4354-854c-316aec197434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795790765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.795790765
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1928432455
Short name T430
Test name
Test status
Simulation time 137643729 ps
CPU time 1.55 seconds
Started Jun 27 04:22:09 PM PDT 24
Finished Jun 27 04:22:11 PM PDT 24
Peak memory 197976 kb
Host smart-1c7c8fb9-d87a-490c-a991-2f3cd231d780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928432455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1928432455
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.4051661104
Short name T129
Test name
Test status
Simulation time 91757512 ps
CPU time 3.89 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 198212 kb
Host smart-cedabe6f-7755-42b2-848b-b9880f656606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051661104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.4051661104
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1174693777
Short name T199
Test name
Test status
Simulation time 289106564 ps
CPU time 1.11 seconds
Started Jun 27 04:22:08 PM PDT 24
Finished Jun 27 04:22:10 PM PDT 24
Peak memory 196108 kb
Host smart-2b0de323-8928-410c-9f70-e2099e78546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174693777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1174693777
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.866411242
Short name T272
Test name
Test status
Simulation time 91558940 ps
CPU time 1.32 seconds
Started Jun 27 04:22:07 PM PDT 24
Finished Jun 27 04:22:10 PM PDT 24
Peak memory 197544 kb
Host smart-1da79498-ddac-4699-88b8-8dd4330b30ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866411242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.866411242
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1526086956
Short name T386
Test name
Test status
Simulation time 2937408147 ps
CPU time 26.92 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:24:16 PM PDT 24
Peak memory 198404 kb
Host smart-ce7a27d8-322b-49b8-b720-d3c9a75fe393
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526086956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1526086956
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3319360437
Short name T45
Test name
Test status
Simulation time 21268170494 ps
CPU time 560.06 seconds
Started Jun 27 04:22:04 PM PDT 24
Finished Jun 27 04:31:25 PM PDT 24
Peak memory 198888 kb
Host smart-d9201a73-ed97-47d2-8532-313163c109dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3319360437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3319360437
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2247612548
Short name T515
Test name
Test status
Simulation time 44637692 ps
CPU time 0.57 seconds
Started Jun 27 04:22:15 PM PDT 24
Finished Jun 27 04:22:17 PM PDT 24
Peak memory 194440 kb
Host smart-92f38cc5-69a0-41f9-ae36-98810786f9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247612548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2247612548
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.200952186
Short name T392
Test name
Test status
Simulation time 81658192 ps
CPU time 0.75 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 193212 kb
Host smart-5ed5c16f-9e44-4c54-bd46-62c3d712a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200952186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.200952186
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3164916716
Short name T336
Test name
Test status
Simulation time 1256913902 ps
CPU time 15.94 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:24:04 PM PDT 24
Peak memory 195344 kb
Host smart-e3ddae75-dd95-4ff7-8d11-823db6e30d12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164916716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3164916716
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2079902237
Short name T555
Test name
Test status
Simulation time 58910486 ps
CPU time 0.81 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 197292 kb
Host smart-a484618d-71d6-455c-81e9-31f8aa43af37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079902237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2079902237
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2088686178
Short name T411
Test name
Test status
Simulation time 323869297 ps
CPU time 1.17 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 196184 kb
Host smart-3196b043-99ae-4aca-912e-e1d20637bf5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088686178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2088686178
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2129506946
Short name T90
Test name
Test status
Simulation time 28076431 ps
CPU time 1.12 seconds
Started Jun 27 04:22:07 PM PDT 24
Finished Jun 27 04:22:09 PM PDT 24
Peak memory 197884 kb
Host smart-bd620785-3d61-4497-a1d0-d206a90b0f9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129506946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2129506946
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3626171364
Short name T86
Test name
Test status
Simulation time 45402604 ps
CPU time 1.21 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 196424 kb
Host smart-3157fdc0-42af-41a8-95cf-e343ca370260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626171364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3626171364
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1863757651
Short name T705
Test name
Test status
Simulation time 29662844 ps
CPU time 0.81 seconds
Started Jun 27 04:22:12 PM PDT 24
Finished Jun 27 04:22:14 PM PDT 24
Peak memory 195824 kb
Host smart-4c3f16a9-2b67-43fe-a7c8-ddf17f98e822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863757651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1863757651
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3480662842
Short name T432
Test name
Test status
Simulation time 161686246 ps
CPU time 0.9 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 197040 kb
Host smart-656ef06e-956c-479e-ad47-0046320a3398
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480662842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3480662842
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1019434206
Short name T235
Test name
Test status
Simulation time 459733170 ps
CPU time 5.04 seconds
Started Jun 27 04:22:16 PM PDT 24
Finished Jun 27 04:22:22 PM PDT 24
Peak memory 198400 kb
Host smart-2b9a2c2e-cd76-4c7a-8cec-55f640461391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019434206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1019434206
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1274902003
Short name T394
Test name
Test status
Simulation time 46584314 ps
CPU time 1.15 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 196004 kb
Host smart-7c2b8c6e-6570-41f5-b0cd-cba8684552df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274902003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1274902003
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2520502065
Short name T502
Test name
Test status
Simulation time 54793562 ps
CPU time 1.03 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 196052 kb
Host smart-abca63a6-4afe-4ba9-ab3f-fa20aa815a89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520502065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2520502065
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1861642967
Short name T396
Test name
Test status
Simulation time 19067791896 ps
CPU time 62.18 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:24:52 PM PDT 24
Peak memory 198460 kb
Host smart-bf139389-5612-4f18-a70e-a77b2ac622be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861642967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1861642967
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3729702849
Short name T226
Test name
Test status
Simulation time 21475172 ps
CPU time 0.57 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 193380 kb
Host smart-42e70f35-1ede-46a2-a218-68456ea97f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729702849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3729702849
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3918798203
Short name T315
Test name
Test status
Simulation time 24767010 ps
CPU time 0.78 seconds
Started Jun 27 04:21:37 PM PDT 24
Finished Jun 27 04:21:38 PM PDT 24
Peak memory 196084 kb
Host smart-649c702a-2217-49f9-96ee-62eb4fa8894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918798203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3918798203
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2836317179
Short name T582
Test name
Test status
Simulation time 432810025 ps
CPU time 11.13 seconds
Started Jun 27 04:20:22 PM PDT 24
Finished Jun 27 04:20:36 PM PDT 24
Peak memory 198532 kb
Host smart-02d29b00-db7d-4c91-8b17-96283d8a1ee5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836317179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2836317179
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2417916214
Short name T120
Test name
Test status
Simulation time 41236666 ps
CPU time 0.73 seconds
Started Jun 27 04:23:24 PM PDT 24
Finished Jun 27 04:23:37 PM PDT 24
Peak memory 196296 kb
Host smart-17d257fb-3c66-4ecd-b283-ee3972743172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417916214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2417916214
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.774912496
Short name T333
Test name
Test status
Simulation time 119152282 ps
CPU time 1.06 seconds
Started Jun 27 04:21:19 PM PDT 24
Finished Jun 27 04:21:21 PM PDT 24
Peak memory 196464 kb
Host smart-c75f2072-71f1-418e-ad39-7a7dc7d90eeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774912496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.774912496
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1959820817
Short name T495
Test name
Test status
Simulation time 109503261 ps
CPU time 1.34 seconds
Started Jun 27 04:20:28 PM PDT 24
Finished Jun 27 04:20:30 PM PDT 24
Peak memory 196956 kb
Host smart-b6ff4f3b-646c-4b3c-8c00-9ff67cadc6d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959820817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1959820817
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3196981655
Short name T97
Test name
Test status
Simulation time 117373596 ps
CPU time 1.95 seconds
Started Jun 27 04:20:25 PM PDT 24
Finished Jun 27 04:20:28 PM PDT 24
Peak memory 197196 kb
Host smart-963e26c2-05d8-4919-b35e-c7d44755b766
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196981655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3196981655
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.379224996
Short name T198
Test name
Test status
Simulation time 231538145 ps
CPU time 0.93 seconds
Started Jun 27 04:23:40 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 196140 kb
Host smart-0d546cea-526d-4c61-bacf-4c18a341eb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379224996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.379224996
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1017832799
Short name T612
Test name
Test status
Simulation time 71205037 ps
CPU time 0.9 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 196968 kb
Host smart-ca048b2e-d464-432c-a221-80e069f93eb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017832799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1017832799
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1776234737
Short name T697
Test name
Test status
Simulation time 254482575 ps
CPU time 2.82 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:26 PM PDT 24
Peak memory 198308 kb
Host smart-ea727ded-f928-4788-ab02-0b4c464aee1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776234737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1776234737
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2183082669
Short name T43
Test name
Test status
Simulation time 369436800 ps
CPU time 0.85 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 213452 kb
Host smart-d58eee80-85e4-40ba-b33f-07de8b4f0c50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183082669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2183082669
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.4181903635
Short name T134
Test name
Test status
Simulation time 529478760 ps
CPU time 0.92 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:23 PM PDT 24
Peak memory 196136 kb
Host smart-f74dc0f0-e129-4bf5-adba-6f43eedafde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181903635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.4181903635
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4080683066
Short name T584
Test name
Test status
Simulation time 63576536 ps
CPU time 0.96 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 195900 kb
Host smart-0fb084f3-a07b-47ad-ba6e-19598a22f280
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080683066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4080683066
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.939017663
Short name T509
Test name
Test status
Simulation time 38883881396 ps
CPU time 94 seconds
Started Jun 27 04:23:24 PM PDT 24
Finished Jun 27 04:25:10 PM PDT 24
Peak memory 198588 kb
Host smart-260c3623-e7ac-4cfd-bbfe-78ede6ebf149
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939017663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.939017663
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.4113734925
Short name T591
Test name
Test status
Simulation time 125523236270 ps
CPU time 564.3 seconds
Started Jun 27 04:22:55 PM PDT 24
Finished Jun 27 04:32:20 PM PDT 24
Peak memory 198664 kb
Host smart-e2bee4a4-1128-4a0c-ae24-2a07c641bd28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4113734925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.4113734925
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3588508334
Short name T34
Test name
Test status
Simulation time 23725189 ps
CPU time 0.6 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:29 PM PDT 24
Peak memory 194876 kb
Host smart-7241323c-1dbb-41cd-ad65-9917d3e2bcf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588508334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3588508334
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4093548390
Short name T297
Test name
Test status
Simulation time 301711311 ps
CPU time 0.89 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:29 PM PDT 24
Peak memory 196796 kb
Host smart-c68cde4f-a389-486a-adaa-35ea4affd47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093548390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4093548390
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1867191765
Short name T520
Test name
Test status
Simulation time 444589333 ps
CPU time 12.54 seconds
Started Jun 27 04:22:27 PM PDT 24
Finished Jun 27 04:22:41 PM PDT 24
Peak memory 197788 kb
Host smart-e7513a4e-c7ed-47b9-9525-49814af47615
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867191765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1867191765
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.177854871
Short name T573
Test name
Test status
Simulation time 61549407 ps
CPU time 0.96 seconds
Started Jun 27 04:22:27 PM PDT 24
Finished Jun 27 04:22:30 PM PDT 24
Peak memory 196948 kb
Host smart-0eed18c3-b84a-42bd-a304-6cb75802b2d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177854871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.177854871
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.528729873
Short name T632
Test name
Test status
Simulation time 411387705 ps
CPU time 1.06 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:29 PM PDT 24
Peak memory 196616 kb
Host smart-178fdda6-a667-4919-95ca-00c7c710cdf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528729873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.528729873
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1256427518
Short name T640
Test name
Test status
Simulation time 92335514 ps
CPU time 1.47 seconds
Started Jun 27 04:22:21 PM PDT 24
Finished Jun 27 04:22:24 PM PDT 24
Peak memory 197128 kb
Host smart-bea5101b-e96a-4a7e-8037-6e0d4c0d2b94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256427518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1256427518
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3553073735
Short name T594
Test name
Test status
Simulation time 147665924 ps
CPU time 3.03 seconds
Started Jun 27 04:22:24 PM PDT 24
Finished Jun 27 04:22:28 PM PDT 24
Peak memory 198516 kb
Host smart-080fb061-3923-440a-bac0-11910476a452
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553073735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3553073735
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.666338947
Short name T252
Test name
Test status
Simulation time 31735707 ps
CPU time 1.15 seconds
Started Jun 27 04:22:12 PM PDT 24
Finished Jun 27 04:22:15 PM PDT 24
Peak memory 197584 kb
Host smart-d770c6c9-090d-415f-90d8-7c84c6ed80c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666338947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.666338947
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3129452636
Short name T413
Test name
Test status
Simulation time 73482731 ps
CPU time 0.89 seconds
Started Jun 27 04:22:22 PM PDT 24
Finished Jun 27 04:22:24 PM PDT 24
Peak memory 196496 kb
Host smart-ce1afca7-a1bb-4700-8db8-4bd560890196
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129452636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3129452636
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3420469424
Short name T648
Test name
Test status
Simulation time 180846766 ps
CPU time 3.18 seconds
Started Jun 27 04:22:23 PM PDT 24
Finished Jun 27 04:22:27 PM PDT 24
Peak memory 198440 kb
Host smart-5bd99c19-37bf-4568-81bc-18b9261865a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420469424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3420469424
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.62525949
Short name T115
Test name
Test status
Simulation time 264430921 ps
CPU time 0.89 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 196044 kb
Host smart-fd3bfe9f-ebc2-49f4-9070-13eee24868b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62525949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.62525949
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3519100425
Short name T469
Test name
Test status
Simulation time 635933546 ps
CPU time 1.19 seconds
Started Jun 27 04:22:07 PM PDT 24
Finished Jun 27 04:22:10 PM PDT 24
Peak memory 196580 kb
Host smart-f19d05d3-0f8b-45fb-b05f-14088f1257e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519100425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3519100425
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1543993188
Short name T130
Test name
Test status
Simulation time 7227203253 ps
CPU time 98.19 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:25:38 PM PDT 24
Peak memory 197292 kb
Host smart-c911f2f2-3545-484d-8054-5e4d9f2c243d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543993188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1543993188
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.671407172
Short name T694
Test name
Test status
Simulation time 30140874392 ps
CPU time 799.41 seconds
Started Jun 27 04:22:21 PM PDT 24
Finished Jun 27 04:35:41 PM PDT 24
Peak memory 199108 kb
Host smart-97180928-50af-45cc-b399-11cd8dd286e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=671407172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.671407172
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.4202901865
Short name T588
Test name
Test status
Simulation time 44867181 ps
CPU time 0.6 seconds
Started Jun 27 04:22:30 PM PDT 24
Finished Jun 27 04:22:32 PM PDT 24
Peak memory 193416 kb
Host smart-9ca39e30-d07b-4c5d-9dad-0bd8d652c096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202901865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.4202901865
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.4149384692
Short name T546
Test name
Test status
Simulation time 33438822 ps
CPU time 0.81 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 194552 kb
Host smart-5d475e5c-6f7d-41e8-b8f0-17c08db83503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149384692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.4149384692
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3639880510
Short name T219
Test name
Test status
Simulation time 3178205307 ps
CPU time 24.99 seconds
Started Jun 27 04:22:30 PM PDT 24
Finished Jun 27 04:22:56 PM PDT 24
Peak memory 198736 kb
Host smart-0ed946f4-7cc1-4350-81e6-342cffc14fcb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639880510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3639880510
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1940082175
Short name T371
Test name
Test status
Simulation time 212500313 ps
CPU time 0.83 seconds
Started Jun 27 04:22:22 PM PDT 24
Finished Jun 27 04:22:24 PM PDT 24
Peak memory 197156 kb
Host smart-ab566373-3266-4db6-81b5-7d56251cd8c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940082175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1940082175
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3113123933
Short name T298
Test name
Test status
Simulation time 667279865 ps
CPU time 1.37 seconds
Started Jun 27 04:22:23 PM PDT 24
Finished Jun 27 04:22:26 PM PDT 24
Peak memory 198572 kb
Host smart-d20a31b3-b029-47cb-99dd-de9330c5eda4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113123933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3113123933
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2239114094
Short name T713
Test name
Test status
Simulation time 318447872 ps
CPU time 3.2 seconds
Started Jun 27 04:22:27 PM PDT 24
Finished Jun 27 04:22:32 PM PDT 24
Peak memory 196884 kb
Host smart-71799db3-5eec-4df1-a192-eae8a1109cb7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239114094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2239114094
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1293150766
Short name T408
Test name
Test status
Simulation time 1534322517 ps
CPU time 2.38 seconds
Started Jun 27 04:22:21 PM PDT 24
Finished Jun 27 04:22:24 PM PDT 24
Peak memory 197036 kb
Host smart-84152eae-0cca-4fb1-b525-91eecd92f757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293150766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1293150766
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2545872218
Short name T117
Test name
Test status
Simulation time 57262613 ps
CPU time 1.02 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:28 PM PDT 24
Peak memory 196488 kb
Host smart-c26cee30-02df-427b-b659-2635b4dce289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545872218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2545872218
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.924413130
Short name T103
Test name
Test status
Simulation time 31959724 ps
CPU time 0.77 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:28 PM PDT 24
Peak memory 196952 kb
Host smart-b01b2750-9e9b-4021-9d7f-5e2f715c4991
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924413130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.924413130
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.777325698
Short name T276
Test name
Test status
Simulation time 476598820 ps
CPU time 5.56 seconds
Started Jun 27 04:22:27 PM PDT 24
Finished Jun 27 04:22:35 PM PDT 24
Peak memory 198404 kb
Host smart-2321d2fd-c87d-4c2c-afaa-8fc6053985ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777325698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.777325698
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3239843702
Short name T162
Test name
Test status
Simulation time 54257763 ps
CPU time 0.75 seconds
Started Jun 27 04:22:16 PM PDT 24
Finished Jun 27 04:22:18 PM PDT 24
Peak memory 196444 kb
Host smart-6c7265f7-908f-4fe4-b0aa-2159fcfde1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239843702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3239843702
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4194895086
Short name T679
Test name
Test status
Simulation time 55463128 ps
CPU time 0.89 seconds
Started Jun 27 04:22:24 PM PDT 24
Finished Jun 27 04:22:26 PM PDT 24
Peak memory 195888 kb
Host smart-25b48338-b94a-47be-b169-9a0b3971dac6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194895086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4194895086
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3745875672
Short name T300
Test name
Test status
Simulation time 18212164314 ps
CPU time 124.41 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:24:33 PM PDT 24
Peak memory 198652 kb
Host smart-834b5fee-dfa3-46e4-8a0d-637f17530eee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745875672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3745875672
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3858546188
Short name T27
Test name
Test status
Simulation time 23036632600 ps
CPU time 753.81 seconds
Started Jun 27 04:22:24 PM PDT 24
Finished Jun 27 04:34:59 PM PDT 24
Peak memory 198768 kb
Host smart-6c7944f3-4edd-4b17-81e2-09eff3af4e7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3858546188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3858546188
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.470172183
Short name T688
Test name
Test status
Simulation time 21839898 ps
CPU time 0.6 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 194716 kb
Host smart-d009b615-4ee7-4445-8d2a-8155ffab7800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470172183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.470172183
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2997449378
Short name T208
Test name
Test status
Simulation time 69947181 ps
CPU time 0.89 seconds
Started Jun 27 04:22:23 PM PDT 24
Finished Jun 27 04:22:25 PM PDT 24
Peak memory 197748 kb
Host smart-875af843-9d54-4b11-8a65-aedcb2775978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997449378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2997449378
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.939251630
Short name T100
Test name
Test status
Simulation time 1650040485 ps
CPU time 22.3 seconds
Started Jun 27 04:22:27 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 197600 kb
Host smart-9c2cc5e7-aead-4827-8107-1abf79eda91e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939251630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.939251630
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1402286574
Short name T580
Test name
Test status
Simulation time 60691709 ps
CPU time 0.88 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:44 PM PDT 24
Peak memory 196848 kb
Host smart-bd31915f-43f4-4fff-bbe6-4459c5ed7a00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402286574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1402286574
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3707790731
Short name T182
Test name
Test status
Simulation time 46356492 ps
CPU time 0.99 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:28 PM PDT 24
Peak memory 197244 kb
Host smart-ddde3965-216a-4ba3-8a48-15bff8241911
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707790731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3707790731
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1170866579
Short name T138
Test name
Test status
Simulation time 33706033 ps
CPU time 1.36 seconds
Started Jun 27 04:22:16 PM PDT 24
Finished Jun 27 04:22:19 PM PDT 24
Peak memory 197408 kb
Host smart-217ad4c7-c5ca-4a9f-8fe0-6fa9e1127da0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170866579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1170866579
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3667604267
Short name T50
Test name
Test status
Simulation time 209741862 ps
CPU time 1.3 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:29 PM PDT 24
Peak memory 196624 kb
Host smart-ee1f4fda-c198-4281-b2ec-3bf8fae290fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667604267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3667604267
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4158880331
Short name T624
Test name
Test status
Simulation time 70055708 ps
CPU time 1.49 seconds
Started Jun 27 04:22:30 PM PDT 24
Finished Jun 27 04:22:32 PM PDT 24
Peak memory 197296 kb
Host smart-db2c968c-6b83-45b9-b3cc-3b38f05a8d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158880331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4158880331
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3428257789
Short name T414
Test name
Test status
Simulation time 118692339 ps
CPU time 1.42 seconds
Started Jun 27 04:22:25 PM PDT 24
Finished Jun 27 04:22:27 PM PDT 24
Peak memory 197652 kb
Host smart-ee7594c4-022f-436b-bd98-5ec969da4f26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428257789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3428257789
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2052835669
Short name T572
Test name
Test status
Simulation time 107263618 ps
CPU time 5.39 seconds
Started Jun 27 04:22:30 PM PDT 24
Finished Jun 27 04:22:36 PM PDT 24
Peak memory 198620 kb
Host smart-3a664f43-d7e3-40bb-9654-db91b479c436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052835669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2052835669
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1772217348
Short name T228
Test name
Test status
Simulation time 130336815 ps
CPU time 1.04 seconds
Started Jun 27 04:22:22 PM PDT 24
Finished Jun 27 04:22:24 PM PDT 24
Peak memory 196756 kb
Host smart-d39716de-d2c6-4046-8101-ecbc31a81437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772217348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1772217348
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.515009287
Short name T559
Test name
Test status
Simulation time 201155894 ps
CPU time 0.97 seconds
Started Jun 27 04:22:26 PM PDT 24
Finished Jun 27 04:22:29 PM PDT 24
Peak memory 197024 kb
Host smart-a2691d94-34f7-4db5-80ea-197e37f66eb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515009287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.515009287
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2629652908
Short name T204
Test name
Test status
Simulation time 33735869554 ps
CPU time 221.04 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:26:27 PM PDT 24
Peak memory 198740 kb
Host smart-2f012b80-8d09-428d-bc4b-761691cf0fb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629652908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2629652908
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1970332602
Short name T716
Test name
Test status
Simulation time 14291318 ps
CPU time 0.56 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 194352 kb
Host smart-9749e4de-ce2b-4dd4-945f-fa760e28bc2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970332602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1970332602
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3501027613
Short name T51
Test name
Test status
Simulation time 26733194 ps
CPU time 0.76 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 194960 kb
Host smart-33d1d1b6-62d6-48ab-b036-c6d5361b3d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501027613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3501027613
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2290912289
Short name T131
Test name
Test status
Simulation time 2768318300 ps
CPU time 22.74 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:23:09 PM PDT 24
Peak memory 197444 kb
Host smart-e535e51b-939f-49b3-b8de-086e74925009
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290912289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2290912289
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.221324832
Short name T426
Test name
Test status
Simulation time 73554223 ps
CPU time 0.97 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 198224 kb
Host smart-7949060d-22ec-4c5a-8e81-2ad09dacbfba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221324832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.221324832
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.778694651
Short name T247
Test name
Test status
Simulation time 21757750 ps
CPU time 0.67 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:22:47 PM PDT 24
Peak memory 195472 kb
Host smart-2e6e7279-ef43-4eda-87cc-2449d9cc04dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778694651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.778694651
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2536097470
Short name T560
Test name
Test status
Simulation time 80507590 ps
CPU time 2.93 seconds
Started Jun 27 04:22:44 PM PDT 24
Finished Jun 27 04:22:50 PM PDT 24
Peak memory 198608 kb
Host smart-c0261869-c9c5-44a1-bfbd-fc7c487d904a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536097470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2536097470
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2659825948
Short name T281
Test name
Test status
Simulation time 228915731 ps
CPU time 1.3 seconds
Started Jun 27 04:22:44 PM PDT 24
Finished Jun 27 04:22:49 PM PDT 24
Peak memory 196732 kb
Host smart-6d0616e4-5a6f-4b41-945e-8bf1301976f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659825948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2659825948
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3569072877
Short name T11
Test name
Test status
Simulation time 101843614 ps
CPU time 1.06 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:44 PM PDT 24
Peak memory 196492 kb
Host smart-c9a812f8-2e3b-4de7-a7e5-219701bc23b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569072877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3569072877
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3653871035
Short name T230
Test name
Test status
Simulation time 131012276 ps
CPU time 1.08 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 196348 kb
Host smart-f2168925-546f-4f3a-bb66-52d7f25b7e06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653871035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3653871035
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4181314547
Short name T550
Test name
Test status
Simulation time 66038961 ps
CPU time 2.84 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:22:49 PM PDT 24
Peak memory 198544 kb
Host smart-cb2c14d8-58a2-48a8-b1c7-629cf7d56e0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181314547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4181314547
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3793773577
Short name T96
Test name
Test status
Simulation time 149071061 ps
CPU time 1.25 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:52 PM PDT 24
Peak memory 197400 kb
Host smart-07a8a9a8-21b0-47cb-89fb-410be4615f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793773577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3793773577
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2802443297
Short name T331
Test name
Test status
Simulation time 99243329 ps
CPU time 1.3 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:47 PM PDT 24
Peak memory 198424 kb
Host smart-99dad4a4-2ef9-4ab9-ac9f-5f68c3e9ad2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802443297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2802443297
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.4138602655
Short name T662
Test name
Test status
Simulation time 6697280373 ps
CPU time 28.28 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 198636 kb
Host smart-1eb40c38-a58a-4ae7-aea7-1d793fff0cea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138602655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.4138602655
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1758083614
Short name T171
Test name
Test status
Simulation time 191829337 ps
CPU time 0.57 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 194712 kb
Host smart-dd82b0bf-eded-4235-94f7-2f691cc9a4ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758083614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1758083614
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.632263237
Short name T561
Test name
Test status
Simulation time 134376186 ps
CPU time 0.8 seconds
Started Jun 27 04:22:43 PM PDT 24
Finished Jun 27 04:22:47 PM PDT 24
Peak memory 195888 kb
Host smart-6a3f1109-7e93-47fe-9ca2-a22b13be9bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632263237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.632263237
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.620809256
Short name T424
Test name
Test status
Simulation time 481751321 ps
CPU time 24.17 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:23:15 PM PDT 24
Peak memory 196900 kb
Host smart-0cce986d-c69d-4c06-a6e5-a5cec55ebcef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620809256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.620809256
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2003490697
Short name T685
Test name
Test status
Simulation time 322426998 ps
CPU time 1.06 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 198680 kb
Host smart-5aa9326e-548f-4eda-a3ab-dbc30169691d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003490697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2003490697
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2712804641
Short name T538
Test name
Test status
Simulation time 139651681 ps
CPU time 0.86 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:52 PM PDT 24
Peak memory 196776 kb
Host smart-66cc96a7-ba40-4179-a835-0fc12461ba20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712804641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2712804641
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.4022529030
Short name T262
Test name
Test status
Simulation time 51270287 ps
CPU time 2.02 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:47 PM PDT 24
Peak memory 198252 kb
Host smart-a44ae739-0eaa-44bf-b3ae-bfd097b52f97
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022529030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.4022529030
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2021508388
Short name T92
Test name
Test status
Simulation time 27950788 ps
CPU time 0.94 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 195200 kb
Host smart-975dc3ed-195f-48a7-ba80-5562336e1cf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021508388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2021508388
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4052756808
Short name T635
Test name
Test status
Simulation time 67674945 ps
CPU time 0.96 seconds
Started Jun 27 04:22:47 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 198004 kb
Host smart-cc827b4e-031b-48cc-ae9a-14b63dc0412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052756808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4052756808
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3553685915
Short name T472
Test name
Test status
Simulation time 146757785 ps
CPU time 1.34 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:52 PM PDT 24
Peak memory 196404 kb
Host smart-02fa6cbb-bd9a-4c2f-aada-0f5e3f3be76b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553685915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3553685915
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2639043068
Short name T126
Test name
Test status
Simulation time 341707374 ps
CPU time 5.58 seconds
Started Jun 27 04:22:44 PM PDT 24
Finished Jun 27 04:22:53 PM PDT 24
Peak memory 198584 kb
Host smart-84931c67-bf13-4471-b0a0-71ad442840be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639043068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2639043068
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3468184394
Short name T54
Test name
Test status
Simulation time 51443279 ps
CPU time 1.47 seconds
Started Jun 27 04:22:47 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 197692 kb
Host smart-182f11f2-d1fd-4f78-abab-367cb5cf88cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468184394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3468184394
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3400681898
Short name T55
Test name
Test status
Simulation time 262574626 ps
CPU time 1.24 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 198524 kb
Host smart-3717ad03-2bc9-45c4-918a-c00d6ad861be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400681898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3400681898
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3654050060
Short name T193
Test name
Test status
Simulation time 14079650089 ps
CPU time 150.8 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:25:15 PM PDT 24
Peak memory 198684 kb
Host smart-269034cd-496a-4686-b8fa-daae192479d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654050060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3654050060
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2410401132
Short name T25
Test name
Test status
Simulation time 76231429711 ps
CPU time 1495.23 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:47:45 PM PDT 24
Peak memory 199104 kb
Host smart-24431c4c-0d67-486c-9baf-3f5e38742000
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2410401132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2410401132
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2252952245
Short name T476
Test name
Test status
Simulation time 13159957 ps
CPU time 0.57 seconds
Started Jun 27 04:23:58 PM PDT 24
Finished Jun 27 04:24:05 PM PDT 24
Peak memory 194312 kb
Host smart-00b35fc1-6b9f-4ade-9d0c-85e7928fe929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252952245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2252952245
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3319387245
Short name T271
Test name
Test status
Simulation time 30113111 ps
CPU time 0.77 seconds
Started Jun 27 04:23:01 PM PDT 24
Finished Jun 27 04:23:04 PM PDT 24
Peak memory 196476 kb
Host smart-f1390df9-03c1-4f55-98cd-2595401425d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319387245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3319387245
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2722791068
Short name T274
Test name
Test status
Simulation time 231323565 ps
CPU time 6.3 seconds
Started Jun 27 04:23:59 PM PDT 24
Finished Jun 27 04:24:11 PM PDT 24
Peak memory 196992 kb
Host smart-3de78420-bbb1-4872-8dec-f4f2a7bedd99
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722791068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2722791068
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2923338104
Short name T187
Test name
Test status
Simulation time 253318855 ps
CPU time 0.75 seconds
Started Jun 27 04:22:57 PM PDT 24
Finished Jun 27 04:22:59 PM PDT 24
Peak memory 195696 kb
Host smart-5d53632b-c26f-4270-b974-8cc20cea16ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923338104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2923338104
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.4231059069
Short name T542
Test name
Test status
Simulation time 67602032 ps
CPU time 0.77 seconds
Started Jun 27 04:23:01 PM PDT 24
Finished Jun 27 04:23:04 PM PDT 24
Peak memory 195808 kb
Host smart-ff40ef3c-71cd-401e-8226-b4a483aa7a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231059069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.4231059069
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.29279307
Short name T352
Test name
Test status
Simulation time 21207172 ps
CPU time 0.99 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:22:58 PM PDT 24
Peak memory 197280 kb
Host smart-e73ab3e8-148d-4da7-9b69-970ab2e41d5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29279307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.gpio_intr_with_filter_rand_intr_event.29279307
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3642010867
Short name T320
Test name
Test status
Simulation time 110653559 ps
CPU time 2.42 seconds
Started Jun 27 04:23:01 PM PDT 24
Finished Jun 27 04:23:05 PM PDT 24
Peak memory 196336 kb
Host smart-bcff44f8-8d12-4cc1-a062-9b93df4e56db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642010867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3642010867
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1265598515
Short name T503
Test name
Test status
Simulation time 33961893 ps
CPU time 0.73 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:45 PM PDT 24
Peak memory 194936 kb
Host smart-4bb0e3ef-aa6f-453b-8d46-08fb05ac1dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265598515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1265598515
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3994869388
Short name T107
Test name
Test status
Simulation time 132333251 ps
CPU time 1.25 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:22:47 PM PDT 24
Peak memory 197604 kb
Host smart-f1972c3a-715d-4cd6-b134-986e7d47977f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994869388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3994869388
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2793419489
Short name T691
Test name
Test status
Simulation time 604792382 ps
CPU time 6.17 seconds
Started Jun 27 04:23:03 PM PDT 24
Finished Jun 27 04:23:11 PM PDT 24
Peak memory 198464 kb
Host smart-69b12200-c09a-4227-915a-cd3340b2824a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793419489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2793419489
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2422237530
Short name T269
Test name
Test status
Simulation time 62560439 ps
CPU time 1.16 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:22:52 PM PDT 24
Peak memory 196156 kb
Host smart-417daf78-97d7-42e1-b8bb-83e9880515ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422237530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2422237530
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3418815309
Short name T530
Test name
Test status
Simulation time 78248633 ps
CPU time 1.12 seconds
Started Jun 27 04:22:44 PM PDT 24
Finished Jun 27 04:22:49 PM PDT 24
Peak memory 196468 kb
Host smart-53f6faa6-e1e5-4f01-ba16-16786f7ac876
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418815309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3418815309
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.4245714399
Short name T294
Test name
Test status
Simulation time 44009254705 ps
CPU time 109.56 seconds
Started Jun 27 04:23:59 PM PDT 24
Finished Jun 27 04:25:55 PM PDT 24
Peak memory 198168 kb
Host smart-89ef8a67-30e8-4d49-b5b9-a04fe48b4c79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245714399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.4245714399
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.999158637
Short name T375
Test name
Test status
Simulation time 106993866878 ps
CPU time 440.89 seconds
Started Jun 27 04:23:59 PM PDT 24
Finished Jun 27 04:31:26 PM PDT 24
Peak memory 198468 kb
Host smart-0daa8597-6b61-49ac-909d-bbe721ef7403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=999158637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.999158637
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.169795191
Short name T445
Test name
Test status
Simulation time 22907811 ps
CPU time 0.55 seconds
Started Jun 27 04:23:59 PM PDT 24
Finished Jun 27 04:24:05 PM PDT 24
Peak memory 194128 kb
Host smart-d1f5eec2-0c7a-40df-bad0-5e3218aa26a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169795191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.169795191
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.855367065
Short name T112
Test name
Test status
Simulation time 60607006 ps
CPU time 0.66 seconds
Started Jun 27 04:23:58 PM PDT 24
Finished Jun 27 04:24:05 PM PDT 24
Peak memory 194904 kb
Host smart-dc47cc16-2a58-4b40-b3f3-b70d35c5510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855367065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.855367065
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3455071288
Short name T143
Test name
Test status
Simulation time 520526756 ps
CPU time 8.48 seconds
Started Jun 27 04:23:05 PM PDT 24
Finished Jun 27 04:23:16 PM PDT 24
Peak memory 198864 kb
Host smart-545ec05d-8e1c-4a57-8f6a-1e7ee0b8c46c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455071288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3455071288
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.167105963
Short name T335
Test name
Test status
Simulation time 167457264 ps
CPU time 1 seconds
Started Jun 27 04:22:55 PM PDT 24
Finished Jun 27 04:22:57 PM PDT 24
Peak memory 198432 kb
Host smart-95a73770-6985-46c2-9caf-80f160af44b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167105963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.167105963
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3969007600
Short name T125
Test name
Test status
Simulation time 23082466 ps
CPU time 0.73 seconds
Started Jun 27 04:23:57 PM PDT 24
Finished Jun 27 04:24:05 PM PDT 24
Peak memory 195664 kb
Host smart-85222ffe-8771-4f40-9341-82b5c11a3b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969007600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3969007600
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3813443368
Short name T221
Test name
Test status
Simulation time 100702969 ps
CPU time 2.96 seconds
Started Jun 27 04:23:52 PM PDT 24
Finished Jun 27 04:24:05 PM PDT 24
Peak memory 197760 kb
Host smart-fecfc1de-79b3-4f23-8ed4-79e111d80b3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813443368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3813443368
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2054499910
Short name T165
Test name
Test status
Simulation time 222458912 ps
CPU time 1.5 seconds
Started Jun 27 04:23:01 PM PDT 24
Finished Jun 27 04:23:04 PM PDT 24
Peak memory 196528 kb
Host smart-adaee36c-56b2-4379-a06d-a995a6c3236d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054499910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2054499910
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.186597543
Short name T711
Test name
Test status
Simulation time 44258462 ps
CPU time 0.67 seconds
Started Jun 27 04:23:00 PM PDT 24
Finished Jun 27 04:23:02 PM PDT 24
Peak memory 195856 kb
Host smart-65bd7878-42df-4b7e-95c7-eed3eef862c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186597543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.186597543
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3301861058
Short name T184
Test name
Test status
Simulation time 39370813 ps
CPU time 1.08 seconds
Started Jun 27 04:23:01 PM PDT 24
Finished Jun 27 04:23:04 PM PDT 24
Peak memory 196908 kb
Host smart-0e5d0c71-254d-46da-baf0-37c1fa8ba3a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301861058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3301861058
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.487169804
Short name T231
Test name
Test status
Simulation time 133929456 ps
CPU time 1.99 seconds
Started Jun 27 04:22:58 PM PDT 24
Finished Jun 27 04:23:01 PM PDT 24
Peak memory 198452 kb
Host smart-9cd755d3-756f-4f18-91a8-0b4a65dd818d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487169804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.487169804
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3769924325
Short name T337
Test name
Test status
Simulation time 107295097 ps
CPU time 0.78 seconds
Started Jun 27 04:23:59 PM PDT 24
Finished Jun 27 04:24:06 PM PDT 24
Peak memory 195484 kb
Host smart-42532fb4-b4cc-4198-a331-a3b53e158e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769924325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3769924325
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1406342058
Short name T607
Test name
Test status
Simulation time 150522298 ps
CPU time 1.26 seconds
Started Jun 27 04:23:03 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 198464 kb
Host smart-deb2c493-a59d-4ff4-8b28-ed1af240a869
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406342058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1406342058
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1624824735
Short name T590
Test name
Test status
Simulation time 8596379946 ps
CPU time 25.35 seconds
Started Jun 27 04:23:01 PM PDT 24
Finished Jun 27 04:23:28 PM PDT 24
Peak memory 198588 kb
Host smart-c18904c8-a082-48e4-997d-d7ad93dd763b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624824735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1624824735
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.23944843
Short name T463
Test name
Test status
Simulation time 55869065422 ps
CPU time 442.92 seconds
Started Jun 27 04:23:00 PM PDT 24
Finished Jun 27 04:30:25 PM PDT 24
Peak memory 198768 kb
Host smart-602bb0e6-97c8-4e2d-bb86-f45c7ecedcf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=23944843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.23944843
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1939683841
Short name T435
Test name
Test status
Simulation time 48902230 ps
CPU time 0.57 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 195428 kb
Host smart-f10533b0-1564-4bb5-911b-874fa008615c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939683841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1939683841
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3542092839
Short name T672
Test name
Test status
Simulation time 27743379 ps
CPU time 0.75 seconds
Started Jun 27 04:23:04 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 196036 kb
Host smart-e778c620-338d-44ca-a8b7-c25c4b41d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542092839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3542092839
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.278065886
Short name T418
Test name
Test status
Simulation time 490074266 ps
CPU time 5.41 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 196008 kb
Host smart-c5421031-e4eb-4ac2-8e1c-322948e7b3f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278065886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.278065886
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3560515267
Short name T487
Test name
Test status
Simulation time 79298682 ps
CPU time 1.02 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 198664 kb
Host smart-14285ca9-bf2a-47dc-aafa-9213ffb721b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560515267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3560515267
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.71280093
Short name T441
Test name
Test status
Simulation time 128689443 ps
CPU time 1.08 seconds
Started Jun 27 04:23:04 PM PDT 24
Finished Jun 27 04:23:08 PM PDT 24
Peak memory 197716 kb
Host smart-44bcb54f-e560-4341-9dd3-5b89b9534bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71280093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.71280093
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3568279020
Short name T667
Test name
Test status
Simulation time 198149434 ps
CPU time 2.06 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 197940 kb
Host smart-19818960-5ad0-45e9-8a18-20dcd4584483
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568279020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3568279020
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.409557399
Short name T22
Test name
Test status
Simulation time 213587790 ps
CPU time 1.02 seconds
Started Jun 27 04:23:59 PM PDT 24
Finished Jun 27 04:24:06 PM PDT 24
Peak memory 195596 kb
Host smart-70b53058-6c9a-4f34-b68b-1a10c8bd4884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409557399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
409557399
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2766659933
Short name T618
Test name
Test status
Simulation time 23341232 ps
CPU time 0.89 seconds
Started Jun 27 04:23:01 PM PDT 24
Finished Jun 27 04:23:04 PM PDT 24
Peak memory 196460 kb
Host smart-8f4b4c6e-ea17-4c3a-8c72-2dcc1bbaffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766659933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2766659933
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4152442625
Short name T180
Test name
Test status
Simulation time 176119718 ps
CPU time 0.73 seconds
Started Jun 27 04:22:57 PM PDT 24
Finished Jun 27 04:22:59 PM PDT 24
Peak memory 195900 kb
Host smart-c5ba5fc8-ce75-480d-89fe-e8ef0abfd099
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152442625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.4152442625
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3775833846
Short name T137
Test name
Test status
Simulation time 916760707 ps
CPU time 3.28 seconds
Started Jun 27 04:23:13 PM PDT 24
Finished Jun 27 04:23:21 PM PDT 24
Peak memory 198464 kb
Host smart-338c21f1-247e-4c4f-9bcd-43c38e0d976b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775833846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3775833846
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3772025116
Short name T651
Test name
Test status
Simulation time 85378475 ps
CPU time 1.3 seconds
Started Jun 27 04:23:05 PM PDT 24
Finished Jun 27 04:23:08 PM PDT 24
Peak memory 197272 kb
Host smart-59cad2a4-abe4-4db7-8e66-4075c98e218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772025116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3772025116
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1464440695
Short name T242
Test name
Test status
Simulation time 190418356 ps
CPU time 0.97 seconds
Started Jun 27 04:23:04 PM PDT 24
Finished Jun 27 04:23:08 PM PDT 24
Peak memory 196416 kb
Host smart-d67f2597-cda2-4680-bc81-08b42008d932
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464440695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1464440695
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3072433902
Short name T615
Test name
Test status
Simulation time 5267312984 ps
CPU time 28.98 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:24:00 PM PDT 24
Peak memory 199016 kb
Host smart-e3261bfb-3fd1-4df5-8cce-322133f0650c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072433902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3072433902
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3751964388
Short name T321
Test name
Test status
Simulation time 13910917 ps
CPU time 0.67 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 195060 kb
Host smart-bd3b053e-2232-44c0-8c2f-4e6d847b1f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751964388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3751964388
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2406987878
Short name T109
Test name
Test status
Simulation time 88552656 ps
CPU time 0.67 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 194116 kb
Host smart-45f16312-3cc8-4fe6-ba88-525c8dcb9b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406987878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2406987878
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1595665476
Short name T496
Test name
Test status
Simulation time 246435129 ps
CPU time 7.44 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:38 PM PDT 24
Peak memory 196432 kb
Host smart-5de368cb-3ca8-4d6b-81ba-c4008b95faaf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595665476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1595665476
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.670653760
Short name T467
Test name
Test status
Simulation time 36097683 ps
CPU time 0.67 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:23 PM PDT 24
Peak memory 195908 kb
Host smart-4ebc7064-b5dd-416c-a3e8-fa31bd09e9d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670653760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.670653760
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2403017323
Short name T306
Test name
Test status
Simulation time 89044824 ps
CPU time 1.1 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:23:30 PM PDT 24
Peak memory 197376 kb
Host smart-d53ec07e-20da-43e8-bf69-7bfc96072ff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403017323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2403017323
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3221100483
Short name T373
Test name
Test status
Simulation time 131995307 ps
CPU time 2.59 seconds
Started Jun 27 04:23:13 PM PDT 24
Finished Jun 27 04:23:20 PM PDT 24
Peak memory 198520 kb
Host smart-13fd71a7-7e3f-4bc1-99ff-29ecbb86fee7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221100483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3221100483
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2792254900
Short name T356
Test name
Test status
Simulation time 154130464 ps
CPU time 2.89 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:26 PM PDT 24
Peak memory 198492 kb
Host smart-cd6ccc9b-a73c-4128-8d7e-17c0d2146409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792254900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2792254900
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3103653746
Short name T620
Test name
Test status
Simulation time 22847073 ps
CPU time 0.77 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 195400 kb
Host smart-173f4728-e9bb-441d-9d40-3294fdae91b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103653746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3103653746
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.477545616
Short name T374
Test name
Test status
Simulation time 27515973 ps
CPU time 1.04 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:24 PM PDT 24
Peak memory 196748 kb
Host smart-5a01c16a-db87-409f-b23c-d1cf244185a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477545616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.477545616
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3529450821
Short name T629
Test name
Test status
Simulation time 314977793 ps
CPU time 3.48 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:33 PM PDT 24
Peak memory 198456 kb
Host smart-49950795-c20e-4e68-8317-f0d607dd61f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529450821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3529450821
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3429502749
Short name T557
Test name
Test status
Simulation time 58238655 ps
CPU time 0.82 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:31 PM PDT 24
Peak memory 196856 kb
Host smart-1803d54a-a471-47af-9b10-365cce2e62b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429502749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3429502749
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1870289692
Short name T163
Test name
Test status
Simulation time 598900363 ps
CPU time 0.87 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 196084 kb
Host smart-cc510989-6e3d-4d55-9029-f87887c416fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870289692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1870289692
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1229386472
Short name T600
Test name
Test status
Simulation time 1996958488 ps
CPU time 20.61 seconds
Started Jun 27 04:23:13 PM PDT 24
Finished Jun 27 04:23:38 PM PDT 24
Peak memory 198644 kb
Host smart-406b9df8-7c96-424b-8b66-5086845e0726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229386472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1229386472
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2376961637
Short name T616
Test name
Test status
Simulation time 75691453120 ps
CPU time 489.07 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:31:40 PM PDT 24
Peak memory 198808 kb
Host smart-c9609df6-54d7-4fe0-a757-23f447842a51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2376961637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2376961637
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3484008901
Short name T516
Test name
Test status
Simulation time 25212262 ps
CPU time 0.66 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:52 PM PDT 24
Peak memory 195196 kb
Host smart-533f8beb-0b63-49fe-ab96-57f66e147a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484008901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3484008901
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.71566143
Short name T422
Test name
Test status
Simulation time 28784914 ps
CPU time 1.01 seconds
Started Jun 27 04:23:40 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 197200 kb
Host smart-514cb6f5-0469-4e6b-af3c-1e452c43f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71566143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.71566143
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.117431432
Short name T152
Test name
Test status
Simulation time 3193879508 ps
CPU time 25.6 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:24:15 PM PDT 24
Peak memory 197172 kb
Host smart-839b1980-f2fd-4bca-93b7-0044744ef48a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117431432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.117431432
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3131309514
Short name T194
Test name
Test status
Simulation time 112362805 ps
CPU time 0.94 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 198228 kb
Host smart-9d735fec-118d-47f8-8ed6-b12fc91f1081
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131309514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3131309514
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2839100778
Short name T479
Test name
Test status
Simulation time 54584424 ps
CPU time 0.85 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:23:52 PM PDT 24
Peak memory 194864 kb
Host smart-61485c52-1908-4c92-8cd4-dff77fa08a14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839100778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2839100778
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3238935993
Short name T419
Test name
Test status
Simulation time 313206779 ps
CPU time 1.62 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:24:12 PM PDT 24
Peak memory 197344 kb
Host smart-2cff5b09-cc22-4eff-81f4-ce867fee97c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238935993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3238935993
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2206186262
Short name T240
Test name
Test status
Simulation time 482544574 ps
CPU time 2.06 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 197248 kb
Host smart-77cbc05c-7d29-4459-8367-43f1007f2a07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206186262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2206186262
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.973082348
Short name T256
Test name
Test status
Simulation time 157504742 ps
CPU time 1.07 seconds
Started Jun 27 04:23:20 PM PDT 24
Finished Jun 27 04:23:32 PM PDT 24
Peak memory 196480 kb
Host smart-4ed9bb5b-a519-499d-837b-7b03470173b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973082348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.973082348
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.414827586
Short name T531
Test name
Test status
Simulation time 147033802 ps
CPU time 1.13 seconds
Started Jun 27 04:23:37 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 196988 kb
Host smart-f3dadd7a-0c89-4dfb-8c53-92f0d2b5b3bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414827586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.414827586
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1196538978
Short name T19
Test name
Test status
Simulation time 148132658 ps
CPU time 2.11 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:51 PM PDT 24
Peak memory 198496 kb
Host smart-39525f7c-1def-479e-9c63-a91f7d93a319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196538978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1196538978
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2270518035
Short name T507
Test name
Test status
Simulation time 118445610 ps
CPU time 0.95 seconds
Started Jun 27 04:23:13 PM PDT 24
Finished Jun 27 04:23:18 PM PDT 24
Peak memory 196216 kb
Host smart-01378eab-1857-43f4-a3a3-023823e0e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270518035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2270518035
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4053994148
Short name T214
Test name
Test status
Simulation time 38814635 ps
CPU time 1 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:23 PM PDT 24
Peak memory 196752 kb
Host smart-e9fcf54c-c0fa-4bb2-bdae-98e7f7fc5e13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053994148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4053994148
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2521047029
Short name T8
Test name
Test status
Simulation time 21415499688 ps
CPU time 55.89 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:24:44 PM PDT 24
Peak memory 197856 kb
Host smart-76b7f0e5-af1d-4ab6-b7ed-a94e79002be5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521047029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2521047029
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.459093627
Short name T236
Test name
Test status
Simulation time 15354641 ps
CPU time 0.54 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 194208 kb
Host smart-7ba2a4f9-625d-496b-9563-cc460b63221a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459093627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.459093627
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2407115929
Short name T156
Test name
Test status
Simulation time 88136631 ps
CPU time 0.71 seconds
Started Jun 27 04:21:08 PM PDT 24
Finished Jun 27 04:21:09 PM PDT 24
Peak memory 194624 kb
Host smart-8ed8f4da-9176-4bd7-adc4-377fb13dcef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407115929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2407115929
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.690946301
Short name T169
Test name
Test status
Simulation time 1468795468 ps
CPU time 24.45 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:46 PM PDT 24
Peak memory 197424 kb
Host smart-497ec494-3d9c-43a8-8139-03f06bed3035
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690946301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.690946301
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.162002381
Short name T677
Test name
Test status
Simulation time 260728159 ps
CPU time 0.84 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:45 PM PDT 24
Peak memory 195984 kb
Host smart-b2f954c1-8223-4b24-8f33-0b6b6f543da8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162002381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.162002381
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2180333465
Short name T53
Test name
Test status
Simulation time 101258819 ps
CPU time 1.13 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:48 PM PDT 24
Peak memory 197076 kb
Host smart-83c1bfdd-6cd8-4f1c-ae26-29ebd6be334a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180333465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2180333465
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1129654274
Short name T255
Test name
Test status
Simulation time 91175061 ps
CPU time 3.23 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:37 PM PDT 24
Peak memory 196904 kb
Host smart-7ed4b9cf-0c80-4bf4-8677-12c6800494ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129654274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1129654274
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1269883762
Short name T400
Test name
Test status
Simulation time 41972630 ps
CPU time 1.1 seconds
Started Jun 27 04:20:30 PM PDT 24
Finished Jun 27 04:20:32 PM PDT 24
Peak memory 196616 kb
Host smart-5662bd7f-d324-4337-9093-8ac7d72c229c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269883762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1269883762
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.194996618
Short name T459
Test name
Test status
Simulation time 31753980 ps
CPU time 1.06 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:45 PM PDT 24
Peak memory 196972 kb
Host smart-0a6d12ac-a366-4777-8d06-8e25852a946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194996618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.194996618
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3465351819
Short name T188
Test name
Test status
Simulation time 117171621 ps
CPU time 0.91 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 196520 kb
Host smart-6e30ffa2-6aec-44ff-85e3-73aa5dcf8c48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465351819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3465351819
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.738890357
Short name T468
Test name
Test status
Simulation time 59156791 ps
CPU time 2.62 seconds
Started Jun 27 04:21:20 PM PDT 24
Finished Jun 27 04:21:24 PM PDT 24
Peak memory 198424 kb
Host smart-07f045f1-94e9-4d52-a6e1-764d6de51ef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738890357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.738890357
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.3058407968
Short name T136
Test name
Test status
Simulation time 324100805 ps
CPU time 1.05 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:46 PM PDT 24
Peak memory 195616 kb
Host smart-0b8f2d35-5181-4230-8a62-70c48bae859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058407968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3058407968
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3853620436
Short name T585
Test name
Test status
Simulation time 229117315 ps
CPU time 0.9 seconds
Started Jun 27 04:21:03 PM PDT 24
Finished Jun 27 04:21:05 PM PDT 24
Peak memory 196872 kb
Host smart-c8f01b1d-5d16-441e-b440-37e81e043e5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853620436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3853620436
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1311010924
Short name T420
Test name
Test status
Simulation time 32646269748 ps
CPU time 95.55 seconds
Started Jun 27 04:22:55 PM PDT 24
Finished Jun 27 04:24:31 PM PDT 24
Peak memory 198492 kb
Host smart-1ca5a840-f072-4e7a-b376-d4abe521c0a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311010924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1311010924
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.57526425
Short name T465
Test name
Test status
Simulation time 12532144 ps
CPU time 0.56 seconds
Started Jun 27 04:23:51 PM PDT 24
Finished Jun 27 04:24:03 PM PDT 24
Peak memory 194496 kb
Host smart-8794cb54-bb48-4ac0-9b72-6e8f6c29ecc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57526425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.57526425
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.843059368
Short name T248
Test name
Test status
Simulation time 503944673 ps
CPU time 0.77 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 196012 kb
Host smart-7b767573-5051-42f6-b683-c7d126fa1448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843059368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.843059368
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2222947204
Short name T510
Test name
Test status
Simulation time 134646980 ps
CPU time 6.27 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 197300 kb
Host smart-2e001e84-c628-4b2a-b1cc-2134f73cb6a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222947204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2222947204
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2661162599
Short name T372
Test name
Test status
Simulation time 75474571 ps
CPU time 0.96 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 197024 kb
Host smart-0a9598c0-0dfd-4f52-9085-724176d21263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661162599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2661162599
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.288639437
Short name T696
Test name
Test status
Simulation time 362528401 ps
CPU time 1.33 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:52 PM PDT 24
Peak memory 198584 kb
Host smart-325dacaa-471e-4c2f-9fde-8516e34c70b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288639437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.288639437
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4051648600
Short name T576
Test name
Test status
Simulation time 126434677 ps
CPU time 0.86 seconds
Started Jun 27 04:23:40 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 196112 kb
Host smart-23fd86d1-dda4-4ede-a0ab-a58e00a6532d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051648600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4051648600
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2261537849
Short name T385
Test name
Test status
Simulation time 399417014 ps
CPU time 2.93 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 196320 kb
Host smart-5e5ce755-fcbe-4bb8-8404-fab9b7f08db5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261537849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2261537849
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1744075395
Short name T517
Test name
Test status
Simulation time 58417420 ps
CPU time 0.98 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 196516 kb
Host smart-a03e8988-b21f-4983-bbf6-8db77d260173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744075395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1744075395
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1294462045
Short name T488
Test name
Test status
Simulation time 58820552 ps
CPU time 0.88 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 196556 kb
Host smart-f00b6781-81db-4c09-8366-139728dc7294
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294462045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1294462045
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.517759124
Short name T3
Test name
Test status
Simulation time 365324935 ps
CPU time 4.41 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 198828 kb
Host smart-994fc356-da2e-4038-83bf-e329b2d5b730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517759124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.517759124
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1676313257
Short name T581
Test name
Test status
Simulation time 408421199 ps
CPU time 1.24 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 196952 kb
Host smart-80a49e00-11e5-4908-bb2d-26cd5983cd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676313257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1676313257
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1359229188
Short name T183
Test name
Test status
Simulation time 59534608 ps
CPU time 1.08 seconds
Started Jun 27 04:23:37 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 197408 kb
Host smart-6516f07b-c4a1-45ef-9656-fe965922a537
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359229188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1359229188
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3867462036
Short name T213
Test name
Test status
Simulation time 3297088614 ps
CPU time 53.81 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:24:48 PM PDT 24
Peak memory 198568 kb
Host smart-c99e8329-3974-4c54-94fc-6afd95aa2225
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867462036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3867462036
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1384439900
Short name T526
Test name
Test status
Simulation time 180567935209 ps
CPU time 1594.44 seconds
Started Jun 27 04:23:47 PM PDT 24
Finished Jun 27 04:50:34 PM PDT 24
Peak memory 198736 kb
Host smart-48b6f1d6-00c5-4644-ae5a-c124d3b962b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1384439900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1384439900
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1565736419
Short name T443
Test name
Test status
Simulation time 47906594 ps
CPU time 0.57 seconds
Started Jun 27 04:23:51 PM PDT 24
Finished Jun 27 04:24:02 PM PDT 24
Peak memory 194512 kb
Host smart-cfd39a34-debf-4cfb-8eac-8cb1e302f25a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565736419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1565736419
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1925664960
Short name T350
Test name
Test status
Simulation time 51724788 ps
CPU time 0.77 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 195752 kb
Host smart-f01e3400-ced6-4b6f-a4f4-267d8917269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925664960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1925664960
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.991577082
Short name T402
Test name
Test status
Simulation time 64754958 ps
CPU time 3.42 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:54 PM PDT 24
Peak memory 196852 kb
Host smart-6a2743a1-fe90-4d70-aede-de378b7bab66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991577082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.991577082
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3957259528
Short name T428
Test name
Test status
Simulation time 965915946 ps
CPU time 0.97 seconds
Started Jun 27 04:23:40 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 197784 kb
Host smart-ea7ec333-9fb4-44ee-b61b-9ade3231af4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957259528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3957259528
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3751053912
Short name T540
Test name
Test status
Simulation time 67636271 ps
CPU time 0.93 seconds
Started Jun 27 04:23:41 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 196548 kb
Host smart-df01bfae-9104-4a03-b4d3-6a6e4ff562af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751053912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3751053912
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1639173606
Short name T220
Test name
Test status
Simulation time 195090237 ps
CPU time 2.41 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:23:52 PM PDT 24
Peak memory 198596 kb
Host smart-b31cf76e-f826-41ee-a99d-28ae9351ff91
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639173606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1639173606
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3946621063
Short name T617
Test name
Test status
Simulation time 210045527 ps
CPU time 1.13 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 196248 kb
Host smart-d607f28c-80b0-48c0-a2e8-899c2e47433c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946621063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3946621063
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.4007526015
Short name T417
Test name
Test status
Simulation time 100451932 ps
CPU time 0.96 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 196352 kb
Host smart-916c3e8c-01f8-4e35-92b1-63939f318bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007526015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.4007526015
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2677614563
Short name T140
Test name
Test status
Simulation time 35784651 ps
CPU time 0.7 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 194316 kb
Host smart-2ca4c03b-ace9-4a09-b90f-4ba48330bc22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677614563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2677614563
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3428228139
Short name T309
Test name
Test status
Simulation time 1012518656 ps
CPU time 4.09 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 198516 kb
Host smart-bc95bc0d-2c75-4759-893a-50102325d78d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428228139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3428228139
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.79896585
Short name T89
Test name
Test status
Simulation time 72985199 ps
CPU time 1.26 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 195932 kb
Host smart-aad35339-102c-40f2-a8e5-ae8a11ce0ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79896585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.79896585
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1153539730
Short name T681
Test name
Test status
Simulation time 80800142 ps
CPU time 1.43 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:02 PM PDT 24
Peak memory 197032 kb
Host smart-1e1cd28c-48cb-4d08-a68a-d32a7596bd9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153539730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1153539730
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3643692604
Short name T539
Test name
Test status
Simulation time 35338832546 ps
CPU time 121.7 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:25:52 PM PDT 24
Peak memory 198672 kb
Host smart-f526093b-a8a1-4d3a-a2b1-831c72e5770a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643692604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3643692604
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1976329784
Short name T447
Test name
Test status
Simulation time 235901499799 ps
CPU time 689.53 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:35:21 PM PDT 24
Peak memory 198808 kb
Host smart-3305cb44-b9c5-4bcd-991d-bed250976046
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1976329784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1976329784
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1707225760
Short name T513
Test name
Test status
Simulation time 63747451 ps
CPU time 0.54 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 195140 kb
Host smart-35712baa-fa86-46f9-a804-5687dc9fb4ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707225760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1707225760
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1122957225
Short name T343
Test name
Test status
Simulation time 17087485 ps
CPU time 0.68 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:52 PM PDT 24
Peak memory 194324 kb
Host smart-b0825ae9-52fd-49b1-90aa-244f45de33a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122957225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1122957225
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3339286297
Short name T501
Test name
Test status
Simulation time 393629043 ps
CPU time 20.65 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:24:12 PM PDT 24
Peak memory 197760 kb
Host smart-ba155dd4-5f50-4a2c-a071-fd39c59d2591
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339286297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3339286297
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.864349112
Short name T563
Test name
Test status
Simulation time 95263815 ps
CPU time 1.04 seconds
Started Jun 27 04:23:37 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 197008 kb
Host smart-8cd216a6-c1bc-4536-808c-a7fbba6f0ed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864349112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.864349112
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1396328539
Short name T610
Test name
Test status
Simulation time 311026128 ps
CPU time 0.92 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 197644 kb
Host smart-2813d149-e084-45e5-b48a-ebe797656d0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396328539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1396328539
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3551908555
Short name T708
Test name
Test status
Simulation time 102715411 ps
CPU time 1.36 seconds
Started Jun 27 04:23:44 PM PDT 24
Finished Jun 27 04:23:59 PM PDT 24
Peak memory 198524 kb
Host smart-2043018e-e7f5-4399-805f-0eee8a0f5fcd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551908555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3551908555
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.213319671
Short name T342
Test name
Test status
Simulation time 432977003 ps
CPU time 1.38 seconds
Started Jun 27 04:23:37 PM PDT 24
Finished Jun 27 04:23:54 PM PDT 24
Peak memory 196264 kb
Host smart-0478bb1a-4040-44d0-a65d-c8b623c65944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213319671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
213319671
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.889125542
Short name T497
Test name
Test status
Simulation time 17932366 ps
CPU time 0.75 seconds
Started Jun 27 04:23:37 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 195836 kb
Host smart-9238e8af-4268-444d-9a19-b44e516fb9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889125542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.889125542
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2215552725
Short name T312
Test name
Test status
Simulation time 71763584 ps
CPU time 0.71 seconds
Started Jun 27 04:23:37 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 196560 kb
Host smart-249b8ee6-59a2-4dac-b1b2-eb1afc97f2eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215552725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2215552725
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.30651863
Short name T267
Test name
Test status
Simulation time 47191593 ps
CPU time 2 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 198440 kb
Host smart-0931a4f1-554e-471c-9e7a-73e97221c9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand
om_long_reg_writes_reg_reads.30651863
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1572148126
Short name T570
Test name
Test status
Simulation time 233401937 ps
CPU time 1.09 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 196208 kb
Host smart-61df2b45-35aa-4fdf-b894-362135e2a429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572148126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1572148126
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.4108905435
Short name T175
Test name
Test status
Simulation time 44629846 ps
CPU time 0.87 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 196364 kb
Host smart-c8336f65-b4ba-4d21-8840-a3f09c1860ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108905435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.4108905435
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3208067006
Short name T514
Test name
Test status
Simulation time 6037368925 ps
CPU time 83.87 seconds
Started Jun 27 04:23:37 PM PDT 24
Finished Jun 27 04:25:16 PM PDT 24
Peak memory 199024 kb
Host smart-6dca5f6c-c0b1-4db0-8670-87407c01de1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208067006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3208067006
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3302404686
Short name T603
Test name
Test status
Simulation time 34579834 ps
CPU time 0.54 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 194396 kb
Host smart-24fdb56f-a92c-4ea8-8499-49ca8f3691e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302404686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3302404686
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3712922641
Short name T626
Test name
Test status
Simulation time 53202787 ps
CPU time 0.82 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 196484 kb
Host smart-d03fc2df-7c5a-44b5-b609-c2b559952daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712922641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3712922641
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.431800729
Short name T88
Test name
Test status
Simulation time 123249088 ps
CPU time 6.53 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:07 PM PDT 24
Peak memory 197392 kb
Host smart-608466ea-5ad6-44fd-b436-ffd08c8560b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431800729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.431800729
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2171772781
Short name T286
Test name
Test status
Simulation time 50130095 ps
CPU time 0.73 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 196244 kb
Host smart-a1dfa88d-20f1-4218-ab94-b6579b7c8dcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171772781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2171772781
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2885629622
Short name T160
Test name
Test status
Simulation time 534314917 ps
CPU time 1.08 seconds
Started Jun 27 04:23:49 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 196328 kb
Host smart-c113b9c7-9285-4b51-b82c-2494311272f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885629622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2885629622
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2295466859
Short name T259
Test name
Test status
Simulation time 321770411 ps
CPU time 3.47 seconds
Started Jun 27 04:23:51 PM PDT 24
Finished Jun 27 04:24:05 PM PDT 24
Peak memory 196840 kb
Host smart-7586d631-0361-4fe1-a86a-fb9e3d6cc828
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295466859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2295466859
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2332971651
Short name T423
Test name
Test status
Simulation time 199264917 ps
CPU time 1.46 seconds
Started Jun 27 04:23:51 PM PDT 24
Finished Jun 27 04:24:03 PM PDT 24
Peak memory 196380 kb
Host smart-d7a34dd6-6330-418a-8000-a7a8ae44a6f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332971651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2332971651
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1275981474
Short name T407
Test name
Test status
Simulation time 38722699 ps
CPU time 0.91 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 196512 kb
Host smart-bca1aec1-5751-4a78-bb74-306068457ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275981474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1275981474
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.478038952
Short name T653
Test name
Test status
Simulation time 137654126 ps
CPU time 0.71 seconds
Started Jun 27 04:23:47 PM PDT 24
Finished Jun 27 04:24:00 PM PDT 24
Peak memory 196672 kb
Host smart-3fd78aa1-7b6f-4ce5-98db-9432e7c53fd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478038952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.478038952
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3111709764
Short name T534
Test name
Test status
Simulation time 141010320 ps
CPU time 1.78 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:23:51 PM PDT 24
Peak memory 198132 kb
Host smart-540a4b88-7150-4116-9623-cbf0e52739ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111709764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3111709764
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.724870393
Short name T291
Test name
Test status
Simulation time 44000239 ps
CPU time 1.32 seconds
Started Jun 27 04:23:51 PM PDT 24
Finished Jun 27 04:24:03 PM PDT 24
Peak memory 196468 kb
Host smart-68b5f781-9fa9-44d1-b680-9f6d469365a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724870393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.724870393
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2466917269
Short name T398
Test name
Test status
Simulation time 49440992 ps
CPU time 1.3 seconds
Started Jun 27 04:23:49 PM PDT 24
Finished Jun 27 04:24:02 PM PDT 24
Peak memory 196076 kb
Host smart-cb5ae78f-179b-4b46-9541-5aa6dfe405c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466917269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2466917269
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3872833265
Short name T669
Test name
Test status
Simulation time 4407962130 ps
CPU time 55.71 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:56 PM PDT 24
Peak memory 198600 kb
Host smart-be1dbd83-a050-49f3-9b4f-9d752aeb007a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872833265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3872833265
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2436277067
Short name T46
Test name
Test status
Simulation time 143713462530 ps
CPU time 1725.27 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 198712 kb
Host smart-c465fd62-5234-4e09-b89a-7e5003bcc9c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2436277067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2436277067
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3682148930
Short name T322
Test name
Test status
Simulation time 19656933 ps
CPU time 0.61 seconds
Started Jun 27 04:24:00 PM PDT 24
Finished Jun 27 04:24:06 PM PDT 24
Peak memory 194572 kb
Host smart-5fb48d24-9267-4e44-aecc-bfe895fd43c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682148930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3682148930
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4108191187
Short name T218
Test name
Test status
Simulation time 73905982 ps
CPU time 0.66 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 195484 kb
Host smart-44ec0a7a-a711-42d1-8121-71e4653de56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108191187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4108191187
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.499114692
Short name T353
Test name
Test status
Simulation time 541931057 ps
CPU time 27.57 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:24:25 PM PDT 24
Peak memory 198408 kb
Host smart-fd787e6a-5fdd-44e4-b3f7-fdc783b73af4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499114692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.499114692
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.4219207188
Short name T471
Test name
Test status
Simulation time 194091267 ps
CPU time 0.83 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:15 PM PDT 24
Peak memory 196348 kb
Host smart-51ad31d1-72dd-42b1-b33c-040dd7414d1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219207188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.4219207188
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.408820270
Short name T110
Test name
Test status
Simulation time 218050685 ps
CPU time 1.49 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 197648 kb
Host smart-e02d65f1-dae0-4d53-888c-e11c85d8ed6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408820270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.408820270
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1681582534
Short name T379
Test name
Test status
Simulation time 292723090 ps
CPU time 2.49 seconds
Started Jun 27 04:23:43 PM PDT 24
Finished Jun 27 04:24:00 PM PDT 24
Peak memory 198292 kb
Host smart-f2c44db8-6e30-4b7e-b1ed-8d1943b349a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681582534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1681582534
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3275712468
Short name T393
Test name
Test status
Simulation time 345310840 ps
CPU time 1.89 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 197160 kb
Host smart-9cbaee69-77b3-467f-aed4-9caff3fa5c7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275712468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3275712468
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1768894070
Short name T329
Test name
Test status
Simulation time 49356216 ps
CPU time 1.03 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 196000 kb
Host smart-8cece4ee-a15d-4e66-8428-ea8fc2efab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768894070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1768894070
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3884826722
Short name T505
Test name
Test status
Simulation time 17597945 ps
CPU time 0.6 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:23:57 PM PDT 24
Peak memory 194640 kb
Host smart-8e9957f1-a4b0-4ef7-bc3d-8bdde9cbef4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884826722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3884826722
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3530253350
Short name T433
Test name
Test status
Simulation time 1684958452 ps
CPU time 1.54 seconds
Started Jun 27 04:24:44 PM PDT 24
Finished Jun 27 04:24:47 PM PDT 24
Peak memory 198464 kb
Host smart-2ba39314-0a5b-4e48-81ce-7eeab3510006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530253350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3530253350
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.888920456
Short name T326
Test name
Test status
Simulation time 228730562 ps
CPU time 1.21 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 196748 kb
Host smart-edfafd21-8dac-453a-b3dd-8b9c857f5e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888920456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.888920456
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.775787391
Short name T172
Test name
Test status
Simulation time 67822783 ps
CPU time 0.72 seconds
Started Jun 27 04:23:47 PM PDT 24
Finished Jun 27 04:24:00 PM PDT 24
Peak memory 195532 kb
Host smart-f3596fbb-b318-4d1b-8a39-5e9494401b0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775787391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.775787391
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2969073507
Short name T23
Test name
Test status
Simulation time 8037673466 ps
CPU time 95.56 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:25:56 PM PDT 24
Peak memory 198564 kb
Host smart-1c5f7ca9-ecd5-43fd-a177-5efcc43bba05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969073507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2969073507
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3316566373
Short name T698
Test name
Test status
Simulation time 69578795199 ps
CPU time 647.74 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:34:59 PM PDT 24
Peak memory 198688 kb
Host smart-a34ce4b7-8c55-43aa-81f2-f54ed214e4c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3316566373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3316566373
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.488464210
Short name T710
Test name
Test status
Simulation time 17328434 ps
CPU time 0.59 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:20 PM PDT 24
Peak memory 195360 kb
Host smart-be4b82f9-722a-4d33-be28-a37274f988b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488464210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.488464210
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3636557468
Short name T31
Test name
Test status
Simulation time 128650978 ps
CPU time 0.9 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 197176 kb
Host smart-2e3147a6-40da-4384-9784-91dddf1f52d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636557468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3636557468
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4097782747
Short name T690
Test name
Test status
Simulation time 136826410 ps
CPU time 7.05 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 196024 kb
Host smart-8a04a6df-36bc-4a81-93a7-92391fda4700
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097782747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4097782747
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.679729274
Short name T409
Test name
Test status
Simulation time 128019808 ps
CPU time 0.84 seconds
Started Jun 27 04:24:08 PM PDT 24
Finished Jun 27 04:24:10 PM PDT 24
Peak memory 196416 kb
Host smart-03b45843-1108-4caa-8d9d-170f00368b34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679729274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.679729274
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.4008057732
Short name T544
Test name
Test status
Simulation time 49736806 ps
CPU time 1.23 seconds
Started Jun 27 04:24:51 PM PDT 24
Finished Jun 27 04:24:53 PM PDT 24
Peak memory 198544 kb
Host smart-8453549c-42b2-4060-bb6c-419a4881d912
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008057732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.4008057732
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2982636109
Short name T706
Test name
Test status
Simulation time 283696306 ps
CPU time 2.07 seconds
Started Jun 27 04:24:03 PM PDT 24
Finished Jun 27 04:24:08 PM PDT 24
Peak memory 198532 kb
Host smart-6586fbfb-720c-4db9-aeca-b42e0783ea72
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982636109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2982636109
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1513032683
Short name T399
Test name
Test status
Simulation time 94833188 ps
CPU time 2.89 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 198560 kb
Host smart-7bc6065e-4950-44c1-bb80-23a3772c497a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513032683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1513032683
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2687146364
Short name T412
Test name
Test status
Simulation time 25428426 ps
CPU time 0.84 seconds
Started Jun 27 04:24:07 PM PDT 24
Finished Jun 27 04:24:09 PM PDT 24
Peak memory 196456 kb
Host smart-e9084b76-d239-41f1-82f3-6ea1fed6381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687146364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2687146364
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2359976469
Short name T376
Test name
Test status
Simulation time 56676312 ps
CPU time 1.09 seconds
Started Jun 27 04:24:00 PM PDT 24
Finished Jun 27 04:24:06 PM PDT 24
Peak memory 196264 kb
Host smart-f13f18ad-0395-4e69-926c-403eef68baef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359976469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2359976469
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3349364800
Short name T521
Test name
Test status
Simulation time 1149368989 ps
CPU time 3.54 seconds
Started Jun 27 04:24:07 PM PDT 24
Finished Jun 27 04:24:11 PM PDT 24
Peak memory 198492 kb
Host smart-7feb4d3a-c539-4bec-bffb-b12e369e2849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349364800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3349364800
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3442608288
Short name T671
Test name
Test status
Simulation time 195932230 ps
CPU time 0.92 seconds
Started Jun 27 04:24:04 PM PDT 24
Finished Jun 27 04:24:07 PM PDT 24
Peak memory 196208 kb
Host smart-6f7b2d13-f004-4633-8c99-96ffeb42c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442608288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3442608288
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3869317978
Short name T181
Test name
Test status
Simulation time 81676667 ps
CPU time 1.01 seconds
Started Jun 27 04:24:01 PM PDT 24
Finished Jun 27 04:24:07 PM PDT 24
Peak memory 196960 kb
Host smart-dc61fabb-ab68-43b4-a000-ca8e6438121d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869317978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3869317978
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1961506526
Short name T302
Test name
Test status
Simulation time 11010167559 ps
CPU time 155.3 seconds
Started Jun 27 04:24:05 PM PDT 24
Finished Jun 27 04:26:42 PM PDT 24
Peak memory 199052 kb
Host smart-a7e3185a-279f-4ceb-9fc4-a52f44f7495b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961506526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1961506526
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3671324760
Short name T566
Test name
Test status
Simulation time 49466396 ps
CPU time 0.56 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:24:12 PM PDT 24
Peak memory 195112 kb
Host smart-b510dd24-8f41-449b-ac52-79c40be4d64b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671324760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3671324760
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3769613931
Short name T190
Test name
Test status
Simulation time 33671088 ps
CPU time 0.87 seconds
Started Jun 27 04:24:04 PM PDT 24
Finished Jun 27 04:24:07 PM PDT 24
Peak memory 196396 kb
Host smart-c366ccc5-91d4-4cd4-b151-26fed4468817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769613931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3769613931
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2775918997
Short name T483
Test name
Test status
Simulation time 3231589580 ps
CPU time 13.96 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:29 PM PDT 24
Peak memory 197204 kb
Host smart-de0dbab1-32f9-4ad3-8e22-6e299dad2328
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775918997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2775918997
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.758547176
Short name T567
Test name
Test status
Simulation time 37782411 ps
CPU time 0.76 seconds
Started Jun 27 04:24:05 PM PDT 24
Finished Jun 27 04:24:08 PM PDT 24
Peak memory 196360 kb
Host smart-88b11870-a0c9-49a0-ae45-60c0710169a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758547176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.758547176
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3231546631
Short name T15
Test name
Test status
Simulation time 103095349 ps
CPU time 0.92 seconds
Started Jun 27 04:24:09 PM PDT 24
Finished Jun 27 04:24:11 PM PDT 24
Peak memory 196604 kb
Host smart-35f251b8-8ec0-4b47-a533-8f840240c81f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231546631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3231546631
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4064328156
Short name T357
Test name
Test status
Simulation time 41856465 ps
CPU time 1.71 seconds
Started Jun 27 04:24:01 PM PDT 24
Finished Jun 27 04:24:07 PM PDT 24
Peak memory 197656 kb
Host smart-0192de88-2b80-4afa-8125-20217f2bd1e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064328156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4064328156
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2611140240
Short name T627
Test name
Test status
Simulation time 134918497 ps
CPU time 1.51 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:22 PM PDT 24
Peak memory 196548 kb
Host smart-7b7ebf4b-a2ee-483e-8c0c-1af695aca04b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611140240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2611140240
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2283213607
Short name T664
Test name
Test status
Simulation time 137331868 ps
CPU time 1.21 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:17 PM PDT 24
Peak memory 197528 kb
Host smart-401cfcde-5999-4007-b84c-99844daf75c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283213607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2283213607
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1892364432
Short name T12
Test name
Test status
Simulation time 44327180 ps
CPU time 1.03 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:16 PM PDT 24
Peak memory 197112 kb
Host smart-59932128-b668-4f69-aaf1-efe6586a6bbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892364432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1892364432
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3754009186
Short name T108
Test name
Test status
Simulation time 1396455373 ps
CPU time 5.77 seconds
Started Jun 27 04:24:09 PM PDT 24
Finished Jun 27 04:24:15 PM PDT 24
Peak memory 198472 kb
Host smart-4215b013-1f91-48c8-989a-76e45331de77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754009186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3754009186
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1802944726
Short name T166
Test name
Test status
Simulation time 192461229 ps
CPU time 1.31 seconds
Started Jun 27 04:24:11 PM PDT 24
Finished Jun 27 04:24:15 PM PDT 24
Peak memory 198540 kb
Host smart-7884295a-7c3e-4c85-9ac7-72b4e860543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802944726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1802944726
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.337364158
Short name T579
Test name
Test status
Simulation time 38586524 ps
CPU time 0.85 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 195608 kb
Host smart-4d99d8db-c490-43bb-bff1-7724011479a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337364158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.337364158
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3643848439
Short name T2
Test name
Test status
Simulation time 8233373997 ps
CPU time 87.24 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:25:38 PM PDT 24
Peak memory 198692 kb
Host smart-db0d7dec-0de0-4a29-9ce2-8b1aa689a24c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643848439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3643848439
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1211272952
Short name T358
Test name
Test status
Simulation time 35531297 ps
CPU time 0.57 seconds
Started Jun 27 04:24:03 PM PDT 24
Finished Jun 27 04:24:07 PM PDT 24
Peak memory 194416 kb
Host smart-e12255aa-f7ef-4090-bf9b-3c6220829dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211272952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1211272952
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1018032601
Short name T646
Test name
Test status
Simulation time 49427711 ps
CPU time 0.75 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:15 PM PDT 24
Peak memory 195724 kb
Host smart-2ac1d222-7f55-4427-bc46-bb3ca5fdef4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018032601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1018032601
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.768259041
Short name T623
Test name
Test status
Simulation time 1920552468 ps
CPU time 18.05 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:24:42 PM PDT 24
Peak memory 195984 kb
Host smart-3fae05ab-5ae1-4cfd-9f61-8f3174bf8cdc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768259041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.768259041
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3055146013
Short name T574
Test name
Test status
Simulation time 29644190 ps
CPU time 0.65 seconds
Started Jun 27 04:24:04 PM PDT 24
Finished Jun 27 04:24:07 PM PDT 24
Peak memory 195072 kb
Host smart-89a22d8f-55b6-4f2f-b7e0-8d2ce2c48fed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055146013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3055146013
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2237634924
Short name T389
Test name
Test status
Simulation time 36399181 ps
CPU time 0.86 seconds
Started Jun 27 04:24:11 PM PDT 24
Finished Jun 27 04:24:14 PM PDT 24
Peak memory 196420 kb
Host smart-6ef1afd2-8932-48d7-95ae-18e36e385b5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237634924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2237634924
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2850371205
Short name T499
Test name
Test status
Simulation time 129491888 ps
CPU time 1.24 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:16 PM PDT 24
Peak memory 197628 kb
Host smart-c3e2bb0c-49c6-4b1a-81e1-01424d72e300
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850371205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2850371205
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2586993703
Short name T196
Test name
Test status
Simulation time 246377475 ps
CPU time 2.58 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:24:27 PM PDT 24
Peak memory 196316 kb
Host smart-57ac8cdd-8983-44ed-aa40-9f4ffdd358c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586993703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2586993703
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.760402070
Short name T282
Test name
Test status
Simulation time 105999664 ps
CPU time 1.26 seconds
Started Jun 27 04:24:16 PM PDT 24
Finished Jun 27 04:24:24 PM PDT 24
Peak memory 197580 kb
Host smart-3e02d6ab-645f-4fa3-b80e-7af8b86a6470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760402070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.760402070
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1163957826
Short name T541
Test name
Test status
Simulation time 101099037 ps
CPU time 0.93 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:24:25 PM PDT 24
Peak memory 197092 kb
Host smart-2f472ff6-f36c-41a9-b8dc-228d1419ce72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163957826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1163957826
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.4243346316
Short name T293
Test name
Test status
Simulation time 216809615 ps
CPU time 2.69 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 198416 kb
Host smart-dbf75bbd-caf9-46ee-86fb-4356eddc3039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243346316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.4243346316
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2686311186
Short name T673
Test name
Test status
Simulation time 202294208 ps
CPU time 1.25 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:15 PM PDT 24
Peak memory 197248 kb
Host smart-e7c35398-b587-4de1-9c7a-38c9f080eb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686311186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2686311186
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1272809559
Short name T217
Test name
Test status
Simulation time 48096714 ps
CPU time 0.78 seconds
Started Jun 27 04:24:11 PM PDT 24
Finished Jun 27 04:24:14 PM PDT 24
Peak memory 195808 kb
Host smart-86c800a9-39f6-4f0f-9999-db5e29106822
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272809559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1272809559
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3029252991
Short name T661
Test name
Test status
Simulation time 2752398242 ps
CPU time 32.32 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:24:44 PM PDT 24
Peak memory 198456 kb
Host smart-3a22c2af-be63-4d62-8896-eb875c034d3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029252991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3029252991
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3652801913
Short name T157
Test name
Test status
Simulation time 20239181 ps
CPU time 0.56 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:20 PM PDT 24
Peak memory 194424 kb
Host smart-437d5ee7-29ae-45be-b0a4-f056abbbc9a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652801913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3652801913
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4168066102
Short name T595
Test name
Test status
Simulation time 47973167 ps
CPU time 0.69 seconds
Started Jun 27 04:24:44 PM PDT 24
Finished Jun 27 04:24:46 PM PDT 24
Peak memory 195348 kb
Host smart-1679a495-3936-4d92-8303-8b4ce62c7c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168066102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4168066102
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.178927732
Short name T608
Test name
Test status
Simulation time 622094827 ps
CPU time 17.27 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:40 PM PDT 24
Peak memory 198488 kb
Host smart-f0c1adbd-47cc-4a23-95de-1a0371509576
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178927732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.178927732
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.822696764
Short name T606
Test name
Test status
Simulation time 29794374 ps
CPU time 0.65 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:15 PM PDT 24
Peak memory 194736 kb
Host smart-d28fbd42-4f90-4abb-9dd5-35b58a248312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822696764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.822696764
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1649810571
Short name T522
Test name
Test status
Simulation time 80594299 ps
CPU time 0.76 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:24:25 PM PDT 24
Peak memory 196344 kb
Host smart-b84cf6f5-913e-46a8-a7ef-c93effc4cba6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649810571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1649810571
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3966541874
Short name T670
Test name
Test status
Simulation time 44176435 ps
CPU time 1.76 seconds
Started Jun 27 04:24:08 PM PDT 24
Finished Jun 27 04:24:11 PM PDT 24
Peak memory 198596 kb
Host smart-073d60dc-5958-4ac1-bde9-ad5f100c107b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966541874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3966541874
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1513663220
Short name T604
Test name
Test status
Simulation time 114785405 ps
CPU time 2.26 seconds
Started Jun 27 04:24:49 PM PDT 24
Finished Jun 27 04:24:52 PM PDT 24
Peak memory 197620 kb
Host smart-bb2118f8-29ec-4937-b0ea-ebc42cf1717b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513663220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1513663220
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2223711740
Short name T305
Test name
Test status
Simulation time 749680491 ps
CPU time 0.9 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:24:12 PM PDT 24
Peak memory 196204 kb
Host smart-cdac3300-ad95-4728-9f0c-7fd6491c808f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223711740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2223711740
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1077166799
Short name T657
Test name
Test status
Simulation time 66725811 ps
CPU time 0.76 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:24:13 PM PDT 24
Peak memory 196644 kb
Host smart-169526da-238f-4cff-b7c0-f73306551ad2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077166799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1077166799
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1734469041
Short name T450
Test name
Test status
Simulation time 174907434 ps
CPU time 1.71 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 198232 kb
Host smart-e46c5825-0a53-48c8-9791-dfd7ad9d750a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734469041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1734469041
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.227061298
Short name T425
Test name
Test status
Simulation time 61256044 ps
CPU time 1.1 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:17 PM PDT 24
Peak memory 196280 kb
Host smart-db5e6760-d4d1-4030-a5b7-cba90e85c8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227061298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.227061298
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2756538989
Short name T508
Test name
Test status
Simulation time 117470635 ps
CPU time 0.93 seconds
Started Jun 27 04:24:11 PM PDT 24
Finished Jun 27 04:24:14 PM PDT 24
Peak memory 196288 kb
Host smart-ca2892ad-7c50-46fb-bc08-de6b5dd5855c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756538989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2756538989
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.4203612977
Short name T266
Test name
Test status
Simulation time 896776475 ps
CPU time 23.59 seconds
Started Jun 27 04:24:02 PM PDT 24
Finished Jun 27 04:24:29 PM PDT 24
Peak memory 198420 kb
Host smart-6c15018f-39db-49ce-bda6-5fb123dcb35c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203612977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.4203612977
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2289928765
Short name T683
Test name
Test status
Simulation time 44150895 ps
CPU time 0.56 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:17 PM PDT 24
Peak memory 194484 kb
Host smart-2fdd2bc5-32fc-43a5-b47a-e91ea8eb1f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289928765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2289928765
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1516649118
Short name T558
Test name
Test status
Simulation time 93159313 ps
CPU time 0.83 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:16 PM PDT 24
Peak memory 195636 kb
Host smart-2ce40657-a5dc-417a-8ce1-ff77726ed3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516649118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1516649118
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.532695081
Short name T345
Test name
Test status
Simulation time 390753889 ps
CPU time 13.86 seconds
Started Jun 27 04:24:11 PM PDT 24
Finished Jun 27 04:24:27 PM PDT 24
Peak memory 197372 kb
Host smart-259be518-917a-451b-ad2b-6629009e7b11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532695081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.532695081
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1155975538
Short name T686
Test name
Test status
Simulation time 75012720 ps
CPU time 0.99 seconds
Started Jun 27 04:24:04 PM PDT 24
Finished Jun 27 04:24:08 PM PDT 24
Peak memory 197708 kb
Host smart-ec9d8fa3-66ec-4e08-9848-73883380bed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155975538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1155975538
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.24513583
Short name T295
Test name
Test status
Simulation time 292862950 ps
CPU time 1.19 seconds
Started Jun 27 04:24:04 PM PDT 24
Finished Jun 27 04:24:08 PM PDT 24
Peak memory 197320 kb
Host smart-a9d773dd-944d-4886-9059-92dc792c0f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.24513583
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1743124219
Short name T52
Test name
Test status
Simulation time 54745193 ps
CPU time 2.07 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 198400 kb
Host smart-04734cd5-73ea-4260-83b8-231b3d1452a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743124219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1743124219
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.155191250
Short name T158
Test name
Test status
Simulation time 166242506 ps
CPU time 1.83 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:24 PM PDT 24
Peak memory 197048 kb
Host smart-91c0da07-70fb-4b94-87eb-f18a3cab85f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155191250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
155191250
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4002657609
Short name T327
Test name
Test status
Simulation time 92392255 ps
CPU time 0.93 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:20 PM PDT 24
Peak memory 196244 kb
Host smart-417bcb36-2373-4f84-8f62-d455c51032e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002657609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4002657609
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.132285253
Short name T243
Test name
Test status
Simulation time 231849216 ps
CPU time 1.04 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:24:13 PM PDT 24
Peak memory 196268 kb
Host smart-f1f3daa6-81e1-4553-b674-04368986668c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132285253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.132285253
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2465375582
Short name T621
Test name
Test status
Simulation time 176053974 ps
CPU time 2.13 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:22 PM PDT 24
Peak memory 198428 kb
Host smart-060a1338-cc71-488f-b792-ed2dd132d6e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465375582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2465375582
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.882791058
Short name T391
Test name
Test status
Simulation time 32586571 ps
CPU time 0.88 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:20 PM PDT 24
Peak memory 196496 kb
Host smart-785d479a-db1d-4bf6-9a28-6d55aed3f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882791058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.882791058
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1297173478
Short name T139
Test name
Test status
Simulation time 51634590 ps
CPU time 0.88 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 195948 kb
Host smart-4b1b337c-b77f-4d16-857b-1906d753860c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297173478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1297173478
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2680158218
Short name T602
Test name
Test status
Simulation time 42557395980 ps
CPU time 92.57 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:25:48 PM PDT 24
Peak memory 198568 kb
Host smart-1d7c9c76-be78-4bfa-b6f7-352a9aecf714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680158218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2680158218
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.616340507
Short name T637
Test name
Test status
Simulation time 365767198386 ps
CPU time 1731.19 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:53:10 PM PDT 24
Peak memory 198648 kb
Host smart-bbb3defa-4d25-497b-9fce-79c6dc14444e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=616340507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.616340507
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2303593228
Short name T461
Test name
Test status
Simulation time 15640720 ps
CPU time 0.58 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:34 PM PDT 24
Peak memory 194656 kb
Host smart-72e5c314-27d4-42db-bea1-c0cb81976472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303593228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2303593228
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1247185704
Short name T258
Test name
Test status
Simulation time 132148388 ps
CPU time 0.77 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 194104 kb
Host smart-7a8741d8-3ba2-40e4-9603-20eddf18fdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247185704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1247185704
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2065294360
Short name T492
Test name
Test status
Simulation time 686000530 ps
CPU time 15.9 seconds
Started Jun 27 04:23:40 PM PDT 24
Finished Jun 27 04:24:11 PM PDT 24
Peak memory 198252 kb
Host smart-705aab3b-bcde-4e24-8fbb-73686b7b88c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065294360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2065294360
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3962264979
Short name T319
Test name
Test status
Simulation time 19488899 ps
CPU time 0.59 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:35 PM PDT 24
Peak memory 195048 kb
Host smart-14268df2-2257-4121-9158-a6d359ed918d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962264979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3962264979
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3977380039
Short name T124
Test name
Test status
Simulation time 85308561 ps
CPU time 1.38 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:45 PM PDT 24
Peak memory 194856 kb
Host smart-4f0edf9f-14af-42d5-b93a-dc3715ba798f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977380039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3977380039
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.536307900
Short name T377
Test name
Test status
Simulation time 111261827 ps
CPU time 2.09 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 196960 kb
Host smart-655f816d-ef62-4811-8e1a-e8e5ffd5b90e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536307900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.536307900
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1413091936
Short name T370
Test name
Test status
Simulation time 172661108 ps
CPU time 3.11 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:47 PM PDT 24
Peak memory 196636 kb
Host smart-b4790030-90bc-4903-be3d-f83f599a3838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413091936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1413091936
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1463143922
Short name T486
Test name
Test status
Simulation time 347736347 ps
CPU time 1.06 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 195360 kb
Host smart-7d537f8e-3ac5-4bf6-94da-8ae222f9c9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463143922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1463143922
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3384488010
Short name T506
Test name
Test status
Simulation time 128346105 ps
CPU time 1.34 seconds
Started Jun 27 04:21:18 PM PDT 24
Finished Jun 27 04:21:20 PM PDT 24
Peak memory 198664 kb
Host smart-e03cad08-820a-46d3-b216-554acef43ea2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384488010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3384488010
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2371274440
Short name T265
Test name
Test status
Simulation time 162438742 ps
CPU time 2.82 seconds
Started Jun 27 04:21:43 PM PDT 24
Finished Jun 27 04:21:47 PM PDT 24
Peak memory 198540 kb
Host smart-a37e7003-373a-46d1-b0ed-963d469a377c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371274440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2371274440
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3196979872
Short name T33
Test name
Test status
Simulation time 636265957 ps
CPU time 0.91 seconds
Started Jun 27 04:21:41 PM PDT 24
Finished Jun 27 04:21:43 PM PDT 24
Peak memory 214040 kb
Host smart-da636e23-1078-4956-86d5-32b3a0f5bd73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196979872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3196979872
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2060199709
Short name T111
Test name
Test status
Simulation time 297205773 ps
CPU time 1.25 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:25 PM PDT 24
Peak memory 197112 kb
Host smart-b0b79dc8-f9d4-49b8-b2bd-c642f01fdfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060199709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2060199709
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1281433837
Short name T250
Test name
Test status
Simulation time 133960844 ps
CPU time 1.1 seconds
Started Jun 27 04:21:08 PM PDT 24
Finished Jun 27 04:21:10 PM PDT 24
Peak memory 196244 kb
Host smart-ee8a15d9-d1ab-4107-ada6-2ab9b8ad7c43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281433837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1281433837
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.4209887046
Short name T132
Test name
Test status
Simulation time 4086832208 ps
CPU time 106.49 seconds
Started Jun 27 04:21:31 PM PDT 24
Finished Jun 27 04:23:18 PM PDT 24
Peak memory 198752 kb
Host smart-528a103e-801e-455c-b8f1-6faa2a3b39a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209887046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.4209887046
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2972138252
Short name T709
Test name
Test status
Simulation time 44594378 ps
CPU time 0.56 seconds
Started Jun 27 04:24:19 PM PDT 24
Finished Jun 27 04:24:27 PM PDT 24
Peak memory 195152 kb
Host smart-c0caf9df-d973-4e99-a47d-331fb68c7754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972138252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2972138252
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.4113642873
Short name T466
Test name
Test status
Simulation time 62588301 ps
CPU time 0.65 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 194624 kb
Host smart-d42ce928-3175-454d-bb84-070b0f6fc26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113642873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.4113642873
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3378196875
Short name T693
Test name
Test status
Simulation time 12707495799 ps
CPU time 28.14 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:50 PM PDT 24
Peak memory 197076 kb
Host smart-11d06431-6a4c-4f02-beca-09cdf2769dea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378196875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3378196875
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2918953841
Short name T649
Test name
Test status
Simulation time 61382152 ps
CPU time 0.75 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 196292 kb
Host smart-a6205d01-8def-4469-88e9-508722000221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918953841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2918953841
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3441534995
Short name T663
Test name
Test status
Simulation time 35050372 ps
CPU time 0.97 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 196512 kb
Host smart-309127bd-78aa-49e9-a1c2-4e7e57d2f3cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441534995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3441534995
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3741520799
Short name T536
Test name
Test status
Simulation time 266760089 ps
CPU time 2.67 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:22 PM PDT 24
Peak memory 198576 kb
Host smart-06c00e5b-350f-4ff6-959a-0ccf2320ee43
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741520799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3741520799
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2428399474
Short name T237
Test name
Test status
Simulation time 198083298 ps
CPU time 1.32 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 196284 kb
Host smart-b5d410a0-87ca-43d5-b032-c11b31e5df6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428399474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2428399474
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1142234493
Short name T500
Test name
Test status
Simulation time 73180478 ps
CPU time 1.18 seconds
Started Jun 27 04:24:11 PM PDT 24
Finished Jun 27 04:24:14 PM PDT 24
Peak memory 197476 kb
Host smart-8151bf09-41ca-4476-ac25-8bda3b41cdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142234493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1142234493
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1322855019
Short name T189
Test name
Test status
Simulation time 29178084 ps
CPU time 0.8 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 197064 kb
Host smart-dbcb4884-c191-4726-8b5d-a6fab10667de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322855019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1322855019
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3226131175
Short name T7
Test name
Test status
Simulation time 716107861 ps
CPU time 4.12 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:29 PM PDT 24
Peak memory 198332 kb
Host smart-fa644b43-9871-4f58-ab78-418676792a2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226131175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3226131175
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2275862982
Short name T304
Test name
Test status
Simulation time 79663807 ps
CPU time 0.75 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 196392 kb
Host smart-2df9bfe9-cff0-4f2d-b2fc-3ed070fb3df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275862982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2275862982
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1608036380
Short name T351
Test name
Test status
Simulation time 80889225 ps
CPU time 0.91 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:17 PM PDT 24
Peak memory 196632 kb
Host smart-c73a391f-0c6b-43cd-94dd-0654c1992913
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608036380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1608036380
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.507943020
Short name T529
Test name
Test status
Simulation time 6437702378 ps
CPU time 78.28 seconds
Started Jun 27 04:24:07 PM PDT 24
Finished Jun 27 04:25:27 PM PDT 24
Peak memory 198580 kb
Host smart-a54077f0-954c-4fd0-beee-9a225ae8a012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507943020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.507943020
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3587855992
Short name T689
Test name
Test status
Simulation time 12871855 ps
CPU time 0.58 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 195320 kb
Host smart-81e04e12-cc1d-4919-84d0-c0a797bc83db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587855992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3587855992
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1450036657
Short name T244
Test name
Test status
Simulation time 50121714 ps
CPU time 0.82 seconds
Started Jun 27 04:24:19 PM PDT 24
Finished Jun 27 04:24:27 PM PDT 24
Peak memory 197420 kb
Host smart-b0d666ca-cfda-42f5-8aa1-466243079281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450036657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1450036657
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.799696849
Short name T142
Test name
Test status
Simulation time 1070640040 ps
CPU time 8.89 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:31 PM PDT 24
Peak memory 198412 kb
Host smart-87f726f1-8ac9-4e87-9656-6ef9745f901c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799696849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.799696849
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.219033323
Short name T20
Test name
Test status
Simulation time 186109501 ps
CPU time 0.74 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:27 PM PDT 24
Peak memory 197012 kb
Host smart-38c6b6f5-a9cb-4713-bbe3-ba5b9beb62c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219033323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.219033323
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1670971871
Short name T127
Test name
Test status
Simulation time 384000215 ps
CPU time 1.24 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:28 PM PDT 24
Peak memory 197384 kb
Host smart-6e239b4e-9de2-4481-af02-741e10a0e2c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670971871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1670971871
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2864707040
Short name T474
Test name
Test status
Simulation time 264328916 ps
CPU time 3.04 seconds
Started Jun 27 04:24:19 PM PDT 24
Finished Jun 27 04:24:30 PM PDT 24
Peak memory 198572 kb
Host smart-afecbf91-cc92-4dd1-a325-d84f572eaa0e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864707040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2864707040
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2340822576
Short name T533
Test name
Test status
Simulation time 347489800 ps
CPU time 2.64 seconds
Started Jun 27 04:24:19 PM PDT 24
Finished Jun 27 04:24:29 PM PDT 24
Peak memory 198524 kb
Host smart-79fba322-2bf1-435f-a805-ca1ba1bdf6ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340822576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2340822576
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2934156899
Short name T161
Test name
Test status
Simulation time 210170474 ps
CPU time 0.92 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 196500 kb
Host smart-f7c6b76d-9371-4520-9060-fc4eace65d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934156899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2934156899
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.799604093
Short name T344
Test name
Test status
Simulation time 18681943 ps
CPU time 0.74 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:16 PM PDT 24
Peak memory 196192 kb
Host smart-edcaaaa3-29e0-4817-8b23-fc892243a58a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799604093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.799604093
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2477336845
Short name T701
Test name
Test status
Simulation time 121596922 ps
CPU time 5.03 seconds
Started Jun 27 04:24:19 PM PDT 24
Finished Jun 27 04:24:32 PM PDT 24
Peak memory 198120 kb
Host smart-4e0b5f59-64ae-46b8-8cc4-abc02cd8d754
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477336845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2477336845
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2163839200
Short name T528
Test name
Test status
Simulation time 351874591 ps
CPU time 1.51 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 195612 kb
Host smart-0ec51ecb-3293-4c6f-8ed7-6bf33ef210ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163839200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2163839200
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1695272310
Short name T273
Test name
Test status
Simulation time 254144264 ps
CPU time 1.18 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 196296 kb
Host smart-48f0c5a3-03e2-4dda-bfb8-3e744521237b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695272310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1695272310
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2261214993
Short name T378
Test name
Test status
Simulation time 19070586323 ps
CPU time 201.62 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:27:44 PM PDT 24
Peak memory 198548 kb
Host smart-22c86f38-3b09-4289-ade4-268126b54882
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261214993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2261214993
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.592557009
Short name T676
Test name
Test status
Simulation time 33429359 ps
CPU time 0.57 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 194472 kb
Host smart-0751e782-f750-4d01-bdfd-06609443b85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592557009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.592557009
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2237507937
Short name T225
Test name
Test status
Simulation time 21989273 ps
CPU time 0.75 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 195408 kb
Host smart-0ae8b993-d910-4ab4-8cbc-f91af17ea5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237507937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2237507937
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.644099538
Short name T478
Test name
Test status
Simulation time 1379348047 ps
CPU time 22.61 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:49 PM PDT 24
Peak memory 195768 kb
Host smart-c5d8e04d-1c6e-43d8-a8d4-8f1c77da7b33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644099538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.644099538
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1527809155
Short name T278
Test name
Test status
Simulation time 99553219 ps
CPU time 0.8 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:20 PM PDT 24
Peak memory 196272 kb
Host smart-f8ec6ef0-24d8-4bd6-9b35-9cf31d615de7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527809155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1527809155
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3958181637
Short name T699
Test name
Test status
Simulation time 63631155 ps
CPU time 1.07 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 196348 kb
Host smart-8b8222e3-3c3f-4945-8112-f84c72c0a48b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958181637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3958181637
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3048421008
Short name T470
Test name
Test status
Simulation time 205541099 ps
CPU time 2.08 seconds
Started Jun 27 04:24:19 PM PDT 24
Finished Jun 27 04:24:29 PM PDT 24
Peak memory 198440 kb
Host smart-62ab749f-59ba-4a34-b8e9-9b7f164e2d8c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048421008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3048421008
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.4283296858
Short name T494
Test name
Test status
Simulation time 231961215 ps
CPU time 1.97 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:20 PM PDT 24
Peak memory 196664 kb
Host smart-4d92a661-864d-46dd-aa14-03e939a8a7f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283296858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.4283296858
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.140821224
Short name T212
Test name
Test status
Simulation time 223504131 ps
CPU time 1.19 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 197408 kb
Host smart-f113fed7-574a-40d1-96cf-30f1ea1450c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140821224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.140821224
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1379432282
Short name T619
Test name
Test status
Simulation time 57442043 ps
CPU time 1.21 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 198492 kb
Host smart-5f53ebb0-0561-45b4-9d93-a25b6be37911
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379432282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1379432282
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1337811568
Short name T146
Test name
Test status
Simulation time 672189870 ps
CPU time 5.23 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 198412 kb
Host smart-36155ab8-a86b-4c8c-8757-8d1d6b8a9e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337811568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1337811568
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3574764435
Short name T700
Test name
Test status
Simulation time 56152449 ps
CPU time 1.38 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 197148 kb
Host smart-c79c5c43-f647-4da2-b78a-04be16372a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574764435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3574764435
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1068461974
Short name T355
Test name
Test status
Simulation time 218190107 ps
CPU time 1.09 seconds
Started Jun 27 04:24:19 PM PDT 24
Finished Jun 27 04:24:28 PM PDT 24
Peak memory 196936 kb
Host smart-98e6be81-0bc6-42d6-9235-f81a0fc77f0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068461974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1068461974
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3189026063
Short name T301
Test name
Test status
Simulation time 4840913370 ps
CPU time 33.56 seconds
Started Jun 27 04:24:11 PM PDT 24
Finished Jun 27 04:24:47 PM PDT 24
Peak memory 198588 kb
Host smart-c3a5b01d-4e3d-48ff-b366-01007d03399c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189026063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3189026063
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2056693819
Short name T206
Test name
Test status
Simulation time 13705351 ps
CPU time 0.58 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 195552 kb
Host smart-65f83904-405b-4161-b91f-c952e2c6ac35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056693819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2056693819
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1958100291
Short name T249
Test name
Test status
Simulation time 58396041 ps
CPU time 0.72 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:17 PM PDT 24
Peak memory 195796 kb
Host smart-28a87732-6e2e-49b4-8d39-76362e6a6992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958100291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1958100291
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2388405620
Short name T712
Test name
Test status
Simulation time 713117263 ps
CPU time 24.2 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:49 PM PDT 24
Peak memory 197440 kb
Host smart-b4b7701d-4552-4fd1-a1e8-61cceda81f2d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388405620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2388405620
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1623489859
Short name T359
Test name
Test status
Simulation time 59816981 ps
CPU time 0.72 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 197068 kb
Host smart-e976b714-a6bf-4fc6-8980-8a59247dfc7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623489859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1623489859
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4022952334
Short name T562
Test name
Test status
Simulation time 73892934 ps
CPU time 0.76 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 195764 kb
Host smart-0d7b65ec-46f3-4fc7-aa32-3a9955a91105
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022952334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4022952334
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3545836234
Short name T209
Test name
Test status
Simulation time 81597442 ps
CPU time 2.87 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:29 PM PDT 24
Peak memory 196924 kb
Host smart-e86e5927-47d5-4411-a663-560629953d60
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545836234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3545836234
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.744273343
Short name T263
Test name
Test status
Simulation time 314852379 ps
CPU time 3.38 seconds
Started Jun 27 04:24:03 PM PDT 24
Finished Jun 27 04:24:09 PM PDT 24
Peak memory 197648 kb
Host smart-7f988cc1-32b9-4a8d-b788-ffbf92fd56da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744273343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
744273343
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2830813037
Short name T680
Test name
Test status
Simulation time 146477429 ps
CPU time 1.2 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:16 PM PDT 24
Peak memory 198488 kb
Host smart-01cc7774-4ace-4660-86bf-030b79759845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830813037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2830813037
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3543088023
Short name T395
Test name
Test status
Simulation time 212898912 ps
CPU time 1.04 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 196540 kb
Host smart-85867cfb-d348-489e-8c2b-e84b963422da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543088023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3543088023
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1745616015
Short name T390
Test name
Test status
Simulation time 219798700 ps
CPU time 3.48 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:28 PM PDT 24
Peak memory 198424 kb
Host smart-c255b2b6-9f87-47bb-9340-ea0dc39b26d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745616015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1745616015
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.714939057
Short name T442
Test name
Test status
Simulation time 211903830 ps
CPU time 1 seconds
Started Jun 27 04:24:14 PM PDT 24
Finished Jun 27 04:24:21 PM PDT 24
Peak memory 196248 kb
Host smart-0692d740-1db3-4443-a07c-30f1dcaca578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714939057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.714939057
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3769373350
Short name T245
Test name
Test status
Simulation time 84521866 ps
CPU time 0.92 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 196220 kb
Host smart-fd59197d-935e-49d6-a79e-fb0ee9f92d7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769373350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3769373350
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2613975876
Short name T384
Test name
Test status
Simulation time 9734654747 ps
CPU time 58.48 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:25:23 PM PDT 24
Peak memory 198620 kb
Host smart-ccce9d89-d3a0-4f06-8333-330cccbd787a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613975876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2613975876
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.737687476
Short name T222
Test name
Test status
Simulation time 14004774 ps
CPU time 0.57 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:15 PM PDT 24
Peak memory 194852 kb
Host smart-5bb59fcc-39c0-4b02-90c4-50f7dd7d96f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737687476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.737687476
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1670076549
Short name T453
Test name
Test status
Simulation time 49941171 ps
CPU time 0.72 seconds
Started Jun 27 04:24:08 PM PDT 24
Finished Jun 27 04:24:09 PM PDT 24
Peak memory 194632 kb
Host smart-3c336aea-c1b6-48e2-ae89-17e8895c2cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670076549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1670076549
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2170698549
Short name T116
Test name
Test status
Simulation time 997661200 ps
CPU time 17.34 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:39 PM PDT 24
Peak memory 197360 kb
Host smart-3ee2cd39-d06e-4e47-b7de-b3a9976cff2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170698549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2170698549
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.960039877
Short name T10
Test name
Test status
Simulation time 112886286 ps
CPU time 0.7 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:17 PM PDT 24
Peak memory 195560 kb
Host smart-74f3d4de-03d3-4e65-b87d-ed117e94f015
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960039877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.960039877
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.219155793
Short name T631
Test name
Test status
Simulation time 21783103 ps
CPU time 0.68 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:22 PM PDT 24
Peak memory 194672 kb
Host smart-069ecac8-51c3-4a68-ad5e-7f47f5d2ecc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219155793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.219155793
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2290957447
Short name T285
Test name
Test status
Simulation time 59497164 ps
CPU time 2.36 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:20 PM PDT 24
Peak memory 197792 kb
Host smart-fd8a7ea9-e291-46d1-9624-e42df0c439ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290957447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2290957447
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1135735312
Short name T270
Test name
Test status
Simulation time 120980142 ps
CPU time 2.3 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:24:12 PM PDT 24
Peak memory 197468 kb
Host smart-061f6574-14b0-483d-a954-3f5e2210474e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135735312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1135735312
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1499289566
Short name T652
Test name
Test status
Simulation time 268928044 ps
CPU time 1.24 seconds
Started Jun 27 04:24:10 PM PDT 24
Finished Jun 27 04:24:12 PM PDT 24
Peak memory 197432 kb
Host smart-1a06345e-fbdd-4b2a-97f6-c5b9b73ae4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499289566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1499289566
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3183770651
Short name T577
Test name
Test status
Simulation time 42819556 ps
CPU time 0.72 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 194760 kb
Host smart-9eba6ea5-d077-43b6-8f80-4e4c4a7cc3eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183770651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3183770651
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1599745855
Short name T545
Test name
Test status
Simulation time 170997694 ps
CPU time 2.96 seconds
Started Jun 27 04:24:16 PM PDT 24
Finished Jun 27 04:24:26 PM PDT 24
Peak memory 198492 kb
Host smart-86b19dc6-bb1c-4513-b556-64817c93e708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599745855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1599745855
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.12142845
Short name T232
Test name
Test status
Simulation time 117636032 ps
CPU time 1.24 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 197356 kb
Host smart-ed4d0f5d-7358-4b8f-8de5-292ae8bb643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12142845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.12142845
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.4185836579
Short name T480
Test name
Test status
Simulation time 94456908 ps
CPU time 0.8 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 195828 kb
Host smart-f9dc7d50-57a3-45b8-af18-cd227ee874fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185836579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.4185836579
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4189438154
Short name T325
Test name
Test status
Simulation time 23994552801 ps
CPU time 163.73 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:27:06 PM PDT 24
Peak memory 198528 kb
Host smart-6f673398-1055-42bc-9050-266500dd9a7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189438154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4189438154
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3932123738
Short name T702
Test name
Test status
Simulation time 888499597808 ps
CPU time 700.59 seconds
Started Jun 27 04:24:13 PM PDT 24
Finished Jun 27 04:35:59 PM PDT 24
Peak memory 206512 kb
Host smart-c5971e64-45a0-4d44-9f32-3a3a4e56a8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3932123738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3932123738
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.612355760
Short name T630
Test name
Test status
Simulation time 27249882 ps
CPU time 0.56 seconds
Started Jun 27 04:24:35 PM PDT 24
Finished Jun 27 04:24:40 PM PDT 24
Peak memory 194940 kb
Host smart-f49d4534-c7c1-43a0-88e2-04716e7838ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612355760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.612355760
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.670891708
Short name T128
Test name
Test status
Simulation time 36437481 ps
CPU time 0.89 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:27 PM PDT 24
Peak memory 197552 kb
Host smart-08f9d297-14a7-4e0b-be61-c48b2afd0280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670891708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.670891708
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1846768444
Short name T718
Test name
Test status
Simulation time 619921197 ps
CPU time 18.55 seconds
Started Jun 27 04:24:28 PM PDT 24
Finished Jun 27 04:24:52 PM PDT 24
Peak memory 198344 kb
Host smart-ea6510fd-f708-4d6c-bd31-d34dcc8407c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846768444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1846768444
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3290553639
Short name T104
Test name
Test status
Simulation time 276083654 ps
CPU time 0.89 seconds
Started Jun 27 04:24:29 PM PDT 24
Finished Jun 27 04:24:35 PM PDT 24
Peak memory 197420 kb
Host smart-b74c0540-bc52-45e3-9ebf-408f0134718a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290553639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3290553639
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1019614384
Short name T387
Test name
Test status
Simulation time 240722002 ps
CPU time 0.98 seconds
Started Jun 27 04:24:17 PM PDT 24
Finished Jun 27 04:24:25 PM PDT 24
Peak memory 197040 kb
Host smart-44913ce1-468a-4b98-8f44-32606af009c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019614384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1019614384
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.4239087076
Short name T439
Test name
Test status
Simulation time 46358898 ps
CPU time 1.27 seconds
Started Jun 27 04:24:27 PM PDT 24
Finished Jun 27 04:24:35 PM PDT 24
Peak memory 197432 kb
Host smart-9107ce09-74d7-4dfd-bed4-bf6eb1e1ae3c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239087076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.4239087076
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.994549682
Short name T99
Test name
Test status
Simulation time 2326733120 ps
CPU time 3.42 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:24:42 PM PDT 24
Peak memory 197892 kb
Host smart-e1269647-b0a5-470d-acbc-6b44e7290383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994549682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
994549682
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3343329758
Short name T485
Test name
Test status
Simulation time 75920578 ps
CPU time 1.32 seconds
Started Jun 27 04:24:18 PM PDT 24
Finished Jun 27 04:24:28 PM PDT 24
Peak memory 198416 kb
Host smart-7b2e343b-cb9a-41f5-b1f8-f4c4b5c550e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343329758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3343329758
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3706901842
Short name T592
Test name
Test status
Simulation time 31345917 ps
CPU time 0.79 seconds
Started Jun 27 04:24:19 PM PDT 24
Finished Jun 27 04:24:27 PM PDT 24
Peak memory 196636 kb
Host smart-4191083f-248b-48ad-8be9-309808c2b91d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706901842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3706901842
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1702541721
Short name T707
Test name
Test status
Simulation time 731325987 ps
CPU time 4.78 seconds
Started Jun 27 04:24:27 PM PDT 24
Finished Jun 27 04:24:38 PM PDT 24
Peak memory 198484 kb
Host smart-644fb80a-19b0-4281-8207-85738af948cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702541721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1702541721
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3059427576
Short name T429
Test name
Test status
Simulation time 44051022 ps
CPU time 1.14 seconds
Started Jun 27 04:24:15 PM PDT 24
Finished Jun 27 04:24:23 PM PDT 24
Peak memory 196840 kb
Host smart-389e7b3c-5878-4598-a20e-3d3fc14327d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059427576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3059427576
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3720022254
Short name T598
Test name
Test status
Simulation time 134511639 ps
CPU time 0.88 seconds
Started Jun 27 04:24:12 PM PDT 24
Finished Jun 27 04:24:16 PM PDT 24
Peak memory 197352 kb
Host smart-3f59f4b5-2136-4834-8aad-fea1b1473551
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720022254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3720022254
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3386321674
Short name T596
Test name
Test status
Simulation time 4410054239 ps
CPU time 106.52 seconds
Started Jun 27 04:24:36 PM PDT 24
Finished Jun 27 04:26:27 PM PDT 24
Peak memory 198700 kb
Host smart-07c93afa-a6ff-4c89-8c9d-ce7928cc51f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386321674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3386321674
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.4126897465
Short name T49
Test name
Test status
Simulation time 27560213302 ps
CPU time 390.99 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:31:10 PM PDT 24
Peak memory 198672 kb
Host smart-5d74649d-05dd-48e0-857e-768ce80eb9ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4126897465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.4126897465
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1564036808
Short name T684
Test name
Test status
Simulation time 31391593 ps
CPU time 0.56 seconds
Started Jun 27 04:24:28 PM PDT 24
Finished Jun 27 04:24:34 PM PDT 24
Peak memory 194488 kb
Host smart-dd4ab493-98c9-45eb-a29e-84674bf99f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564036808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1564036808
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.671697502
Short name T451
Test name
Test status
Simulation time 38698755 ps
CPU time 0.76 seconds
Started Jun 27 04:24:24 PM PDT 24
Finished Jun 27 04:24:32 PM PDT 24
Peak memory 195872 kb
Host smart-6e69ef6b-3901-44dc-9867-94fc98972b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671697502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.671697502
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1224339344
Short name T334
Test name
Test status
Simulation time 1722930194 ps
CPU time 20.48 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:24:59 PM PDT 24
Peak memory 195920 kb
Host smart-1a1920fa-114a-4026-9eb2-795e73fb8d10
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224339344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1224339344
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2858267824
Short name T93
Test name
Test status
Simulation time 34035003 ps
CPU time 0.68 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:24:39 PM PDT 24
Peak memory 195768 kb
Host smart-4d650a23-0fd9-4f3c-88bf-2a50d4932b6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858267824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2858267824
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.99056087
Short name T369
Test name
Test status
Simulation time 280752560 ps
CPU time 1.2 seconds
Started Jun 27 04:24:31 PM PDT 24
Finished Jun 27 04:24:37 PM PDT 24
Peak memory 196276 kb
Host smart-27124484-e3dd-4e63-a575-6b76ae92a58b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99056087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.99056087
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.788528678
Short name T174
Test name
Test status
Simulation time 46757925 ps
CPU time 1.71 seconds
Started Jun 27 04:24:40 PM PDT 24
Finished Jun 27 04:24:44 PM PDT 24
Peak memory 198568 kb
Host smart-3fa10f92-98ec-4c1f-9c04-6f5f5c9f2ca9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788528678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.788528678
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2948934336
Short name T458
Test name
Test status
Simulation time 148744782 ps
CPU time 3.02 seconds
Started Jun 27 04:24:28 PM PDT 24
Finished Jun 27 04:24:37 PM PDT 24
Peak memory 196964 kb
Host smart-a1c91b50-8736-4dff-b2c5-a298cf4380a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948934336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2948934336
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.4203243809
Short name T229
Test name
Test status
Simulation time 77185946 ps
CPU time 0.89 seconds
Started Jun 27 04:24:31 PM PDT 24
Finished Jun 27 04:24:37 PM PDT 24
Peak memory 197084 kb
Host smart-d3869cac-bbd5-469b-9f37-a7b60117fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203243809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.4203243809
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.842582448
Short name T675
Test name
Test status
Simulation time 32928494 ps
CPU time 0.79 seconds
Started Jun 27 04:24:29 PM PDT 24
Finished Jun 27 04:24:35 PM PDT 24
Peak memory 196548 kb
Host smart-f945f440-e99c-4574-a9a4-46a5792cd402
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842582448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.842582448
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3237886058
Short name T650
Test name
Test status
Simulation time 100634920 ps
CPU time 2.3 seconds
Started Jun 27 04:24:30 PM PDT 24
Finished Jun 27 04:24:38 PM PDT 24
Peak memory 198836 kb
Host smart-65e6b0d4-68ac-44c5-b91f-cfbb6e5cf14f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237886058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3237886058
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.139030439
Short name T106
Test name
Test status
Simulation time 43997036 ps
CPU time 0.88 seconds
Started Jun 27 04:24:37 PM PDT 24
Finished Jun 27 04:24:42 PM PDT 24
Peak memory 196180 kb
Host smart-eaa69f6d-a2c2-400c-b68b-ed1e19dbaf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139030439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.139030439
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.860295851
Short name T98
Test name
Test status
Simulation time 35242286 ps
CPU time 1.12 seconds
Started Jun 27 04:24:32 PM PDT 24
Finished Jun 27 04:24:39 PM PDT 24
Peak memory 196284 kb
Host smart-c1e264ec-74f4-4c66-809d-713025b1808a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860295851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.860295851
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1049210675
Short name T13
Test name
Test status
Simulation time 7219485770 ps
CPU time 168.7 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:27:28 PM PDT 24
Peak memory 198536 kb
Host smart-965a0275-8af1-40c0-b3e1-6722da616f0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049210675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1049210675
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1108201184
Short name T687
Test name
Test status
Simulation time 39566952044 ps
CPU time 535.68 seconds
Started Jun 27 04:24:30 PM PDT 24
Finished Jun 27 04:33:31 PM PDT 24
Peak memory 199180 kb
Host smart-9cc98b27-af14-4b2c-945d-20f41a60efb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1108201184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1108201184
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3898409595
Short name T24
Test name
Test status
Simulation time 40262781 ps
CPU time 0.55 seconds
Started Jun 27 04:24:30 PM PDT 24
Finished Jun 27 04:24:36 PM PDT 24
Peak memory 194628 kb
Host smart-adf9ad8f-8f71-46fe-bbd1-e9edcef67ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898409595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3898409595
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3927972465
Short name T452
Test name
Test status
Simulation time 89264693 ps
CPU time 0.68 seconds
Started Jun 27 04:24:40 PM PDT 24
Finished Jun 27 04:24:43 PM PDT 24
Peak memory 195684 kb
Host smart-57983499-c06c-472a-b50e-664e777444f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927972465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3927972465
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1492335368
Short name T364
Test name
Test status
Simulation time 400696338 ps
CPU time 20.3 seconds
Started Jun 27 04:24:34 PM PDT 24
Finished Jun 27 04:25:00 PM PDT 24
Peak memory 198404 kb
Host smart-d754748b-1d13-47c9-a8ea-7e39f3c90c0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492335368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1492335368
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.4038198814
Short name T149
Test name
Test status
Simulation time 18405806 ps
CPU time 0.64 seconds
Started Jun 27 04:24:35 PM PDT 24
Finished Jun 27 04:24:41 PM PDT 24
Peak memory 194636 kb
Host smart-da28ee8f-5a7a-46bd-b569-32b4ce50b454
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038198814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.4038198814
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.172436705
Short name T406
Test name
Test status
Simulation time 76925895 ps
CPU time 0.68 seconds
Started Jun 27 04:24:35 PM PDT 24
Finished Jun 27 04:24:41 PM PDT 24
Peak memory 194784 kb
Host smart-38da4df1-14cc-4b52-b49f-82c84efc43e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172436705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.172436705
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1482914330
Short name T260
Test name
Test status
Simulation time 883530967 ps
CPU time 2.91 seconds
Started Jun 27 04:24:40 PM PDT 24
Finished Jun 27 04:24:46 PM PDT 24
Peak memory 198492 kb
Host smart-18cbbbd2-e1d9-45ce-9623-36c6cbef73aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482914330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1482914330
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.564643983
Short name T717
Test name
Test status
Simulation time 309144019 ps
CPU time 2.29 seconds
Started Jun 27 04:24:28 PM PDT 24
Finished Jun 27 04:24:36 PM PDT 24
Peak memory 196292 kb
Host smart-31bd0f11-6434-40d4-bcc0-8c98a26e86e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564643983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
564643983
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3524868297
Short name T340
Test name
Test status
Simulation time 37265114 ps
CPU time 0.89 seconds
Started Jun 27 04:24:35 PM PDT 24
Finished Jun 27 04:24:41 PM PDT 24
Peak memory 196128 kb
Host smart-26856eec-9371-4dfe-94ac-bfb95ae6261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524868297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3524868297
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2316675917
Short name T397
Test name
Test status
Simulation time 134945124 ps
CPU time 1.16 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:24:40 PM PDT 24
Peak memory 198492 kb
Host smart-971d7c22-b353-496e-80be-995b507d8b87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316675917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2316675917
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.513187869
Short name T475
Test name
Test status
Simulation time 341482004 ps
CPU time 4.49 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:24:43 PM PDT 24
Peak memory 198400 kb
Host smart-d6135c7d-27d9-480e-ba0d-c56f00eb91a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513187869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.513187869
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1756037470
Short name T122
Test name
Test status
Simulation time 170120886 ps
CPU time 1.15 seconds
Started Jun 27 04:24:29 PM PDT 24
Finished Jun 27 04:24:36 PM PDT 24
Peak memory 196304 kb
Host smart-e4cf79c1-cb6b-47a2-843b-3a71b5ea3b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756037470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1756037470
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2140529342
Short name T552
Test name
Test status
Simulation time 184473554 ps
CPU time 1.37 seconds
Started Jun 27 04:24:40 PM PDT 24
Finished Jun 27 04:24:44 PM PDT 24
Peak memory 198556 kb
Host smart-10a5dc85-d94d-4586-8c26-0367510fd042
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140529342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2140529342
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2024558651
Short name T170
Test name
Test status
Simulation time 6021104434 ps
CPU time 162.86 seconds
Started Jun 27 04:24:30 PM PDT 24
Finished Jun 27 04:27:18 PM PDT 24
Peak memory 198932 kb
Host smart-e7bcb852-a0fb-4a75-afd1-64ac85853565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024558651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2024558651
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1248496497
Short name T338
Test name
Test status
Simulation time 84355008 ps
CPU time 0.55 seconds
Started Jun 27 04:24:43 PM PDT 24
Finished Jun 27 04:24:45 PM PDT 24
Peak memory 194456 kb
Host smart-28b89959-8e00-492c-a3d9-178e098da405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248496497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1248496497
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1611705350
Short name T279
Test name
Test status
Simulation time 45054524 ps
CPU time 0.81 seconds
Started Jun 27 04:24:40 PM PDT 24
Finished Jun 27 04:24:44 PM PDT 24
Peak memory 195892 kb
Host smart-b0614c35-58da-45da-b78c-98350d20f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611705350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1611705350
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3017442758
Short name T593
Test name
Test status
Simulation time 1817494945 ps
CPU time 19.77 seconds
Started Jun 27 04:24:28 PM PDT 24
Finished Jun 27 04:24:54 PM PDT 24
Peak memory 195972 kb
Host smart-2546b7d7-4db1-4b50-9f32-f0067bc3b4cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017442758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3017442758
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1883568125
Short name T535
Test name
Test status
Simulation time 191587452 ps
CPU time 1.1 seconds
Started Jun 27 04:24:30 PM PDT 24
Finished Jun 27 04:24:37 PM PDT 24
Peak memory 197448 kb
Host smart-f94a944a-d2d8-43d8-97c2-f64cb4346630
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883568125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1883568125
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3337682014
Short name T634
Test name
Test status
Simulation time 117372362 ps
CPU time 0.95 seconds
Started Jun 27 04:24:35 PM PDT 24
Finished Jun 27 04:24:41 PM PDT 24
Peak memory 196532 kb
Host smart-d06fd4e7-524b-4a54-af66-6b74b941f55b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337682014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3337682014
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2291824606
Short name T16
Test name
Test status
Simulation time 107499443 ps
CPU time 1.23 seconds
Started Jun 27 04:24:36 PM PDT 24
Finished Jun 27 04:24:42 PM PDT 24
Peak memory 196780 kb
Host smart-ce3679d2-4ae0-4f62-974d-cd93fa69fc56
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291824606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2291824606
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1459920044
Short name T289
Test name
Test status
Simulation time 201243673 ps
CPU time 2.11 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:24:41 PM PDT 24
Peak memory 198512 kb
Host smart-efcabad4-69ab-4e49-9335-2d6390999cfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459920044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1459920044
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1590780968
Short name T148
Test name
Test status
Simulation time 283858804 ps
CPU time 1.14 seconds
Started Jun 27 04:24:33 PM PDT 24
Finished Jun 27 04:24:40 PM PDT 24
Peak memory 197112 kb
Host smart-1d814c72-b9ef-41f3-a399-ad7d079923fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590780968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1590780968
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3684123577
Short name T532
Test name
Test status
Simulation time 80329636 ps
CPU time 0.86 seconds
Started Jun 27 04:24:31 PM PDT 24
Finished Jun 27 04:24:38 PM PDT 24
Peak memory 197036 kb
Host smart-6dc73bc6-9a73-4b57-aac9-d26d1848104c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684123577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3684123577
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2758317627
Short name T382
Test name
Test status
Simulation time 599504123 ps
CPU time 4.71 seconds
Started Jun 27 04:24:32 PM PDT 24
Finished Jun 27 04:24:43 PM PDT 24
Peak memory 198496 kb
Host smart-11d2d906-6e86-40e0-9f32-f9dbabdd74d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758317627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2758317627
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2503852029
Short name T346
Test name
Test status
Simulation time 31967193 ps
CPU time 0.8 seconds
Started Jun 27 04:24:34 PM PDT 24
Finished Jun 27 04:24:40 PM PDT 24
Peak memory 195608 kb
Host smart-946b2128-3034-4ef9-865d-553342f1a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503852029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2503852029
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2174184349
Short name T642
Test name
Test status
Simulation time 28656974 ps
CPU time 0.91 seconds
Started Jun 27 04:24:28 PM PDT 24
Finished Jun 27 04:24:35 PM PDT 24
Peak memory 195872 kb
Host smart-5b727c60-9505-49cb-b1d1-ecd49c1c89d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174184349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2174184349
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.876169690
Short name T253
Test name
Test status
Simulation time 2279541897 ps
CPU time 32.76 seconds
Started Jun 27 04:24:35 PM PDT 24
Finished Jun 27 04:25:13 PM PDT 24
Peak memory 198388 kb
Host smart-81952d19-413d-48e3-bcfd-f67e18878965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876169690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.876169690
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3743660749
Short name T47
Test name
Test status
Simulation time 119881974250 ps
CPU time 2325.88 seconds
Started Jun 27 04:24:28 PM PDT 24
Finished Jun 27 05:03:20 PM PDT 24
Peak memory 198508 kb
Host smart-90cba02a-86bf-47d9-be04-331a0bbcfb2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3743660749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3743660749
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.416665865
Short name T155
Test name
Test status
Simulation time 13934807 ps
CPU time 0.55 seconds
Started Jun 27 04:24:43 PM PDT 24
Finished Jun 27 04:24:45 PM PDT 24
Peak memory 194576 kb
Host smart-27969338-13f8-479e-8f93-34913f12442b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416665865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.416665865
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2071402081
Short name T381
Test name
Test status
Simulation time 29607283 ps
CPU time 0.85 seconds
Started Jun 27 04:24:43 PM PDT 24
Finished Jun 27 04:24:45 PM PDT 24
Peak memory 196376 kb
Host smart-795c983f-6d9a-47ec-a1f4-8946d5ef9595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071402081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2071402081
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.926527345
Short name T133
Test name
Test status
Simulation time 832870688 ps
CPU time 10.72 seconds
Started Jun 27 04:24:43 PM PDT 24
Finished Jun 27 04:24:55 PM PDT 24
Peak memory 197336 kb
Host smart-472266ec-6777-4b0e-9311-15c56217e311
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926527345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.926527345
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3773343960
Short name T571
Test name
Test status
Simulation time 230134307 ps
CPU time 1.01 seconds
Started Jun 27 04:24:31 PM PDT 24
Finished Jun 27 04:24:38 PM PDT 24
Peak memory 198492 kb
Host smart-ebd7f371-254a-4fa5-93be-8f23c6335b71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773343960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3773343960
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.166136458
Short name T151
Test name
Test status
Simulation time 222244603 ps
CPU time 0.88 seconds
Started Jun 27 04:24:43 PM PDT 24
Finished Jun 27 04:24:45 PM PDT 24
Peak memory 196964 kb
Host smart-737e6ae3-0bec-4044-8dc7-de2bbf3ab17f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166136458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.166136458
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2637499894
Short name T17
Test name
Test status
Simulation time 89544395 ps
CPU time 3.31 seconds
Started Jun 27 04:24:32 PM PDT 24
Finished Jun 27 04:24:42 PM PDT 24
Peak memory 198480 kb
Host smart-f5263fb6-c0d5-473f-ad8d-e8ae153cd31f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637499894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2637499894
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1113117020
Short name T599
Test name
Test status
Simulation time 142027258 ps
CPU time 1.68 seconds
Started Jun 27 04:24:36 PM PDT 24
Finished Jun 27 04:24:42 PM PDT 24
Peak memory 196680 kb
Host smart-a4ef7e1f-849c-4919-8207-e96f75672004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113117020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1113117020
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.822961177
Short name T102
Test name
Test status
Simulation time 16826506 ps
CPU time 0.68 seconds
Started Jun 27 04:24:41 PM PDT 24
Finished Jun 27 04:24:44 PM PDT 24
Peak memory 195756 kb
Host smart-02516c9c-1c84-423a-beaa-edc57a0222f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822961177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.822961177
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1024699706
Short name T551
Test name
Test status
Simulation time 33892368 ps
CPU time 0.85 seconds
Started Jun 27 04:24:38 PM PDT 24
Finished Jun 27 04:24:43 PM PDT 24
Peak memory 196972 kb
Host smart-d3d58117-ee4c-4ee4-be64-23d28c7f4155
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024699706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1024699706
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.740865501
Short name T5
Test name
Test status
Simulation time 813072885 ps
CPU time 4.91 seconds
Started Jun 27 04:24:46 PM PDT 24
Finished Jun 27 04:24:52 PM PDT 24
Peak memory 198616 kb
Host smart-3b04c3ab-2815-4ed8-980c-7ab222185033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740865501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.740865501
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3526853881
Short name T575
Test name
Test status
Simulation time 214864706 ps
CPU time 1.08 seconds
Started Jun 27 04:24:31 PM PDT 24
Finished Jun 27 04:24:38 PM PDT 24
Peak memory 196256 kb
Host smart-b91c3751-d542-4db4-aa58-f8d519b6778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526853881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3526853881
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2207303298
Short name T647
Test name
Test status
Simulation time 51205112 ps
CPU time 0.83 seconds
Started Jun 27 04:24:31 PM PDT 24
Finished Jun 27 04:24:38 PM PDT 24
Peak memory 195852 kb
Host smart-b92ea0fc-8821-4120-a58b-e2402744ae55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207303298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2207303298
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3140562152
Short name T524
Test name
Test status
Simulation time 7274907835 ps
CPU time 95.76 seconds
Started Jun 27 04:24:27 PM PDT 24
Finished Jun 27 04:26:09 PM PDT 24
Peak memory 198612 kb
Host smart-99e440eb-20e9-47f6-9705-d715ed3c503c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140562152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3140562152
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1910026568
Short name T368
Test name
Test status
Simulation time 20605116547 ps
CPU time 271.74 seconds
Started Jun 27 04:24:46 PM PDT 24
Finished Jun 27 04:29:19 PM PDT 24
Peak memory 198668 kb
Host smart-f804ee7e-bfcd-4ce2-b271-59117d7cb97e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1910026568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1910026568
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.544720370
Short name T168
Test name
Test status
Simulation time 39950585 ps
CPU time 0.59 seconds
Started Jun 27 04:20:56 PM PDT 24
Finished Jun 27 04:20:58 PM PDT 24
Peak memory 194512 kb
Host smart-690dc845-c477-4294-ae9c-b1ff51aa75ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544720370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.544720370
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2096165716
Short name T440
Test name
Test status
Simulation time 30184876 ps
CPU time 0.9 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:45 PM PDT 24
Peak memory 195596 kb
Host smart-197027c5-2073-46be-bc65-f43d81297232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096165716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2096165716
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3438453810
Short name T366
Test name
Test status
Simulation time 270021707 ps
CPU time 13.11 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:24:04 PM PDT 24
Peak memory 197136 kb
Host smart-941d43b6-077a-4370-a38c-7b89f7a67f6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438453810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3438453810
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3700915666
Short name T287
Test name
Test status
Simulation time 93005309 ps
CPU time 0.6 seconds
Started Jun 27 04:23:45 PM PDT 24
Finished Jun 27 04:23:59 PM PDT 24
Peak memory 195316 kb
Host smart-9fca9edf-b620-4fbf-95a6-41372632cd52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700915666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3700915666
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2304466281
Short name T454
Test name
Test status
Simulation time 69371319 ps
CPU time 1.3 seconds
Started Jun 27 04:21:38 PM PDT 24
Finished Jun 27 04:21:40 PM PDT 24
Peak memory 197108 kb
Host smart-f5b97844-8f39-4aa7-a0ef-12a7fc78e2eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304466281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2304466281
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4178736981
Short name T178
Test name
Test status
Simulation time 131594166 ps
CPU time 1.31 seconds
Started Jun 27 04:23:31 PM PDT 24
Finished Jun 27 04:23:46 PM PDT 24
Peak memory 196560 kb
Host smart-034602e4-ae22-43cb-94c2-c488239906a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178736981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4178736981
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2862668289
Short name T328
Test name
Test status
Simulation time 71917025 ps
CPU time 2.04 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:56 PM PDT 24
Peak memory 196804 kb
Host smart-1968a4e0-cf6a-4729-8e22-a360cfa24fbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862668289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2862668289
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2982259408
Short name T57
Test name
Test status
Simulation time 77579348 ps
CPU time 1.16 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 197184 kb
Host smart-34b87088-cdc9-4016-8942-ba41d8ea6d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982259408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2982259408
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2599576800
Short name T568
Test name
Test status
Simulation time 110111310 ps
CPU time 0.83 seconds
Started Jun 27 04:21:37 PM PDT 24
Finished Jun 27 04:21:38 PM PDT 24
Peak memory 197168 kb
Host smart-c4b11fd3-c79e-4d83-a5c1-8a748e906f3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599576800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2599576800
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3011894404
Short name T192
Test name
Test status
Simulation time 528541617 ps
CPU time 4.83 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 196592 kb
Host smart-864150b8-bb26-4b6c-9b74-ad3ccf5953da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011894404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3011894404
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2784243330
Short name T317
Test name
Test status
Simulation time 130382312 ps
CPU time 1.07 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:35 PM PDT 24
Peak memory 195532 kb
Host smart-f4599f8a-c237-4b84-b706-3deb1479bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784243330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2784243330
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3056351564
Short name T354
Test name
Test status
Simulation time 55594973 ps
CPU time 0.83 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:45 PM PDT 24
Peak memory 193948 kb
Host smart-1fd610cd-754b-4265-a66a-c8414001664c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056351564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3056351564
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2974532174
Short name T91
Test name
Test status
Simulation time 24659337014 ps
CPU time 22.67 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:24:17 PM PDT 24
Peak memory 197216 kb
Host smart-64f4b230-931a-4d06-bc2f-910ea7607344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974532174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2974532174
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.729830822
Short name T404
Test name
Test status
Simulation time 425886102814 ps
CPU time 2017.02 seconds
Started Jun 27 04:21:37 PM PDT 24
Finished Jun 27 04:55:14 PM PDT 24
Peak memory 198800 kb
Host smart-0dc92bb6-1b42-47dc-a1eb-96ebd12b21eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=729830822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.729830822
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2070134770
Short name T185
Test name
Test status
Simulation time 26477360 ps
CPU time 0.54 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 193288 kb
Host smart-2c837439-9ed2-4d22-bef6-8dfd1f73d8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070134770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2070134770
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1066415426
Short name T482
Test name
Test status
Simulation time 54513245 ps
CPU time 0.58 seconds
Started Jun 27 04:23:43 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 194128 kb
Host smart-cc5e0e86-9559-449f-b643-5e62a7e68152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066415426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1066415426
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.84112364
Short name T94
Test name
Test status
Simulation time 1262882760 ps
CPU time 21.85 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 197376 kb
Host smart-709e8205-02b5-474f-b3fe-03b72e49699a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84112364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress.84112364
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2114176424
Short name T164
Test name
Test status
Simulation time 24471451 ps
CPU time 0.64 seconds
Started Jun 27 04:23:32 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 195064 kb
Host smart-7610447f-27de-4906-b8c9-18031b52122a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114176424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2114176424
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2492976682
Short name T330
Test name
Test status
Simulation time 192306518 ps
CPU time 1.22 seconds
Started Jun 27 04:23:31 PM PDT 24
Finished Jun 27 04:23:46 PM PDT 24
Peak memory 197392 kb
Host smart-87bc75a0-3dbe-4545-8c11-aaea3cc797a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492976682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2492976682
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.168489011
Short name T349
Test name
Test status
Simulation time 117763671 ps
CPU time 1.35 seconds
Started Jun 27 04:23:43 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 198060 kb
Host smart-5c1cbe17-0ce6-4c96-a01c-1799a32c89bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168489011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.168489011
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3719129233
Short name T177
Test name
Test status
Simulation time 349306169 ps
CPU time 3.14 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 197348 kb
Host smart-46746295-dc2c-4c8e-9c4c-ea2beb3bfd92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719129233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3719129233
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2998394985
Short name T410
Test name
Test status
Simulation time 256263223 ps
CPU time 0.97 seconds
Started Jun 27 04:23:43 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 196120 kb
Host smart-5cda86e9-0830-4317-81e4-99ef17b8882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998394985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2998394985
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2999494923
Short name T613
Test name
Test status
Simulation time 101392427 ps
CPU time 0.98 seconds
Started Jun 27 04:22:04 PM PDT 24
Finished Jun 27 04:22:06 PM PDT 24
Peak memory 196700 kb
Host smart-0839595f-93ca-490f-9816-dc1fa77e5109
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999494923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2999494923
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1694792996
Short name T205
Test name
Test status
Simulation time 584228504 ps
CPU time 5.03 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:52 PM PDT 24
Peak memory 198048 kb
Host smart-3ef59178-1500-4a80-9f51-5f2c5da1fb0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694792996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1694792996
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.899879474
Short name T257
Test name
Test status
Simulation time 100210962 ps
CPU time 1.05 seconds
Started Jun 27 04:20:50 PM PDT 24
Finished Jun 27 04:20:51 PM PDT 24
Peak memory 196456 kb
Host smart-99fdfe3d-2d69-4e13-a794-ed1f325797c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899879474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.899879474
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.513084095
Short name T179
Test name
Test status
Simulation time 217009651 ps
CPU time 0.89 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 196088 kb
Host smart-4010fd1e-757f-4fb9-96e3-87d1b2adf1ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513084095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.513084095
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2008439978
Short name T449
Test name
Test status
Simulation time 12147385956 ps
CPU time 162.52 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:26:31 PM PDT 24
Peak memory 197168 kb
Host smart-5845939e-8927-4a07-be38-8ba3ad3c7111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008439978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2008439978
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.4067899261
Short name T564
Test name
Test status
Simulation time 33374750124 ps
CPU time 862.46 seconds
Started Jun 27 04:23:43 PM PDT 24
Finished Jun 27 04:38:20 PM PDT 24
Peak memory 198488 kb
Host smart-adff05d6-02fd-4318-825f-975d1be40e72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4067899261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.4067899261
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1176466722
Short name T202
Test name
Test status
Simulation time 19322864 ps
CPU time 0.57 seconds
Started Jun 27 04:22:25 PM PDT 24
Finished Jun 27 04:22:27 PM PDT 24
Peak memory 193592 kb
Host smart-fa338764-34b5-4c45-ad98-3349db7926fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176466722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1176466722
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2125948655
Short name T153
Test name
Test status
Simulation time 66417974 ps
CPU time 0.61 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 195076 kb
Host smart-c05ee06d-ecfb-439e-b235-8f5d9ed35648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125948655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2125948655
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1136394079
Short name T554
Test name
Test status
Simulation time 140495471 ps
CPU time 4.04 seconds
Started Jun 27 04:23:39 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 195700 kb
Host smart-ae9f2f77-3c09-442e-a619-24df6cd88873
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136394079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1136394079
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3011250823
Short name T348
Test name
Test status
Simulation time 75221233 ps
CPU time 0.69 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 196120 kb
Host smart-a14bc1c1-dd9c-4f51-81a1-ed2956db429f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011250823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3011250823
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3175287348
Short name T481
Test name
Test status
Simulation time 79687820 ps
CPU time 0.79 seconds
Started Jun 27 04:23:43 PM PDT 24
Finished Jun 27 04:23:58 PM PDT 24
Peak memory 195736 kb
Host smart-600728bf-32cd-4110-b908-3823cd7e78ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175287348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3175287348
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.490459747
Short name T628
Test name
Test status
Simulation time 279610513 ps
CPU time 1.73 seconds
Started Jun 27 04:23:31 PM PDT 24
Finished Jun 27 04:23:46 PM PDT 24
Peak memory 198276 kb
Host smart-da252330-9f9e-4655-a843-fa4d87f3808a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490459747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.490459747
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3419426026
Short name T543
Test name
Test status
Simulation time 86579775 ps
CPU time 2.24 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:02 PM PDT 24
Peak memory 197428 kb
Host smart-90281b03-e624-4911-988f-42b260e7f565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419426026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3419426026
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1986432457
Short name T405
Test name
Test status
Simulation time 64512474 ps
CPU time 1.22 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 197472 kb
Host smart-b366b9b7-a9b0-43ff-89ac-d1666bead9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986432457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1986432457
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.407406517
Short name T537
Test name
Test status
Simulation time 69393992 ps
CPU time 1.25 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 195624 kb
Host smart-0e1930de-3dd4-4baf-bfd2-6cf75e818982
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407406517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.407406517
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4201268617
Short name T622
Test name
Test status
Simulation time 310290245 ps
CPU time 4.74 seconds
Started Jun 27 04:23:40 PM PDT 24
Finished Jun 27 04:24:00 PM PDT 24
Peak memory 198072 kb
Host smart-229aead8-8da3-4fd3-8694-ec51a8fa2b22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201268617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4201268617
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3516069718
Short name T548
Test name
Test status
Simulation time 47647764 ps
CPU time 0.95 seconds
Started Jun 27 04:23:48 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 195976 kb
Host smart-1e4ea83f-afc5-42d4-abfb-d956b7d6eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516069718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3516069718
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.963967390
Short name T625
Test name
Test status
Simulation time 34645706 ps
CPU time 0.79 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 196108 kb
Host smart-c78d5370-7f46-48a0-a5f2-b0a151e91a26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963967390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.963967390
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.775210516
Short name T512
Test name
Test status
Simulation time 10529870885 ps
CPU time 53.55 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:24:05 PM PDT 24
Peak memory 198180 kb
Host smart-49adcd81-f731-4836-99ff-8e54e55d1010
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775210516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.775210516
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1789232285
Short name T678
Test name
Test status
Simulation time 55191162146 ps
CPU time 339.98 seconds
Started Jun 27 04:22:32 PM PDT 24
Finished Jun 27 04:28:14 PM PDT 24
Peak memory 198264 kb
Host smart-9e0751c2-f51f-48e9-bf92-4bb6426229c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1789232285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1789232285
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1923982605
Short name T105
Test name
Test status
Simulation time 42804463 ps
CPU time 0.62 seconds
Started Jun 27 04:21:05 PM PDT 24
Finished Jun 27 04:21:06 PM PDT 24
Peak memory 195544 kb
Host smart-643ec38f-aea4-4818-a441-ab03290b927a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923982605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1923982605
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.731949372
Short name T587
Test name
Test status
Simulation time 98068343 ps
CPU time 0.78 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 193628 kb
Host smart-2a38fab4-adee-4bde-b73b-981136118ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731949372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.731949372
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.4131669978
Short name T658
Test name
Test status
Simulation time 1372562640 ps
CPU time 14.06 seconds
Started Jun 27 04:21:04 PM PDT 24
Finished Jun 27 04:21:18 PM PDT 24
Peak memory 196656 kb
Host smart-839a7b32-17ba-4076-bbcc-5ee5bbd6418b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131669978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.4131669978
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.183805272
Short name T299
Test name
Test status
Simulation time 84635983 ps
CPU time 0.95 seconds
Started Jun 27 04:22:46 PM PDT 24
Finished Jun 27 04:22:50 PM PDT 24
Peak memory 198024 kb
Host smart-312ea0f5-70d8-41b7-b984-0fefee54dc59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183805272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.183805272
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1662472960
Short name T154
Test name
Test status
Simulation time 193041040 ps
CPU time 0.93 seconds
Started Jun 27 04:22:33 PM PDT 24
Finished Jun 27 04:22:36 PM PDT 24
Peak memory 196024 kb
Host smart-3e57caed-ad88-4bf2-b178-1493321acc2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662472960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1662472960
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2102708081
Short name T264
Test name
Test status
Simulation time 66846332 ps
CPU time 2.47 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:36 PM PDT 24
Peak memory 198108 kb
Host smart-4818eb9b-7b7d-410e-9573-981ca3041a6e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102708081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2102708081
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3996687012
Short name T489
Test name
Test status
Simulation time 248482320 ps
CPU time 3.34 seconds
Started Jun 27 04:22:32 PM PDT 24
Finished Jun 27 04:22:37 PM PDT 24
Peak memory 196988 kb
Host smart-c820813d-0638-4860-9193-e4aaf5f197d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996687012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3996687012
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3973055941
Short name T56
Test name
Test status
Simulation time 87094611 ps
CPU time 0.95 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:23:51 PM PDT 24
Peak memory 196376 kb
Host smart-b2c98d66-3de8-45b6-a228-befb4948df56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973055941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3973055941
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1405124938
Short name T123
Test name
Test status
Simulation time 54740094 ps
CPU time 0.78 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:23:13 PM PDT 24
Peak memory 196816 kb
Host smart-6c7a0421-cb3a-452f-aea3-2956431ffa87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405124938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1405124938
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1769537254
Short name T197
Test name
Test status
Simulation time 368576996 ps
CPU time 4.12 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:15 PM PDT 24
Peak memory 196196 kb
Host smart-e7d1e3f9-d977-4ff1-afbd-fef30b588525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769537254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1769537254
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2411540592
Short name T448
Test name
Test status
Simulation time 85272373 ps
CPU time 1.12 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 195216 kb
Host smart-14180dbe-c896-4594-a2d7-985a01411e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411540592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2411540592
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1820352228
Short name T586
Test name
Test status
Simulation time 38895161 ps
CPU time 1.02 seconds
Started Jun 27 04:22:47 PM PDT 24
Finished Jun 27 04:22:51 PM PDT 24
Peak memory 196152 kb
Host smart-2ee4aed3-e022-41ce-83cd-b7874e6598c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820352228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1820352228
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1497806954
Short name T569
Test name
Test status
Simulation time 8611355045 ps
CPU time 35.26 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:23:48 PM PDT 24
Peak memory 198348 kb
Host smart-7b7524bb-fb2a-4e38-ae55-85993b7e2d73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497806954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1497806954
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.915009188
Short name T611
Test name
Test status
Simulation time 20381906868 ps
CPU time 522.66 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:31:16 PM PDT 24
Peak memory 196692 kb
Host smart-035fb698-92be-47bb-a258-5f1391d17171
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=915009188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.915009188
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1417407287
Short name T210
Test name
Test status
Simulation time 11503167 ps
CPU time 0.53 seconds
Started Jun 27 04:23:06 PM PDT 24
Finished Jun 27 04:23:10 PM PDT 24
Peak memory 194180 kb
Host smart-4f447f84-e30e-44b7-be1a-c73780658260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417407287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1417407287
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1188187292
Short name T211
Test name
Test status
Simulation time 27651878 ps
CPU time 0.83 seconds
Started Jun 27 04:22:31 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 196104 kb
Host smart-c6607f3f-856c-4b49-b675-1bb38ce4a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188187292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1188187292
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1963521642
Short name T119
Test name
Test status
Simulation time 882392524 ps
CPU time 6.24 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:17 PM PDT 24
Peak memory 195388 kb
Host smart-4dec039e-c2ce-4432-8c40-aa723cc879c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963521642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1963521642
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.315594522
Short name T362
Test name
Test status
Simulation time 80367784 ps
CPU time 0.91 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:12 PM PDT 24
Peak memory 195944 kb
Host smart-5677e4ee-0504-44c5-b048-057f50bfcbd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315594522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.315594522
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.709019914
Short name T484
Test name
Test status
Simulation time 91749194 ps
CPU time 1.22 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:13 PM PDT 24
Peak memory 196088 kb
Host smart-34052889-cdc0-4df4-a254-774ac21d8960
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709019914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.709019914
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1603646636
Short name T101
Test name
Test status
Simulation time 297307123 ps
CPU time 3.11 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:36 PM PDT 24
Peak memory 198020 kb
Host smart-9d1b14af-871a-4f29-8c57-57c3eb90b12d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603646636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1603646636
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1123195726
Short name T431
Test name
Test status
Simulation time 332426763 ps
CPU time 1.9 seconds
Started Jun 27 04:22:32 PM PDT 24
Finished Jun 27 04:22:35 PM PDT 24
Peak memory 196968 kb
Host smart-87f24acd-5114-4ba7-aab8-529f075b45a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123195726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1123195726
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.624012483
Short name T223
Test name
Test status
Simulation time 196277114 ps
CPU time 0.86 seconds
Started Jun 27 04:22:46 PM PDT 24
Finished Jun 27 04:22:50 PM PDT 24
Peak memory 196208 kb
Host smart-9c7995fe-f6bb-415d-80ed-320dc8319e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624012483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.624012483
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2525108996
Short name T682
Test name
Test status
Simulation time 55731253 ps
CPU time 0.98 seconds
Started Jun 27 04:21:34 PM PDT 24
Finished Jun 27 04:21:36 PM PDT 24
Peak memory 196540 kb
Host smart-33de76bf-54cf-4c4f-8e83-44d2841ba93f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525108996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2525108996
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.394358206
Short name T565
Test name
Test status
Simulation time 400569140 ps
CPU time 3.82 seconds
Started Jun 27 04:22:46 PM PDT 24
Finished Jun 27 04:22:53 PM PDT 24
Peak memory 198432 kb
Host smart-931c6b6c-a257-46bc-9287-43a913eb0652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394358206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.394358206
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3296849236
Short name T654
Test name
Test status
Simulation time 228878612 ps
CPU time 1.03 seconds
Started Jun 27 04:23:22 PM PDT 24
Finished Jun 27 04:23:34 PM PDT 24
Peak memory 196184 kb
Host smart-211db1a9-5fd0-418f-8f30-c52c5354b990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296849236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3296849236
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3648376545
Short name T261
Test name
Test status
Simulation time 44084775 ps
CPU time 1.19 seconds
Started Jun 27 04:22:39 PM PDT 24
Finished Jun 27 04:22:42 PM PDT 24
Peak memory 198444 kb
Host smart-ab259238-858f-4d79-bd03-bc6a050d03eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648376545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3648376545
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1025618891
Short name T277
Test name
Test status
Simulation time 38430961069 ps
CPU time 95.05 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:25:26 PM PDT 24
Peak memory 198420 kb
Host smart-23c6132e-7833-404b-a41b-be11b394d233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025618891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1025618891
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.991708969
Short name T867
Test name
Test status
Simulation time 38537947 ps
CPU time 1.18 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:22:44 PM PDT 24
Peak memory 197236 kb
Host smart-d6f4ebea-fc13-4697-a3af-743b0ee18445
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=991708969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.991708969
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2071254030
Short name T914
Test name
Test status
Simulation time 37783213 ps
CPU time 0.92 seconds
Started Jun 27 04:23:38 PM PDT 24
Finished Jun 27 04:23:54 PM PDT 24
Peak memory 197848 kb
Host smart-180fc405-bcb2-4aae-9917-0b6ea3544d44
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071254030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2071254030
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3603856350
Short name T873
Test name
Test status
Simulation time 55927788 ps
CPU time 1.22 seconds
Started Jun 27 04:19:06 PM PDT 24
Finished Jun 27 04:19:08 PM PDT 24
Peak memory 196188 kb
Host smart-7da97c21-6213-49b8-b672-757fff984475
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3603856350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3603856350
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2236565750
Short name T860
Test name
Test status
Simulation time 60693940 ps
CPU time 1.11 seconds
Started Jun 27 04:19:47 PM PDT 24
Finished Jun 27 04:19:49 PM PDT 24
Peak memory 198272 kb
Host smart-ff529ee9-69a5-42ea-9a22-c64c59d7548c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236565750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2236565750
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4145018070
Short name T911
Test name
Test status
Simulation time 72013704 ps
CPU time 0.97 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:23:14 PM PDT 24
Peak memory 197228 kb
Host smart-42d98418-c894-4581-9eba-c8ffbfc5de0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4145018070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.4145018070
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2845293442
Short name T929
Test name
Test status
Simulation time 191335112 ps
CPU time 1.22 seconds
Started Jun 27 04:20:36 PM PDT 24
Finished Jun 27 04:20:40 PM PDT 24
Peak memory 196908 kb
Host smart-09fca799-fdf2-4b7f-b0e5-ca02442e2775
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845293442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2845293442
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3459952654
Short name T942
Test name
Test status
Simulation time 106621248 ps
CPU time 0.72 seconds
Started Jun 27 04:23:38 PM PDT 24
Finished Jun 27 04:23:54 PM PDT 24
Peak memory 195384 kb
Host smart-a732ea5a-6355-411e-91a6-a7146f3ea621
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3459952654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3459952654
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2877583021
Short name T934
Test name
Test status
Simulation time 37945921 ps
CPU time 0.75 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 195488 kb
Host smart-5e714172-cd1b-4d30-a1cc-bd4a4f8b3d70
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877583021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2877583021
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2929278224
Short name T893
Test name
Test status
Simulation time 29893481 ps
CPU time 0.94 seconds
Started Jun 27 04:19:21 PM PDT 24
Finished Jun 27 04:19:23 PM PDT 24
Peak memory 197188 kb
Host smart-b766ac8e-8ca2-455f-bf3d-d20e1db93e2a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2929278224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2929278224
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3549932608
Short name T903
Test name
Test status
Simulation time 250709474 ps
CPU time 0.84 seconds
Started Jun 27 04:19:21 PM PDT 24
Finished Jun 27 04:19:23 PM PDT 24
Peak memory 197048 kb
Host smart-a31d1e06-21f4-45ba-a526-1dcd288ab1bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549932608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3549932608
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.286963177
Short name T937
Test name
Test status
Simulation time 32971158 ps
CPU time 0.86 seconds
Started Jun 27 04:23:24 PM PDT 24
Finished Jun 27 04:23:37 PM PDT 24
Peak memory 194872 kb
Host smart-7384f84d-e232-4e82-991b-c8e299480b39
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=286963177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.286963177
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2150187799
Short name T861
Test name
Test status
Simulation time 63636513 ps
CPU time 1.28 seconds
Started Jun 27 04:23:26 PM PDT 24
Finished Jun 27 04:23:40 PM PDT 24
Peak memory 196180 kb
Host smart-f4eb9ec7-ef0e-404c-980b-3fb6e0524192
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150187799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2150187799
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3797832689
Short name T856
Test name
Test status
Simulation time 263306681 ps
CPU time 1.04 seconds
Started Jun 27 04:21:40 PM PDT 24
Finished Jun 27 04:21:42 PM PDT 24
Peak memory 196884 kb
Host smart-3846fa28-2bb7-448e-a39f-080b28c9255f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3797832689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3797832689
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2613723216
Short name T897
Test name
Test status
Simulation time 113843711 ps
CPU time 0.75 seconds
Started Jun 27 04:23:24 PM PDT 24
Finished Jun 27 04:23:37 PM PDT 24
Peak memory 195672 kb
Host smart-7ccd5c5f-a792-4801-a78a-87cbe2d44f08
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613723216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2613723216
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3483629764
Short name T877
Test name
Test status
Simulation time 106775586 ps
CPU time 1.34 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 196700 kb
Host smart-f7b2c68c-68a5-44d1-89d5-6943dc9ab411
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3483629764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3483629764
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3350747428
Short name T913
Test name
Test status
Simulation time 369113205 ps
CPU time 1.2 seconds
Started Jun 27 04:23:36 PM PDT 24
Finished Jun 27 04:23:52 PM PDT 24
Peak memory 198128 kb
Host smart-ad879dd7-0cae-4709-9a1d-12d48d5573d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350747428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3350747428
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1199146941
Short name T886
Test name
Test status
Simulation time 235964249 ps
CPU time 1.17 seconds
Started Jun 27 04:19:25 PM PDT 24
Finished Jun 27 04:19:28 PM PDT 24
Peak memory 198320 kb
Host smart-cab06b53-231b-4e6b-b925-8e2014480d5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1199146941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1199146941
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.963834626
Short name T863
Test name
Test status
Simulation time 162227199 ps
CPU time 0.94 seconds
Started Jun 27 04:20:56 PM PDT 24
Finished Jun 27 04:20:58 PM PDT 24
Peak memory 198428 kb
Host smart-ccdb0ec7-220d-4f07-84c5-b1a6f3b5460d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963834626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.963834626
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.485148605
Short name T859
Test name
Test status
Simulation time 78552710 ps
CPU time 1.11 seconds
Started Jun 27 04:21:44 PM PDT 24
Finished Jun 27 04:21:46 PM PDT 24
Peak memory 196056 kb
Host smart-7f0f4777-f802-4141-bdbe-d78f6439194c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=485148605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.485148605
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1732267627
Short name T887
Test name
Test status
Simulation time 48081138 ps
CPU time 1.13 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:48 PM PDT 24
Peak memory 196868 kb
Host smart-d5694733-c2d6-4885-aa36-a1c557aef9b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732267627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1732267627
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.319567004
Short name T939
Test name
Test status
Simulation time 171310992 ps
CPU time 1.31 seconds
Started Jun 27 04:20:10 PM PDT 24
Finished Jun 27 04:20:13 PM PDT 24
Peak memory 197108 kb
Host smart-efb4fdd3-ff96-4c13-8753-d296cdd24a7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=319567004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.319567004
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.569478204
Short name T895
Test name
Test status
Simulation time 65661372 ps
CPU time 1.06 seconds
Started Jun 27 04:23:27 PM PDT 24
Finished Jun 27 04:23:41 PM PDT 24
Peak memory 197432 kb
Host smart-286ff7df-170e-4c47-b8df-8c8313e8f43f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569478204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.569478204
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1343205843
Short name T865
Test name
Test status
Simulation time 213723630 ps
CPU time 1.02 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 197508 kb
Host smart-64505239-d177-4506-8b7f-3fd6f6143e84
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1343205843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1343205843
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2456899480
Short name T889
Test name
Test status
Simulation time 53115678 ps
CPU time 1.14 seconds
Started Jun 27 04:20:21 PM PDT 24
Finished Jun 27 04:20:24 PM PDT 24
Peak memory 196924 kb
Host smart-0738663b-87c6-4ebd-a43d-8390f7ac2fab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456899480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2456899480
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.185176180
Short name T921
Test name
Test status
Simulation time 53473414 ps
CPU time 1.34 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:22:58 PM PDT 24
Peak memory 197172 kb
Host smart-4ff0b50c-147d-4376-8a01-629a3c2f16d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=185176180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.185176180
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4268443937
Short name T881
Test name
Test status
Simulation time 45423471 ps
CPU time 1.37 seconds
Started Jun 27 04:20:00 PM PDT 24
Finished Jun 27 04:20:02 PM PDT 24
Peak memory 197896 kb
Host smart-641ad253-e85a-43f2-9f92-cd018ce0a06e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268443937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4268443937
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3697565096
Short name T898
Test name
Test status
Simulation time 243077482 ps
CPU time 1.17 seconds
Started Jun 27 04:20:06 PM PDT 24
Finished Jun 27 04:20:09 PM PDT 24
Peak memory 196568 kb
Host smart-4d108fe7-a1e4-42dd-aa4a-7f31873a3be4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3697565096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3697565096
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1401093020
Short name T922
Test name
Test status
Simulation time 67219187 ps
CPU time 1 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:27 PM PDT 24
Peak memory 196660 kb
Host smart-6ae0224c-d530-46bc-ac04-a7676a7698fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401093020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1401093020
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4259479169
Short name T931
Test name
Test status
Simulation time 184711348 ps
CPU time 1.24 seconds
Started Jun 27 04:23:24 PM PDT 24
Finished Jun 27 04:23:37 PM PDT 24
Peak memory 198284 kb
Host smart-203393ae-97e7-4e16-9cb1-320288971b52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4259479169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4259479169
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2516679313
Short name T857
Test name
Test status
Simulation time 107324464 ps
CPU time 1.18 seconds
Started Jun 27 04:19:53 PM PDT 24
Finished Jun 27 04:19:55 PM PDT 24
Peak memory 196880 kb
Host smart-ce332dff-b6d6-4bf8-b572-7a866cde79e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516679313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2516679313
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.714122490
Short name T946
Test name
Test status
Simulation time 81723912 ps
CPU time 1.43 seconds
Started Jun 27 04:20:05 PM PDT 24
Finished Jun 27 04:20:07 PM PDT 24
Peak memory 197332 kb
Host smart-bd60943a-175c-43e8-af62-f9a4af7ae480
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=714122490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.714122490
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2538266488
Short name T912
Test name
Test status
Simulation time 263140475 ps
CPU time 1.14 seconds
Started Jun 27 04:21:19 PM PDT 24
Finished Jun 27 04:21:21 PM PDT 24
Peak memory 198276 kb
Host smart-18ae2df9-a612-4631-acca-e636bb463273
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538266488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2538266488
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1411022168
Short name T909
Test name
Test status
Simulation time 38634897 ps
CPU time 0.93 seconds
Started Jun 27 04:21:42 PM PDT 24
Finished Jun 27 04:21:44 PM PDT 24
Peak memory 196916 kb
Host smart-98e5042e-576e-46ad-a753-e6839cc4c057
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1411022168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1411022168
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2639259360
Short name T847
Test name
Test status
Simulation time 68192578 ps
CPU time 0.76 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 195352 kb
Host smart-5068bd52-18a2-4ad4-bb6d-202942c83918
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639259360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2639259360
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3718718435
Short name T935
Test name
Test status
Simulation time 29852431 ps
CPU time 0.88 seconds
Started Jun 27 04:23:26 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 196516 kb
Host smart-79ee221d-c531-4c4f-9b40-0391b0f20030
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3718718435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3718718435
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.815738759
Short name T919
Test name
Test status
Simulation time 623510140 ps
CPU time 1.07 seconds
Started Jun 27 04:23:25 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 196520 kb
Host smart-c7c4722e-881f-4358-af3a-b8abc30ebd2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815738759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.815738759
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.755378159
Short name T916
Test name
Test status
Simulation time 27001157 ps
CPU time 0.74 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:26 PM PDT 24
Peak memory 194712 kb
Host smart-bcbafadc-38a0-4e08-be56-a57aba09bb5a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=755378159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.755378159
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3753827591
Short name T890
Test name
Test status
Simulation time 58179902 ps
CPU time 1.48 seconds
Started Jun 27 04:19:42 PM PDT 24
Finished Jun 27 04:19:45 PM PDT 24
Peak memory 196976 kb
Host smart-b75058d4-0aa7-49f5-8e50-e6fca7bcc77b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753827591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3753827591
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1421322575
Short name T870
Test name
Test status
Simulation time 48575206 ps
CPU time 0.96 seconds
Started Jun 27 04:20:21 PM PDT 24
Finished Jun 27 04:20:24 PM PDT 24
Peak memory 198416 kb
Host smart-df3b501f-6a42-4444-b4e3-c94d5dcf86a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1421322575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1421322575
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3197684601
Short name T875
Test name
Test status
Simulation time 192238007 ps
CPU time 1.11 seconds
Started Jun 27 04:20:34 PM PDT 24
Finished Jun 27 04:20:36 PM PDT 24
Peak memory 197148 kb
Host smart-4bcbc93d-37cc-44a8-a7a4-604b131ebfbe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197684601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3197684601
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3261910424
Short name T900
Test name
Test status
Simulation time 142083190 ps
CPU time 0.98 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 195524 kb
Host smart-4de80701-8f69-41ba-af53-07ba376f6d0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3261910424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3261910424
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.429601654
Short name T904
Test name
Test status
Simulation time 85571199 ps
CPU time 1.47 seconds
Started Jun 27 04:21:52 PM PDT 24
Finished Jun 27 04:21:55 PM PDT 24
Peak memory 197712 kb
Host smart-a475798c-3cb2-414f-9125-caf686df1b4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429601654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.429601654
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3577225985
Short name T905
Test name
Test status
Simulation time 24956892 ps
CPU time 0.77 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 195448 kb
Host smart-b50220ba-6a52-41a6-b7e1-c8d1932f093c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3577225985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3577225985
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1220080499
Short name T851
Test name
Test status
Simulation time 199930296 ps
CPU time 1.4 seconds
Started Jun 27 04:22:39 PM PDT 24
Finished Jun 27 04:22:41 PM PDT 24
Peak memory 196632 kb
Host smart-8b632dd0-054e-4ff6-85f4-8f58a3176c05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220080499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1220080499
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1951408223
Short name T892
Test name
Test status
Simulation time 120957585 ps
CPU time 0.72 seconds
Started Jun 27 04:23:26 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 195404 kb
Host smart-5bd8bce8-9661-405f-b7da-c9ff58e1d76d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1951408223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1951408223
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3012356122
Short name T936
Test name
Test status
Simulation time 324328550 ps
CPU time 1.29 seconds
Started Jun 27 04:20:54 PM PDT 24
Finished Jun 27 04:20:56 PM PDT 24
Peak memory 197656 kb
Host smart-c8604ab1-d5f4-4c08-9649-e0b39990f3b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012356122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3012356122
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2658037414
Short name T938
Test name
Test status
Simulation time 178912928 ps
CPU time 1.17 seconds
Started Jun 27 04:23:38 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 195756 kb
Host smart-15d0d858-f9b9-4e39-a722-e777ce55a598
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2658037414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2658037414
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3644107039
Short name T940
Test name
Test status
Simulation time 285585762 ps
CPU time 1.2 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:22:58 PM PDT 24
Peak memory 196864 kb
Host smart-89ae7e73-08df-4454-ae44-d017051e3894
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644107039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3644107039
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1570769541
Short name T876
Test name
Test status
Simulation time 234271194 ps
CPU time 1.2 seconds
Started Jun 27 04:22:39 PM PDT 24
Finished Jun 27 04:22:41 PM PDT 24
Peak memory 197972 kb
Host smart-6eea2e69-fc94-4dbb-bc26-939c8644b35c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1570769541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1570769541
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702732767
Short name T878
Test name
Test status
Simulation time 188495674 ps
CPU time 1.04 seconds
Started Jun 27 04:22:38 PM PDT 24
Finished Jun 27 04:22:40 PM PDT 24
Peak memory 195808 kb
Host smart-0feb7c26-89dd-4b9a-bb2c-a55e70ccdb1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702732767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1702732767
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2659201029
Short name T858
Test name
Test status
Simulation time 285872726 ps
CPU time 1.12 seconds
Started Jun 27 04:20:37 PM PDT 24
Finished Jun 27 04:20:41 PM PDT 24
Peak memory 197768 kb
Host smart-eb16cfc3-090c-4ac3-8c34-ddc60fc89355
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2659201029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2659201029
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3334385613
Short name T928
Test name
Test status
Simulation time 839905082 ps
CPU time 1.26 seconds
Started Jun 27 04:20:15 PM PDT 24
Finished Jun 27 04:20:18 PM PDT 24
Peak memory 196784 kb
Host smart-64454111-2e8a-4bf5-af59-c83eccc040d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334385613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3334385613
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2381799089
Short name T850
Test name
Test status
Simulation time 172486156 ps
CPU time 0.97 seconds
Started Jun 27 04:20:54 PM PDT 24
Finished Jun 27 04:20:56 PM PDT 24
Peak memory 197604 kb
Host smart-2b26e14f-c33e-4cf5-922b-15ca350e111d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2381799089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2381799089
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.819634300
Short name T888
Test name
Test status
Simulation time 90783599 ps
CPU time 0.81 seconds
Started Jun 27 04:23:17 PM PDT 24
Finished Jun 27 04:23:27 PM PDT 24
Peak memory 197896 kb
Host smart-52431561-f5db-4a39-bcf1-7dbdda6f8c2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819634300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.819634300
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2554910119
Short name T920
Test name
Test status
Simulation time 109378031 ps
CPU time 1.01 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 195932 kb
Host smart-56ceff56-380c-4227-afff-fc516aa7910e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2554910119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2554910119
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1940258802
Short name T944
Test name
Test status
Simulation time 83924276 ps
CPU time 0.81 seconds
Started Jun 27 04:19:45 PM PDT 24
Finished Jun 27 04:19:47 PM PDT 24
Peak memory 196144 kb
Host smart-60233544-d980-456d-bb3e-6b7f53c23958
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940258802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1940258802
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3663112754
Short name T907
Test name
Test status
Simulation time 175647845 ps
CPU time 1.22 seconds
Started Jun 27 04:21:52 PM PDT 24
Finished Jun 27 04:21:55 PM PDT 24
Peak memory 196804 kb
Host smart-0638aa7c-1b58-4946-8926-ada187ddbc7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3663112754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3663112754
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3334783777
Short name T866
Test name
Test status
Simulation time 158522247 ps
CPU time 1.14 seconds
Started Jun 27 04:20:56 PM PDT 24
Finished Jun 27 04:20:58 PM PDT 24
Peak memory 196100 kb
Host smart-88462ee0-e5ee-473d-bbb5-4623cab71900
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334783777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3334783777
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1713575417
Short name T908
Test name
Test status
Simulation time 42112963 ps
CPU time 0.9 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:22:46 PM PDT 24
Peak memory 194512 kb
Host smart-2e32a96e-2e1c-434c-b597-6bfb14e3964a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1713575417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1713575417
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.517782910
Short name T899
Test name
Test status
Simulation time 60831874 ps
CPU time 1.03 seconds
Started Jun 27 04:22:39 PM PDT 24
Finished Jun 27 04:22:42 PM PDT 24
Peak memory 196520 kb
Host smart-fd47fe88-6789-4408-97bf-303bc4ff8717
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517782910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.517782910
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.489438199
Short name T894
Test name
Test status
Simulation time 59973061 ps
CPU time 0.83 seconds
Started Jun 27 04:21:59 PM PDT 24
Finished Jun 27 04:22:01 PM PDT 24
Peak memory 195804 kb
Host smart-6030ddc6-8742-4f33-b3c6-e0a3e5e0f268
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=489438199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.489438199
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1107098461
Short name T864
Test name
Test status
Simulation time 60973302 ps
CPU time 1.14 seconds
Started Jun 27 04:22:38 PM PDT 24
Finished Jun 27 04:22:40 PM PDT 24
Peak memory 195960 kb
Host smart-8cd48163-e96a-46ac-8da5-a027f2f3cc03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107098461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1107098461
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.871083904
Short name T932
Test name
Test status
Simulation time 35430009 ps
CPU time 0.99 seconds
Started Jun 27 04:23:33 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 196456 kb
Host smart-67654667-e4bc-4226-9714-66c2e4867b3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=871083904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.871083904
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.137796963
Short name T885
Test name
Test status
Simulation time 59668157 ps
CPU time 0.97 seconds
Started Jun 27 04:20:33 PM PDT 24
Finished Jun 27 04:20:35 PM PDT 24
Peak memory 196248 kb
Host smart-89742c3e-c839-476f-89c3-1a8fd4705521
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137796963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.137796963
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.472582277
Short name T868
Test name
Test status
Simulation time 110244921 ps
CPU time 1.21 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 197240 kb
Host smart-c2ffd4ec-02b0-4b96-ac1d-875984b0b22a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=472582277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.472582277
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3884752486
Short name T915
Test name
Test status
Simulation time 339225584 ps
CPU time 1.17 seconds
Started Jun 27 04:23:16 PM PDT 24
Finished Jun 27 04:23:25 PM PDT 24
Peak memory 196716 kb
Host smart-a777a049-6256-4cc6-98de-d8da3348e657
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884752486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3884752486
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.422416976
Short name T871
Test name
Test status
Simulation time 34186004 ps
CPU time 1.01 seconds
Started Jun 27 04:23:26 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 196684 kb
Host smart-cb7a829f-85fe-42c6-b263-f4497f3f2719
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=422416976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.422416976
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2163160991
Short name T869
Test name
Test status
Simulation time 167148410 ps
CPU time 1.24 seconds
Started Jun 27 04:20:15 PM PDT 24
Finished Jun 27 04:20:18 PM PDT 24
Peak memory 196856 kb
Host smart-1d7d9200-0e00-4525-89e8-cbcb36eef01b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163160991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2163160991
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4221449390
Short name T945
Test name
Test status
Simulation time 24968405 ps
CPU time 0.93 seconds
Started Jun 27 04:21:26 PM PDT 24
Finished Jun 27 04:21:28 PM PDT 24
Peak memory 196536 kb
Host smart-2a5d5406-d4d7-481f-bebd-13c12183e3bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4221449390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4221449390
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3725836060
Short name T874
Test name
Test status
Simulation time 67365002 ps
CPU time 0.84 seconds
Started Jun 27 04:23:49 PM PDT 24
Finished Jun 27 04:24:02 PM PDT 24
Peak memory 196548 kb
Host smart-1a6368ce-426f-4a41-9011-d3fcd12e96c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725836060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3725836060
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.17355049
Short name T924
Test name
Test status
Simulation time 198738445 ps
CPU time 1 seconds
Started Jun 27 04:19:48 PM PDT 24
Finished Jun 27 04:19:49 PM PDT 24
Peak memory 196896 kb
Host smart-96cf7272-b0e8-49c8-8249-ce44ee876a33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=17355049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.17355049
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.804754229
Short name T923
Test name
Test status
Simulation time 156476927 ps
CPU time 1.12 seconds
Started Jun 27 04:20:23 PM PDT 24
Finished Jun 27 04:20:26 PM PDT 24
Peak memory 196936 kb
Host smart-18bcb31d-9c6d-4a83-8b90-5af8fbd30b3f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804754229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.804754229
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.541847946
Short name T862
Test name
Test status
Simulation time 280728301 ps
CPU time 1.13 seconds
Started Jun 27 04:20:56 PM PDT 24
Finished Jun 27 04:20:59 PM PDT 24
Peak memory 196292 kb
Host smart-aa5e2195-5432-4e80-89b7-1ba645b185c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=541847946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.541847946
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3054813279
Short name T943
Test name
Test status
Simulation time 50076765 ps
CPU time 1.06 seconds
Started Jun 27 04:22:39 PM PDT 24
Finished Jun 27 04:22:42 PM PDT 24
Peak memory 195932 kb
Host smart-43c56e8a-183d-4eda-9e2b-d153f09c7fc2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054813279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3054813279
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.83510095
Short name T918
Test name
Test status
Simulation time 83180541 ps
CPU time 0.87 seconds
Started Jun 27 04:23:30 PM PDT 24
Finished Jun 27 04:23:44 PM PDT 24
Peak memory 196820 kb
Host smart-f95d21f3-07ed-41df-a964-539b15a0a2ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=83510095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.83510095
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1366555848
Short name T925
Test name
Test status
Simulation time 77695074 ps
CPU time 0.69 seconds
Started Jun 27 04:22:53 PM PDT 24
Finished Jun 27 04:22:55 PM PDT 24
Peak memory 195944 kb
Host smart-ebc184aa-5eba-4371-b8aa-947caa4b6d9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366555848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1366555848
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3445466608
Short name T941
Test name
Test status
Simulation time 78049368 ps
CPU time 1.41 seconds
Started Jun 27 04:20:23 PM PDT 24
Finished Jun 27 04:20:26 PM PDT 24
Peak memory 197408 kb
Host smart-1dc5c0c1-42c9-4f06-85b5-3aa609350e30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3445466608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3445466608
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2874908127
Short name T872
Test name
Test status
Simulation time 231789685 ps
CPU time 1.07 seconds
Started Jun 27 04:20:15 PM PDT 24
Finished Jun 27 04:20:17 PM PDT 24
Peak memory 196928 kb
Host smart-42fce51a-7049-43c2-b67c-1201edc40317
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874908127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2874908127
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3288794959
Short name T910
Test name
Test status
Simulation time 135089876 ps
CPU time 0.95 seconds
Started Jun 27 04:21:18 PM PDT 24
Finished Jun 27 04:21:19 PM PDT 24
Peak memory 196876 kb
Host smart-ebbcdcce-f765-4eef-b053-4c4661fbb9de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3288794959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3288794959
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4039442798
Short name T883
Test name
Test status
Simulation time 47683758 ps
CPU time 1.22 seconds
Started Jun 27 04:23:30 PM PDT 24
Finished Jun 27 04:23:45 PM PDT 24
Peak memory 195936 kb
Host smart-e2ab25cb-977d-458f-a336-a59faf51820a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039442798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4039442798
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3263029538
Short name T854
Test name
Test status
Simulation time 56097901 ps
CPU time 0.94 seconds
Started Jun 27 04:22:53 PM PDT 24
Finished Jun 27 04:22:55 PM PDT 24
Peak memory 195540 kb
Host smart-d1faa605-3eba-469e-b75c-1cf20ef5a824
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3263029538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3263029538
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1078146835
Short name T855
Test name
Test status
Simulation time 135917244 ps
CPU time 1.01 seconds
Started Jun 27 04:23:35 PM PDT 24
Finished Jun 27 04:23:51 PM PDT 24
Peak memory 196576 kb
Host smart-aca63d7b-6c4b-4de4-847f-905aa8025bc1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078146835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1078146835
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1389350813
Short name T896
Test name
Test status
Simulation time 70393400 ps
CPU time 0.92 seconds
Started Jun 27 04:23:26 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 196796 kb
Host smart-23a13ac6-6bf1-4830-9910-51676247bde6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1389350813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1389350813
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.220505235
Short name T930
Test name
Test status
Simulation time 42856962 ps
CPU time 0.86 seconds
Started Jun 27 04:22:39 PM PDT 24
Finished Jun 27 04:22:41 PM PDT 24
Peak memory 195408 kb
Host smart-e358ec5f-39b1-4764-b2d8-87e8069b7254
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220505235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.220505235
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2509645346
Short name T917
Test name
Test status
Simulation time 249791586 ps
CPU time 1.13 seconds
Started Jun 27 04:23:18 PM PDT 24
Finished Jun 27 04:23:29 PM PDT 24
Peak memory 198056 kb
Host smart-2f038a6a-73bb-4dc3-8fcd-1cdf6e008aef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2509645346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2509645346
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1765784973
Short name T852
Test name
Test status
Simulation time 111046562 ps
CPU time 0.87 seconds
Started Jun 27 04:20:16 PM PDT 24
Finished Jun 27 04:20:19 PM PDT 24
Peak memory 195756 kb
Host smart-a1a3042a-75e1-48eb-b5aa-982b22f11792
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765784973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1765784973
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2877914033
Short name T901
Test name
Test status
Simulation time 41031371 ps
CPU time 1.15 seconds
Started Jun 27 04:20:15 PM PDT 24
Finished Jun 27 04:20:18 PM PDT 24
Peak memory 196816 kb
Host smart-161a684b-9fd6-40aa-a11e-0f7fb245697f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2877914033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2877914033
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3639611059
Short name T879
Test name
Test status
Simulation time 133729509 ps
CPU time 1.01 seconds
Started Jun 27 04:22:53 PM PDT 24
Finished Jun 27 04:22:55 PM PDT 24
Peak memory 198252 kb
Host smart-0d3c3b49-5804-4f42-8e13-4046bfc7da66
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639611059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3639611059
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.859334199
Short name T853
Test name
Test status
Simulation time 142730923 ps
CPU time 1.31 seconds
Started Jun 27 04:23:25 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 198008 kb
Host smart-e9bf525d-ebe1-46c6-9800-81ed7027fd79
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=859334199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.859334199
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3898423681
Short name T849
Test name
Test status
Simulation time 143442074 ps
CPU time 0.93 seconds
Started Jun 27 04:23:26 PM PDT 24
Finished Jun 27 04:23:39 PM PDT 24
Peak memory 198112 kb
Host smart-a04abf1b-96c7-437d-b295-bc156d4302a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898423681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3898423681
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2938267437
Short name T884
Test name
Test status
Simulation time 80352168 ps
CPU time 1.2 seconds
Started Jun 27 04:23:38 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 196444 kb
Host smart-7e51fcd1-27ee-4b32-8b18-cf52186b5bd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2938267437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2938267437
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1582565781
Short name T891
Test name
Test status
Simulation time 260602898 ps
CPU time 1.06 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:22:57 PM PDT 24
Peak memory 196796 kb
Host smart-91a4b460-6066-4623-8e07-1f3377096d85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582565781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1582565781
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1476140605
Short name T926
Test name
Test status
Simulation time 59428889 ps
CPU time 1.27 seconds
Started Jun 27 04:22:27 PM PDT 24
Finished Jun 27 04:22:30 PM PDT 24
Peak memory 196944 kb
Host smart-b9253c4a-caf9-4dfd-bfd9-1ab1c6f46a15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1476140605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1476140605
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2786294920
Short name T906
Test name
Test status
Simulation time 52121595 ps
CPU time 1.5 seconds
Started Jun 27 04:19:52 PM PDT 24
Finished Jun 27 04:19:55 PM PDT 24
Peak memory 198292 kb
Host smart-b1ff5e25-35bf-4fac-87b3-f800bc97e5dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786294920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2786294920
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.12788398
Short name T933
Test name
Test status
Simulation time 51691703 ps
CPU time 1.15 seconds
Started Jun 27 04:23:38 PM PDT 24
Finished Jun 27 04:23:55 PM PDT 24
Peak memory 196552 kb
Host smart-6d0cfca9-6493-47bd-b229-05d8b669fb05
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=12788398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.12788398
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2157736053
Short name T902
Test name
Test status
Simulation time 61683269 ps
CPU time 1.3 seconds
Started Jun 27 04:19:26 PM PDT 24
Finished Jun 27 04:19:28 PM PDT 24
Peak memory 197284 kb
Host smart-d8fdb3b2-5f6b-4218-bb10-c0edb6e64ecd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157736053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2157736053
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.600955163
Short name T880
Test name
Test status
Simulation time 65703841 ps
CPU time 1.27 seconds
Started Jun 27 04:19:52 PM PDT 24
Finished Jun 27 04:19:55 PM PDT 24
Peak memory 196824 kb
Host smart-ecac3f8a-6393-4500-ae3f-c1257159ffde
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=600955163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.600955163
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4199563781
Short name T848
Test name
Test status
Simulation time 69697776 ps
CPU time 1.08 seconds
Started Jun 27 04:20:10 PM PDT 24
Finished Jun 27 04:20:13 PM PDT 24
Peak memory 196076 kb
Host smart-31df15ee-5dea-4361-97d2-6bded945050c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199563781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4199563781
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2873558425
Short name T882
Test name
Test status
Simulation time 33604521 ps
CPU time 0.9 seconds
Started Jun 27 04:23:34 PM PDT 24
Finished Jun 27 04:23:49 PM PDT 24
Peak memory 196684 kb
Host smart-7f2ad9a2-7828-4a76-b329-7771358b9e40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2873558425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2873558425
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3393754572
Short name T927
Test name
Test status
Simulation time 89356928 ps
CPU time 0.9 seconds
Started Jun 27 04:21:18 PM PDT 24
Finished Jun 27 04:21:20 PM PDT 24
Peak memory 196872 kb
Host smart-e66cd4ea-57ed-4789-a8d7-be42e2b9d492
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393754572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3393754572
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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