Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3129007	1			T21	91		T22	1		T23	120
all_pins[1]	3129007	1			T21	91		T22	1		T23	120
all_pins[2]	3129007	1			T21	91		T22	1		T23	120
all_pins[3]	3129007	1			T21	91		T22	1		T23	120
all_pins[4]	3129007	1			T21	91		T22	1		T23	120
all_pins[5]	3129007	1			T21	91		T22	1		T23	120
all_pins[6]	3129007	1			T21	91		T22	1		T23	120
all_pins[7]	3129007	1			T21	91		T22	1		T23	120
all_pins[8]	3129007	1			T21	91		T22	1		T23	120
all_pins[9]	3129007	1			T21	91		T22	1		T23	120
all_pins[10]	3129007	1			T21	91		T22	1		T23	120
all_pins[11]	3129007	1			T21	91		T22	1		T23	120
all_pins[12]	3129007	1			T21	91		T22	1		T23	120
all_pins[13]	3129007	1			T21	91		T22	1		T23	120
all_pins[14]	3129007	1			T21	91		T22	1		T23	120
all_pins[15]	3129007	1			T21	91		T22	1		T23	120
all_pins[16]	3129007	1			T21	91		T22	1		T23	120
all_pins[17]	3129007	1			T21	91		T22	1		T23	120
all_pins[18]	3129007	1			T21	91		T22	1		T23	120
all_pins[19]	3129007	1			T21	91		T22	1		T23	120
all_pins[20]	3129007	1			T21	91		T22	1		T23	120
all_pins[21]	3129007	1			T21	91		T22	1		T23	120
all_pins[22]	3129007	1			T21	91		T22	1		T23	120
all_pins[23]	3129007	1			T21	91		T22	1		T23	120
all_pins[24]	3129007	1			T21	91		T22	1		T23	120
all_pins[25]	3129007	1			T21	91		T22	1		T23	120
all_pins[26]	3129007	1			T21	91		T22	1		T23	120
all_pins[27]	3129007	1			T21	91		T22	1		T23	120
all_pins[28]	3129007	1			T21	91		T22	1		T23	120
all_pins[29]	3129007	1			T21	91		T22	1		T23	120
all_pins[30]	3129007	1			T21	91		T22	1		T23	120
all_pins[31]	3129007	1			T21	91		T22	1		T23	120

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	62218169	1			T21	2380		T22	32		T23	1996
values[0x1]	37910055	1			T21	532		T23	1844		T24	637
transitions[0x0=>0x1]	22714025	1			T21	343		T23	937		T24	327
transitions[0x1=>0x0]	22713866	1			T21	343		T23	936		T24	326

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1941640	1			T21	75		T22	1		T23	59
all_pins[0]	values[0x1]	1187367	1			T21	16		T23	61		T24	22
all_pins[0]	transitions[0x0=>0x1]	734067	1			T21	14		T23	32		T24	10
all_pins[0]	transitions[0x1=>0x0]	732541	1			T21	7		T23	34		T24	10
all_pins[1]	values[0x0]	1943937	1			T21	66		T22	1		T23	55
all_pins[1]	values[0x1]	1185070	1			T21	25		T23	65		T24	27
all_pins[1]	transitions[0x0=>0x1]	708102	1			T21	15		T23	31		T24	13
all_pins[1]	transitions[0x1=>0x0]	710399	1			T21	6		T23	27		T24	8
all_pins[2]	values[0x0]	1943046	1			T21	82		T22	1		T23	68
all_pins[2]	values[0x1]	1185961	1			T21	9		T23	52		T24	16
all_pins[2]	transitions[0x0=>0x1]	709878	1			T21	9		T23	25		T24	6
all_pins[2]	transitions[0x1=>0x0]	708987	1			T21	25		T23	38		T24	17
all_pins[3]	values[0x0]	1944666	1			T21	83		T22	1		T23	59
all_pins[3]	values[0x1]	1184341	1			T21	8		T23	61		T24	16
all_pins[3]	transitions[0x0=>0x1]	707531	1			T21	6		T23	37		T24	13
all_pins[3]	transitions[0x1=>0x0]	709151	1			T21	7		T23	28		T24	13
all_pins[4]	values[0x0]	1950725	1			T21	62		T22	1		T23	63
all_pins[4]	values[0x1]	1178282	1			T21	29		T23	57		T24	19
all_pins[4]	transitions[0x0=>0x1]	705037	1			T21	22		T23	24		T24	10
all_pins[4]	transitions[0x1=>0x0]	711096	1			T21	1		T23	28		T24	7
all_pins[5]	values[0x0]	1945341	1			T21	84		T22	1		T23	58
all_pins[5]	values[0x1]	1183666	1			T21	7		T23	62		T24	17
all_pins[5]	transitions[0x0=>0x1]	710758	1			T23	36		T24	9		T26	12
all_pins[5]	transitions[0x1=>0x0]	705374	1			T21	22		T23	31		T24	11
all_pins[6]	values[0x0]	1947696	1			T21	67		T22	1		T23	60
all_pins[6]	values[0x1]	1181311	1			T21	24		T23	60		T24	21
all_pins[6]	transitions[0x0=>0x1]	706458	1			T21	24		T23	28		T24	11
all_pins[6]	transitions[0x1=>0x0]	708813	1			T21	7		T23	30		T24	7
all_pins[7]	values[0x0]	1944634	1			T21	77		T22	1		T23	59
all_pins[7]	values[0x1]	1184373	1			T21	14		T23	61		T24	14
all_pins[7]	transitions[0x0=>0x1]	709313	1			T21	11		T23	27		T24	6
all_pins[7]	transitions[0x1=>0x0]	706251	1			T21	21		T23	26		T24	13
all_pins[8]	values[0x0]	1945661	1			T21	80		T22	1		T23	64
all_pins[8]	values[0x1]	1183346	1			T21	11		T23	56		T24	20
all_pins[8]	transitions[0x0=>0x1]	707874	1			T21	7		T23	28		T24	14
all_pins[8]	transitions[0x1=>0x0]	708901	1			T21	10		T23	33		T24	8
all_pins[9]	values[0x0]	1943477	1			T21	72		T22	1		T23	66
all_pins[9]	values[0x1]	1185530	1			T21	19		T23	54		T24	13
all_pins[9]	transitions[0x0=>0x1]	713089	1			T21	15		T23	30		T24	7
all_pins[9]	transitions[0x1=>0x0]	710905	1			T21	7		T23	32		T24	14
all_pins[10]	values[0x0]	1945720	1			T21	77		T22	1		T23	64
all_pins[10]	values[0x1]	1183287	1			T21	14		T23	56		T24	15
all_pins[10]	transitions[0x0=>0x1]	707193	1			T21	3		T23	33		T24	11
all_pins[10]	transitions[0x1=>0x0]	709436	1			T21	8		T23	31		T24	9
all_pins[11]	values[0x0]	1944559	1			T21	73		T22	1		T23	69
all_pins[11]	values[0x1]	1184448	1			T21	18		T23	51		T24	16
all_pins[11]	transitions[0x0=>0x1]	707672	1			T21	16		T23	29		T24	12
all_pins[11]	transitions[0x1=>0x0]	706511	1			T21	12		T23	34		T24	11
all_pins[12]	values[0x0]	1941828	1			T21	64		T22	1		T23	54
all_pins[12]	values[0x1]	1187179	1			T21	27		T23	66		T24	18
all_pins[12]	transitions[0x0=>0x1]	712215	1			T21	19		T23	37		T24	10
all_pins[12]	transitions[0x1=>0x0]	709484	1			T21	10		T23	22		T24	8
all_pins[13]	values[0x0]	1947029	1			T21	70		T22	1		T23	63
all_pins[13]	values[0x1]	1181978	1			T21	21		T23	57		T24	23
all_pins[13]	transitions[0x0=>0x1]	707637	1			T21	8		T23	24		T24	12
all_pins[13]	transitions[0x1=>0x0]	712838	1			T21	14		T23	33		T24	7
all_pins[14]	values[0x0]	1948337	1			T21	66		T22	1		T23	65
all_pins[14]	values[0x1]	1180670	1			T21	25		T23	55		T24	23
all_pins[14]	transitions[0x0=>0x1]	707223	1			T21	15		T23	27		T24	12
all_pins[14]	transitions[0x1=>0x0]	708531	1			T21	11		T23	29		T24	12
all_pins[15]	values[0x0]	1941831	1			T21	76		T22	1		T23	63
all_pins[15]	values[0x1]	1187176	1			T21	15		T23	57		T24	20
all_pins[15]	transitions[0x0=>0x1]	712830	1			T21	8		T23	29		T24	9
all_pins[15]	transitions[0x1=>0x0]	706324	1			T21	18		T23	27		T24	12
all_pins[16]	values[0x0]	1942368	1			T21	71		T22	1		T23	60
all_pins[16]	values[0x1]	1186639	1			T21	20		T23	60		T24	23
all_pins[16]	transitions[0x0=>0x1]	709702	1			T21	13		T23	30		T24	12
all_pins[16]	transitions[0x1=>0x0]	710239	1			T21	8		T23	27		T24	9
all_pins[17]	values[0x0]	1946957	1			T21	75		T22	1		T23	62
all_pins[17]	values[0x1]	1182050	1			T21	16		T23	58		T24	19
all_pins[17]	transitions[0x0=>0x1]	706757	1			T21	10		T23	25		T24	8
all_pins[17]	transitions[0x1=>0x0]	711346	1			T21	14		T23	27		T24	12
all_pins[18]	values[0x0]	1941780	1			T21	82		T22	1		T23	51
all_pins[18]	values[0x1]	1187227	1			T21	9		T23	69		T24	22
all_pins[18]	transitions[0x0=>0x1]	710310	1			T21	7		T23	37		T24	13
all_pins[18]	transitions[0x1=>0x0]	705133	1			T21	14		T23	26		T24	10
all_pins[19]	values[0x0]	1948763	1			T21	79		T22	1		T23	62
all_pins[19]	values[0x1]	1180244	1			T21	12		T23	58		T24	17
all_pins[19]	transitions[0x0=>0x1]	705927	1			T21	12		T23	19		T24	5
all_pins[19]	transitions[0x1=>0x0]	712910	1			T21	9		T23	30		T24	10
all_pins[20]	values[0x0]	1939295	1			T21	83		T22	1		T23	70
all_pins[20]	values[0x1]	1189712	1			T21	8		T23	50		T24	24
all_pins[20]	transitions[0x0=>0x1]	714284	1			T21	3		T23	26		T24	13
all_pins[20]	transitions[0x1=>0x0]	704816	1			T21	7		T23	34		T24	6
all_pins[21]	values[0x0]	1947291	1			T21	81		T22	1		T23	53
all_pins[21]	values[0x1]	1181716	1			T21	10		T23	67		T24	26
all_pins[21]	transitions[0x0=>0x1]	705403	1			T21	10		T23	38		T24	10
all_pins[21]	transitions[0x1=>0x0]	713399	1			T21	8		T23	21		T24	8
all_pins[22]	values[0x0]	1939956	1			T21	85		T22	1		T23	62
all_pins[22]	values[0x1]	1189051	1			T21	6		T23	58		T24	21
all_pins[22]	transitions[0x0=>0x1]	713484	1			T21	3		T23	31		T24	8
all_pins[22]	transitions[0x1=>0x0]	706149	1			T21	7		T23	40		T24	13
all_pins[23]	values[0x0]	1947477	1			T21	80		T22	1		T23	60
all_pins[23]	values[0x1]	1181530	1			T21	11		T23	60		T24	16
all_pins[23]	transitions[0x0=>0x1]	704243	1			T21	11		T23	34		T24	9
all_pins[23]	transitions[0x1=>0x0]	711764	1			T21	6		T23	32		T24	14
all_pins[24]	values[0x0]	1943476	1			T21	67		T22	1		T23	69
all_pins[24]	values[0x1]	1185531	1			T21	24		T23	51		T24	20
all_pins[24]	transitions[0x0=>0x1]	712234	1			T21	16		T23	27		T24	11
all_pins[24]	transitions[0x1=>0x0]	708233	1			T21	3		T23	36		T24	7
all_pins[25]	values[0x0]	1945184	1			T21	67		T22	1		T23	72
all_pins[25]	values[0x1]	1183823	1			T21	24		T23	48		T24	21
all_pins[25]	transitions[0x0=>0x1]	707925	1			T21	12		T23	22		T24	11
all_pins[25]	transitions[0x1=>0x0]	709633	1			T21	12		T23	25		T24	10
all_pins[26]	values[0x0]	1942749	1			T21	65		T22	1		T23	68
all_pins[26]	values[0x1]	1186258	1			T21	26		T23	52		T24	19
all_pins[26]	transitions[0x0=>0x1]	709784	1			T21	11		T23	28		T24	10
all_pins[26]	transitions[0x1=>0x0]	707349	1			T21	9		T23	24		T24	12
all_pins[27]	values[0x0]	1941576	1			T21	73		T22	1		T23	69
all_pins[27]	values[0x1]	1187431	1			T21	18		T23	51		T24	21
all_pins[27]	transitions[0x0=>0x1]	711859	1			T21	5		T23	24		T24	11
all_pins[27]	transitions[0x1=>0x0]	710686	1			T21	13		T23	25		T24	9
all_pins[28]	values[0x0]	1945560	1			T21	70		T22	1		T23	65
all_pins[28]	values[0x1]	1183447	1			T21	21		T23	55		T24	17
all_pins[28]	transitions[0x0=>0x1]	706324	1			T21	13		T23	27		T24	9
all_pins[28]	transitions[0x1=>0x0]	710308	1			T21	10		T23	23		T24	13
all_pins[29]	values[0x0]	1944679	1			T21	64		T22	1		T23	68
all_pins[29]	values[0x1]	1184328	1			T21	27		T23	52		T24	23
all_pins[29]	transitions[0x0=>0x1]	708823	1			T21	14		T23	32		T24	13
all_pins[29]	transitions[0x1=>0x0]	707942	1			T21	8		T23	35		T24	7
all_pins[30]	values[0x0]	1937924	1			T21	82		T22	1		T23	60
all_pins[30]	values[0x1]	1191083	1			T21	9		T23	60		T24	25
all_pins[30]	transitions[0x0=>0x1]	713380	1			T21	2		T23	31		T24	12
all_pins[30]	transitions[0x1=>0x0]	706625	1			T21	20		T23	23		T24	10
all_pins[31]	values[0x0]	1943007	1			T21	82		T22	1		T23	56
all_pins[31]	values[0x1]	1186000	1			T21	9		T23	64		T24	23
all_pins[31]	transitions[0x0=>0x1]	706709	1			T21	9		T23	29		T24	7
all_pins[31]	transitions[0x1=>0x0]	711792	1			T21	9		T23	25		T24	9