Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[1]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[2]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[3]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[4]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[5]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[6]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[7]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[8]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[9]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[10]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[11]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[12]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[13]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[14]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[15]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[16]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[17]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[18]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[19]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[20]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[21]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[22]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[23]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[24]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[25]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[26]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[27]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[28]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[29]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[30]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[31]	10923329	1			T21	184		T22	1		T23	1725

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

201694463

1

T21

2975

T22

32

T23

28196

auto[1]

147852065

1

T21

2913

T23

27004

T24

389649

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281780736

1

T21

5327

T22

32

T23

55200

auto[1]

67765792

1

T21

561

T25

10542

T27

5107

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261829812

1

T21

4450

T22

32

T23

55200

auto[1]

87716716

1

T21

1438

T25

10944

T27

5064

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	3976312	1			T21	78		T22	1		T23	849
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3134784	1			T21	57		T23	876		T24	13515
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1065293	1			T21	5		T25	176		T27	101
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1255811	1			T21	19		T25	171		T27	64
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	432997	1			T21	2		T12	13		T2	18
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1058132	1			T21	23		T25	168		T27	92
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	3976257	1			T21	76		T22	1		T23	893
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3139141	1			T21	69		T23	832		T24	12194
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1066088	1			T21	3		T25	175		T27	92
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1253693	1			T21	22		T25	162		T27	60
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	431375	1			T21	10		T1	1		T12	8
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1056775	1			T21	4		T25	178		T27	76
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	3978232	1			T21	98		T22	1		T23	940
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3138842	1			T21	58		T23	785		T24	13172
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1068873	1			T21	2		T25	154		T27	59
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1252915	1			T25	169		T27	98		T28	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	432366	1			T21	20		T12	13		T2	16
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1052101	1			T21	6		T25	146		T27	82
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	3992929	1			T21	103		T22	1		T23	828
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3130013	1			T21	31		T23	897		T24	12033
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1066442	1			T21	13		T25	166		T27	83
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1250898	1			T21	20		T25	157		T27	54
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	427461	1			T21	4		T1	1		T12	7
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1055586	1			T21	13		T25	178		T27	90
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	3988388	1			T21	27		T22	1		T23	827
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3133594	1			T21	95		T23	898		T24	11754
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1066688	1			T21	1		T25	171		T27	72
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1248917	1			T21	15		T25	178		T27	75
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	432086	1			T21	23		T2	12		T16	17
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1053656	1			T21	23		T25	174		T27	96
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	3994287	1			T21	105		T22	1		T23	855
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3124744	1			T21	42		T23	870		T24	11684
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1063510	1			T21	7		T25	153		T27	63
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1254340	1			T21	23		T25	156		T27	106
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	430695	1			T21	5		T12	11		T2	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1055753	1			T21	2		T25	180		T27	82
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	3986613	1			T21	56		T22	1		T23	972
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3132360	1			T21	96		T23	753		T24	12647
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1065852	1			T21	2		T25	138		T27	65
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1252457	1			T21	13		T25	193		T27	84
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	431943	1			T21	3		T1	5		T12	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1054104	1			T21	14		T25	190		T27	76
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	3984680	1			T21	92		T22	1		T23	929
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3138664	1			T21	38		T23	796		T24	12424
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1065383	1			T25	166		T27	90		T28	18
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1252543	1			T21	21		T25	160		T27	78
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	429493	1			T21	25		T1	4		T12	10
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1052566	1			T21	8		T25	195		T27	74
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	3978513	1			T21	107		T22	1		T23	947
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3132621	1			T21	48		T23	778		T24	12493
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1063543	1			T21	2		T25	204		T27	81
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1258138	1			T21	16		T25	151		T27	68
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	432117	1			T21	11		T12	15		T2	18
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1058397	1			T25	164		T27	84		T28	29
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	3974851	1			T21	72		T22	1		T23	883
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3136837	1			T21	47		T23	842		T24	12271
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1065094	1			T21	7		T25	154		T27	105
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1258312	1			T21	24		T25	182		T27	44
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	432815	1			T21	10		T1	1		T12	5
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1055420	1			T21	24		T25	162		T27	84
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	3972999	1			T21	55		T22	1		T23	904
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3137596	1			T21	73		T23	821		T24	12533
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1070512	1			T21	5		T25	170		T27	67
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1251633	1			T21	9		T25	202		T27	78
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	433194	1			T21	23		T1	1		T12	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1057395	1			T21	19		T25	154		T27	90
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	3961511	1			T21	75		T22	1		T23	931
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3149391	1			T21	56		T23	794		T24	12749
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1063905	1			T21	3		T25	135		T27	94
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1258164	1			T21	30		T25	190		T27	81
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	431587	1			T21	8		T1	4		T12	12
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1058771	1			T21	12		T25	162		T27	66
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	3969447	1			T21	38		T22	1		T23	894
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3146055	1			T21	74		T23	831		T24	12871
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1062905	1			T21	5		T25	166		T27	86
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1258603	1			T21	11		T25	168		T27	73
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	432771	1			T21	27		T1	5		T12	6
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1053548	1			T21	29		T25	191		T27	62
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	3981786	1			T21	114		T22	1		T23	784
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3140471	1			T21	36		T23	941		T24	12994
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1067877	1			T21	14		T25	150		T27	56
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1251533	1			T21	9		T25	184		T27	80
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	428647	1			T21	9		T12	6		T2	11
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1053015	1			T21	2		T25	155		T27	108
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	3984847	1			T21	45		T22	1		T23	932
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3124243	1			T21	75		T23	793		T24	11590
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1064623	1			T21	2		T25	178		T27	92
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1255927	1			T21	5		T25	156		T27	48
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	434586	1			T21	21		T1	1		T12	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1059103	1			T21	36		T25	171		T27	68
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	3977526	1			T21	80		T22	1		T23	947
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3135146	1			T21	64		T23	778		T24	13137
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1064713	1			T25	165		T27	66		T28	22
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1257302	1			T21	17		T25	164		T27	74
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	429795	1			T21	4		T1	1		T12	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1058847	1			T21	19		T25	156		T27	66
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	3988454	1			T21	79		T22	1		T23	967
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3132285	1			T21	58		T23	758		T24	11206
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1064312	1			T21	1		T25	190		T27	84
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1255338	1			T21	13		T25	166		T27	75
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	431109	1			T21	14		T12	11		T2	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1051831	1			T21	19		T25	146		T27	72
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	3988874	1			T21	77		T22	1		T23	818
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3132067	1			T21	69		T23	907		T24	12727
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1065574	1			T21	4		T25	136		T27	92
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1255567	1			T21	23		T25	192		T27	67
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	431816	1			T21	7		T1	1		T12	6
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1049431	1			T21	4		T25	168		T27	80
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	3988634	1			T21	72		T22	1		T23	890
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3130335	1			T21	53		T23	835		T24	12302
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1064127	1			T21	6		T25	159		T27	80
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1253587	1			T21	30		T25	162		T27	106
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	432397	1			T21	14		T1	1		T12	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1054249	1			T21	9		T25	158		T27	65
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	3989906	1			T21	68		T22	1		T23	833
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3128577	1			T21	77		T23	892		T24	12609
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1059976	1			T21	6		T25	132		T27	78
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1257620	1			T21	18		T25	218		T27	89
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	433201	1			T21	15		T1	1		T12	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1054049	1			T25	153		T27	90		T28	18
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	3986410	1			T21	56		T22	1		T23	796
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3129295	1			T21	62		T23	929		T24	12144
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1063971	1			T25	138		T27	76		T28	32
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1257256	1			T21	25		T25	194		T27	74
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	434061	1			T21	28		T1	5		T12	7
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1052336	1			T21	13		T25	170		T27	89
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	3978594	1			T21	78		T22	1		T23	868
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3144216	1			T21	83		T23	857		T24	12591
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1060597	1			T21	4		T25	142		T27	62
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1256062	1			T21	2		T25	180		T27	100
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	432253	1			T21	9		T1	6		T12	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1051607	1			T21	8		T25	191		T27	91
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	3996037	1			T21	71		T22	1		T23	852
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3126889	1			T21	65		T23	873		T24	12369
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1059419	1			T21	1		T25	148		T27	54
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1255240	1			T21	6		T25	180		T27	101
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	433156	1			T21	33		T1	5		T12	13
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1052588	1			T21	8		T25	164		T27	106
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	3986124	1			T21	63		T22	1		T23	933
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3135917	1			T21	69		T23	792		T24	11618
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1066007	1			T21	2		T25	178		T27	75
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1252092	1			T21	30		T25	157		T27	78
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	431133	1			T21	17		T1	1		T12	23
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1052056	1			T21	3		T25	162		T27	62
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	3991729	1			T21	54		T22	1		T23	878
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3125764	1			T21	97		T23	847		T24	11701
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1062994	1			T21	1		T25	187		T27	80
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1254276	1			T21	15		T25	166		T27	72
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	434778	1			T21	10		T1	1		T12	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1053788	1			T21	7		T25	134		T27	76
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	3984180	1			T21	70		T22	1		T23	812
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3136657	1			T21	67		T23	913		T24	11609
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1064177	1			T21	3		T25	158		T27	80
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1252432	1			T21	3		T25	172		T27	91
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	433379	1			T21	14		T12	3		T2	14
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1052504	1			T21	27		T25	175		T27	80
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	3983318	1			T21	77		T22	1		T23	883
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3134201	1			T21	62		T23	842		T24	11485
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1062589	1			T21	2		T25	136		T27	77
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1257441	1			T21	13		T25	191		T27	64
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	431024	1			T21	11		T1	4		T12	11
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1054756	1			T21	19		T25	188		T27	96
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	3988680	1			T21	63		T22	1		T23	807
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3136934	1			T21	56		T23	918		T24	11201
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1063245	1			T21	2		T25	192		T27	100
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1255278	1			T21	20		T25	164		T27	60
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	430776	1			T21	19		T1	4		T12	5
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1048416	1			T21	24		T25	164		T27	68
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	3995171	1			T21	94		T22	1		T23	906
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3128665	1			T21	34		T23	819		T24	11572
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1057349	1			T21	2		T25	168		T27	80
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1258921	1			T21	22		T25	159		T27	68
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	432395	1			T21	10		T1	4		T12	14
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1050828	1			T21	22		T25	172		T27	104
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	3989481	1			T21	49		T22	1		T23	827
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3130976	1			T21	79		T23	898		T24	11272
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1056682	1			T25	146		T27	88		T28	34
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1258807	1			T21	18		T25	202		T27	86
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	433765	1			T21	8		T1	2		T12	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1053618	1			T21	30		T25	170		T27	65
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	3984820	1			T21	70		T22	1		T23	860
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3134709	1			T21	39		T23	865		T24	12029
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1062226	1			T21	2		T25	162		T27	68
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1259616	1			T21	27		T25	150		T27	104
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	434481	1			T21	25		T1	1		T12	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1047477	1			T21	21		T25	182		T27	84
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	3986734	1			T21	71		T22	1		T23	951
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3140159	1			T21	76		T23	774		T24	11153
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1056794	1			T21	5		T25	164		T27	77
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1256080	1			T21	11		T25	163		T27	80
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	431813	1			T21	20		T1	1		T12	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1051749	1			T21	1		T25	164		T27	60

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal