Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[1]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[2]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[3]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[4]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[5]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[6]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[7]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[8]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[9]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[10]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[11]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[12]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[13]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[14]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[15]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[16]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[17]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[18]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[19]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[20]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[21]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[22]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[23]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[24]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[25]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[26]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[27]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[28]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[29]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[30]	10923329	1			T21	184		T22	1		T23	1725
bins_for_gpio_bits[31]	10923329	1			T21	184		T22	1		T23	1725

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

201694463

1

T21

2975

T22

32

T23

28196

auto[1]

147852065

1

T21

2913

T23

27004

T24

389649

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

201687392

1

T21

2983

T22

32

T23

28196

auto[1]

147859136

1

T21

2905

T23

27004

T24

389649

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6107281	1			T21	102		T22	1		T23	849
bins_for_gpio_bits[0]	auto[0]	auto[1]	189908	1			T21	1		T25	46		T27	20
bins_for_gpio_bits[0]	auto[1]	auto[0]	190135	1			T25	46		T27	20		T28	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	4436005	1			T21	81		T23	876		T24	13515
bins_for_gpio_bits[1]	auto[0]	auto[0]	6105966	1			T21	101		T22	1		T23	893
bins_for_gpio_bits[1]	auto[0]	auto[1]	189855	1			T25	48		T27	19		T28	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	190072	1			T25	48		T27	19		T28	6
bins_for_gpio_bits[1]	auto[1]	auto[1]	4437436	1			T21	83		T23	832		T24	12194
bins_for_gpio_bits[2]	auto[0]	auto[0]	6110722	1			T21	100		T22	1		T23	940
bins_for_gpio_bits[2]	auto[0]	auto[1]	189045	1			T25	36		T27	20		T28	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	189298	1			T25	36		T27	20		T28	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	4434264	1			T21	84		T23	785		T24	13172
bins_for_gpio_bits[3]	auto[0]	auto[0]	6120877	1			T21	136		T22	1		T23	828
bins_for_gpio_bits[3]	auto[0]	auto[1]	189159	1			T21	1		T25	44		T27	18
bins_for_gpio_bits[3]	auto[1]	auto[0]	189392	1			T25	44		T27	18		T28	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	4423901	1			T21	47		T23	897		T24	12033
bins_for_gpio_bits[4]	auto[0]	auto[0]	6114337	1			T21	43		T22	1		T23	827
bins_for_gpio_bits[4]	auto[0]	auto[1]	189409	1			T25	44		T27	16		T28	6
bins_for_gpio_bits[4]	auto[1]	auto[0]	189656	1			T25	44		T27	16		T28	6
bins_for_gpio_bits[4]	auto[1]	auto[1]	4429927	1			T21	141		T23	898		T24	11754
bins_for_gpio_bits[5]	auto[0]	auto[0]	6122563	1			T21	135		T22	1		T23	855
bins_for_gpio_bits[5]	auto[0]	auto[1]	189341	1			T25	42		T27	22		T28	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	189574	1			T25	42		T27	22		T28	6
bins_for_gpio_bits[5]	auto[1]	auto[1]	4421851	1			T21	49		T23	870		T24	11684
bins_for_gpio_bits[6]	auto[0]	auto[0]	6115035	1			T21	71		T22	1		T23	972
bins_for_gpio_bits[6]	auto[0]	auto[1]	189683	1			T21	1		T25	47		T27	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	189887	1			T25	47		T27	18		T28	5
bins_for_gpio_bits[6]	auto[1]	auto[1]	4428724	1			T21	112		T23	753		T24	12647
bins_for_gpio_bits[7]	auto[0]	auto[0]	6112828	1			T21	113		T22	1		T23	929
bins_for_gpio_bits[7]	auto[0]	auto[1]	189585	1			T25	48		T27	17		T28	6
bins_for_gpio_bits[7]	auto[1]	auto[0]	189778	1			T25	49		T27	17		T28	7
bins_for_gpio_bits[7]	auto[1]	auto[1]	4431138	1			T21	71		T23	796		T24	12424
bins_for_gpio_bits[8]	auto[0]	auto[0]	6109626	1			T21	125		T22	1		T23	947
bins_for_gpio_bits[8]	auto[0]	auto[1]	190322	1			T25	42		T27	26		T28	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	190568	1			T25	42		T27	26		T28	5
bins_for_gpio_bits[8]	auto[1]	auto[1]	4432813	1			T21	59		T23	778		T24	12493
bins_for_gpio_bits[9]	auto[0]	auto[0]	6108587	1			T21	103		T22	1		T23	883
bins_for_gpio_bits[9]	auto[0]	auto[1]	189439	1			T25	41		T27	18		T28	7
bins_for_gpio_bits[9]	auto[1]	auto[0]	189670	1			T25	41		T27	18		T28	7
bins_for_gpio_bits[9]	auto[1]	auto[1]	4435633	1			T21	81		T23	842		T24	12271
bins_for_gpio_bits[10]	auto[0]	auto[0]	6105454	1			T21	69		T22	1		T23	904
bins_for_gpio_bits[10]	auto[0]	auto[1]	189437	1			T25	48		T27	23		T28	7
bins_for_gpio_bits[10]	auto[1]	auto[0]	189690	1			T25	48		T27	23		T28	8
bins_for_gpio_bits[10]	auto[1]	auto[1]	4438748	1			T21	115		T23	821		T24	12533
bins_for_gpio_bits[11]	auto[0]	auto[0]	6093254	1			T21	108		T22	1		T23	931
bins_for_gpio_bits[11]	auto[0]	auto[1]	190123	1			T21	1		T25	37		T27	21
bins_for_gpio_bits[11]	auto[1]	auto[0]	190326	1			T25	37		T27	21		T28	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	4449626	1			T21	75		T23	794		T24	12749
bins_for_gpio_bits[12]	auto[0]	auto[0]	6101040	1			T21	54		T22	1		T23	894
bins_for_gpio_bits[12]	auto[0]	auto[1]	189721	1			T25	39		T27	19		T28	6
bins_for_gpio_bits[12]	auto[1]	auto[0]	189915	1			T25	40		T27	19		T28	6
bins_for_gpio_bits[12]	auto[1]	auto[1]	4442653	1			T21	130		T23	831		T24	12871
bins_for_gpio_bits[13]	auto[0]	auto[0]	6111767	1			T21	137		T22	1		T23	784
bins_for_gpio_bits[13]	auto[0]	auto[1]	189215	1			T25	39		T27	18		T28	3
bins_for_gpio_bits[13]	auto[1]	auto[0]	189429	1			T25	40		T27	18		T28	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	4432918	1			T21	47		T23	941		T24	12994
bins_for_gpio_bits[14]	auto[0]	auto[0]	6115045	1			T21	52		T22	1		T23	932
bins_for_gpio_bits[14]	auto[0]	auto[1]	190096	1			T25	46		T27	19		T28	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	190352	1			T25	47		T27	19		T28	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	4427836	1			T21	132		T23	793		T24	11590
bins_for_gpio_bits[15]	auto[0]	auto[0]	6109186	1			T21	97		T22	1		T23	947
bins_for_gpio_bits[15]	auto[0]	auto[1]	190118	1			T25	34		T27	16		T28	7
bins_for_gpio_bits[15]	auto[1]	auto[0]	190355	1			T25	34		T27	16		T28	7
bins_for_gpio_bits[15]	auto[1]	auto[1]	4433670	1			T21	87		T23	778		T24	13137
bins_for_gpio_bits[16]	auto[0]	auto[0]	6118375	1			T21	93		T22	1		T23	967
bins_for_gpio_bits[16]	auto[0]	auto[1]	189540	1			T25	41		T27	18		T28	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	189729	1			T25	41		T27	18		T28	7
bins_for_gpio_bits[16]	auto[1]	auto[1]	4425685	1			T21	91		T23	758		T24	11206
bins_for_gpio_bits[17]	auto[0]	auto[0]	6119935	1			T21	104		T22	1		T23	818
bins_for_gpio_bits[17]	auto[0]	auto[1]	189867	1			T25	35		T27	18		T28	9
bins_for_gpio_bits[17]	auto[1]	auto[0]	190080	1			T25	35		T27	18		T28	9
bins_for_gpio_bits[17]	auto[1]	auto[1]	4423447	1			T21	80		T23	907		T24	12727
bins_for_gpio_bits[18]	auto[0]	auto[0]	6116156	1			T21	108		T22	1		T23	890
bins_for_gpio_bits[18]	auto[0]	auto[1]	189962	1			T21	1		T25	43		T27	19
bins_for_gpio_bits[18]	auto[1]	auto[0]	190192	1			T25	43		T27	20		T28	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	4427019	1			T21	75		T23	835		T24	12302
bins_for_gpio_bits[19]	auto[0]	auto[0]	6118058	1			T21	92		T22	1		T23	833
bins_for_gpio_bits[19]	auto[0]	auto[1]	189218	1			T25	42		T27	21		T28	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	189444	1			T25	43		T27	21		T28	6
bins_for_gpio_bits[19]	auto[1]	auto[1]	4426609	1			T21	92		T23	892		T24	12609
bins_for_gpio_bits[20]	auto[0]	auto[0]	6117785	1			T21	81		T22	1		T23	796
bins_for_gpio_bits[20]	auto[0]	auto[1]	189622	1			T21	1		T25	40		T27	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	189852	1			T25	40		T27	17		T28	4
bins_for_gpio_bits[20]	auto[1]	auto[1]	4426070	1			T21	102		T23	929		T24	12144
bins_for_gpio_bits[21]	auto[0]	auto[0]	6105162	1			T21	84		T22	1		T23	868
bins_for_gpio_bits[21]	auto[0]	auto[1]	189894	1			T25	49		T27	24		T28	7
bins_for_gpio_bits[21]	auto[1]	auto[0]	190091	1			T25	50		T27	25		T28	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	4438182	1			T21	100		T23	857		T24	12591
bins_for_gpio_bits[22]	auto[0]	auto[0]	6121409	1			T21	78		T22	1		T23	852
bins_for_gpio_bits[22]	auto[0]	auto[1]	189069	1			T25	36		T27	22		T28	6
bins_for_gpio_bits[22]	auto[1]	auto[0]	189287	1			T25	36		T27	22		T28	7
bins_for_gpio_bits[22]	auto[1]	auto[1]	4423564	1			T21	106		T23	873		T24	12369
bins_for_gpio_bits[23]	auto[0]	auto[0]	6114336	1			T21	95		T22	1		T23	933
bins_for_gpio_bits[23]	auto[0]	auto[1]	189681	1			T25	42		T27	18		T28	6
bins_for_gpio_bits[23]	auto[1]	auto[0]	189887	1			T25	42		T27	18		T28	7
bins_for_gpio_bits[23]	auto[1]	auto[1]	4429425	1			T21	89		T23	792		T24	11618
bins_for_gpio_bits[24]	auto[0]	auto[0]	6119043	1			T21	70		T22	1		T23	878
bins_for_gpio_bits[24]	auto[0]	auto[1]	189760	1			T25	37		T27	21		T28	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	189956	1			T25	37		T27	21		T28	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	4424570	1			T21	114		T23	847		T24	11701
bins_for_gpio_bits[25]	auto[0]	auto[0]	6111406	1			T21	76		T22	1		T23	812
bins_for_gpio_bits[25]	auto[0]	auto[1]	189179	1			T21	1		T25	43		T27	20
bins_for_gpio_bits[25]	auto[1]	auto[0]	189383	1			T25	44		T27	20		T28	9
bins_for_gpio_bits[25]	auto[1]	auto[1]	4433361	1			T21	107		T23	913		T24	11609
bins_for_gpio_bits[26]	auto[0]	auto[0]	6113374	1			T21	92		T22	1		T23	883
bins_for_gpio_bits[26]	auto[0]	auto[1]	189741	1			T25	49		T27	20		T28	6
bins_for_gpio_bits[26]	auto[1]	auto[0]	189974	1			T25	49		T27	20		T28	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	4430240	1			T21	92		T23	842		T24	11485
bins_for_gpio_bits[27]	auto[0]	auto[0]	6117209	1			T21	85		T22	1		T23	807
bins_for_gpio_bits[27]	auto[0]	auto[1]	189841	1			T25	49		T27	17		T28	5
bins_for_gpio_bits[27]	auto[1]	auto[0]	189994	1			T25	49		T27	17		T28	5
bins_for_gpio_bits[27]	auto[1]	auto[1]	4426285	1			T21	99		T23	918		T24	11201
bins_for_gpio_bits[28]	auto[0]	auto[0]	6121949	1			T21	118		T22	1		T23	906
bins_for_gpio_bits[28]	auto[0]	auto[1]	189224	1			T25	43		T27	25		T28	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	189492	1			T25	43		T27	25		T28	8
bins_for_gpio_bits[28]	auto[1]	auto[1]	4422664	1			T21	66		T23	819		T24	11572
bins_for_gpio_bits[29]	auto[0]	auto[0]	6115187	1			T21	67		T22	1		T23	827
bins_for_gpio_bits[29]	auto[0]	auto[1]	189584	1			T21	1		T25	41		T27	17
bins_for_gpio_bits[29]	auto[1]	auto[0]	189783	1			T25	41		T27	18		T28	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	4428775	1			T21	116		T23	898		T24	11272
bins_for_gpio_bits[30]	auto[0]	auto[0]	6117523	1			T21	99		T22	1		T23	860
bins_for_gpio_bits[30]	auto[0]	auto[1]	188899	1			T25	46		T27	22		T28	5
bins_for_gpio_bits[30]	auto[1]	auto[0]	189139	1			T25	46		T27	22		T28	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	4427768	1			T21	85		T23	865		T24	12029
bins_for_gpio_bits[31]	auto[0]	auto[0]	6110024	1			T21	87		T22	1		T23	951
bins_for_gpio_bits[31]	auto[0]	auto[1]	189356	1			T25	47		T27	17		T28	3
bins_for_gpio_bits[31]	auto[1]	auto[0]	189584	1			T25	47		T27	17		T28	3
bins_for_gpio_bits[31]	auto[1]	auto[1]	4434365	1			T21	97		T23	774		T24	11153