Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6586094 |
1 |
|
|
T21 |
90 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4432400 |
1 |
|
|
T21 |
43 |
|
T29 |
130 |
|
T30 |
1265 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10455151 |
1 |
|
|
T21 |
130 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
563343 |
1 |
|
|
T21 |
3 |
|
T29 |
7 |
|
T30 |
291 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6570637 |
1 |
|
|
T21 |
82 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4447857 |
1 |
|
|
T21 |
51 |
|
T29 |
95 |
|
T30 |
1441 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1947054 |
1 |
|
|
T21 |
36 |
|
T29 |
45 |
|
T30 |
561 |
| auto[1] |
auto[0] |
auto[1] |
282886 |
1 |
|
|
T21 |
1 |
|
T29 |
2 |
|
T30 |
142 |
| auto[1] |
auto[1] |
auto[0] |
1937460 |
1 |
|
|
T21 |
12 |
|
T29 |
43 |
|
T30 |
589 |
| auto[1] |
auto[1] |
auto[1] |
280457 |
1 |
|
|
T21 |
2 |
|
T29 |
5 |
|
T30 |
149 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6575049 |
1 |
|
|
T21 |
67 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4443445 |
1 |
|
|
T21 |
66 |
|
T29 |
118 |
|
T30 |
745 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10455543 |
1 |
|
|
T21 |
129 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
562951 |
1 |
|
|
T21 |
4 |
|
T29 |
9 |
|
T30 |
216 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6578910 |
1 |
|
|
T21 |
106 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4439584 |
1 |
|
|
T21 |
27 |
|
T29 |
149 |
|
T30 |
1118 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1935609 |
1 |
|
|
T21 |
10 |
|
T29 |
69 |
|
T30 |
599 |
| auto[1] |
auto[0] |
auto[1] |
280973 |
1 |
|
|
T21 |
2 |
|
T29 |
4 |
|
T30 |
151 |
| auto[1] |
auto[1] |
auto[0] |
1941024 |
1 |
|
|
T21 |
13 |
|
T29 |
71 |
|
T30 |
303 |
| auto[1] |
auto[1] |
auto[1] |
281978 |
1 |
|
|
T21 |
2 |
|
T29 |
5 |
|
T30 |
65 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6568849 |
1 |
|
|
T21 |
100 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4449645 |
1 |
|
|
T21 |
33 |
|
T29 |
130 |
|
T30 |
1235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10458435 |
1 |
|
|
T21 |
130 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
560059 |
1 |
|
|
T21 |
3 |
|
T29 |
6 |
|
T30 |
236 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6589848 |
1 |
|
|
T21 |
102 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4428646 |
1 |
|
|
T21 |
31 |
|
T29 |
121 |
|
T30 |
1204 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1934999 |
1 |
|
|
T21 |
19 |
|
T29 |
63 |
|
T30 |
451 |
| auto[1] |
auto[0] |
auto[1] |
280287 |
1 |
|
|
T21 |
3 |
|
T29 |
4 |
|
T30 |
93 |
| auto[1] |
auto[1] |
auto[0] |
1933588 |
1 |
|
|
T21 |
9 |
|
T29 |
52 |
|
T30 |
517 |
| auto[1] |
auto[1] |
auto[1] |
279772 |
1 |
|
|
T29 |
2 |
|
T30 |
143 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6589494 |
1 |
|
|
T21 |
86 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4429000 |
1 |
|
|
T21 |
47 |
|
T29 |
163 |
|
T30 |
1023 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10461563 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
556931 |
1 |
|
|
T21 |
1 |
|
T29 |
6 |
|
T30 |
243 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6615306 |
1 |
|
|
T21 |
88 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4403188 |
1 |
|
|
T21 |
45 |
|
T29 |
81 |
|
T30 |
1214 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1923418 |
1 |
|
|
T21 |
26 |
|
T29 |
21 |
|
T30 |
521 |
| auto[1] |
auto[0] |
auto[1] |
277955 |
1 |
|
|
T29 |
2 |
|
T30 |
131 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1922839 |
1 |
|
|
T21 |
18 |
|
T29 |
54 |
|
T30 |
450 |
| auto[1] |
auto[1] |
auto[1] |
278976 |
1 |
|
|
T21 |
1 |
|
T29 |
4 |
|
T30 |
112 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6602759 |
1 |
|
|
T21 |
79 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4415735 |
1 |
|
|
T21 |
54 |
|
T29 |
90 |
|
T30 |
1175 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10454304 |
1 |
|
|
T21 |
131 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
564190 |
1 |
|
|
T21 |
2 |
|
T29 |
6 |
|
T30 |
204 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6564147 |
1 |
|
|
T21 |
88 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4454347 |
1 |
|
|
T21 |
45 |
|
T29 |
156 |
|
T30 |
1038 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1955326 |
1 |
|
|
T21 |
18 |
|
T29 |
95 |
|
T30 |
411 |
| auto[1] |
auto[0] |
auto[1] |
283670 |
1 |
|
|
T21 |
1 |
|
T29 |
3 |
|
T30 |
93 |
| auto[1] |
auto[1] |
auto[0] |
1934831 |
1 |
|
|
T21 |
25 |
|
T29 |
55 |
|
T30 |
423 |
| auto[1] |
auto[1] |
auto[1] |
280520 |
1 |
|
|
T21 |
1 |
|
T29 |
3 |
|
T30 |
111 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6606670 |
1 |
|
|
T21 |
70 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4411824 |
1 |
|
|
T21 |
63 |
|
T29 |
129 |
|
T30 |
908 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10455103 |
1 |
|
|
T21 |
133 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
563391 |
1 |
|
|
T29 |
7 |
|
T30 |
234 |
|
T1 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6574212 |
1 |
|
|
T21 |
111 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4444282 |
1 |
|
|
T21 |
22 |
|
T29 |
110 |
|
T30 |
1244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1947948 |
1 |
|
|
T21 |
13 |
|
T29 |
61 |
|
T30 |
603 |
| auto[1] |
auto[0] |
auto[1] |
283296 |
1 |
|
|
T29 |
3 |
|
T30 |
141 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1932943 |
1 |
|
|
T21 |
9 |
|
T29 |
42 |
|
T30 |
407 |
| auto[1] |
auto[1] |
auto[1] |
280095 |
1 |
|
|
T29 |
4 |
|
T30 |
93 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6601626 |
1 |
|
|
T21 |
94 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4416868 |
1 |
|
|
T21 |
39 |
|
T29 |
110 |
|
T30 |
785 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10459147 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
559347 |
1 |
|
|
T21 |
1 |
|
T29 |
2 |
|
T30 |
202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6610194 |
1 |
|
|
T21 |
102 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4408300 |
1 |
|
|
T21 |
31 |
|
T29 |
91 |
|
T30 |
1050 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1939491 |
1 |
|
|
T21 |
24 |
|
T29 |
54 |
|
T30 |
510 |
| auto[1] |
auto[0] |
auto[1] |
282824 |
1 |
|
|
T21 |
1 |
|
T30 |
105 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1909462 |
1 |
|
|
T21 |
6 |
|
T29 |
35 |
|
T30 |
338 |
| auto[1] |
auto[1] |
auto[1] |
276523 |
1 |
|
|
T29 |
2 |
|
T30 |
97 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6597319 |
1 |
|
|
T21 |
83 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4421175 |
1 |
|
|
T21 |
50 |
|
T29 |
117 |
|
T30 |
1190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10457117 |
1 |
|
|
T21 |
131 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
561377 |
1 |
|
|
T21 |
2 |
|
T29 |
6 |
|
T30 |
258 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6583937 |
1 |
|
|
T21 |
83 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4434557 |
1 |
|
|
T21 |
50 |
|
T29 |
140 |
|
T30 |
1303 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1945077 |
1 |
|
|
T21 |
23 |
|
T29 |
76 |
|
T30 |
468 |
| auto[1] |
auto[0] |
auto[1] |
282596 |
1 |
|
|
T21 |
1 |
|
T29 |
2 |
|
T30 |
118 |
| auto[1] |
auto[1] |
auto[0] |
1928103 |
1 |
|
|
T21 |
25 |
|
T29 |
58 |
|
T30 |
577 |
| auto[1] |
auto[1] |
auto[1] |
278781 |
1 |
|
|
T21 |
1 |
|
T29 |
4 |
|
T30 |
140 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6585913 |
1 |
|
|
T21 |
83 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4432581 |
1 |
|
|
T21 |
50 |
|
T29 |
109 |
|
T30 |
867 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10456302 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
562192 |
1 |
|
|
T21 |
1 |
|
T29 |
5 |
|
T30 |
239 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6582642 |
1 |
|
|
T21 |
108 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4435852 |
1 |
|
|
T21 |
25 |
|
T29 |
116 |
|
T30 |
1258 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1940308 |
1 |
|
|
T21 |
20 |
|
T29 |
61 |
|
T30 |
596 |
| auto[1] |
auto[0] |
auto[1] |
281489 |
1 |
|
|
T29 |
3 |
|
T30 |
143 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1933352 |
1 |
|
|
T21 |
4 |
|
T29 |
50 |
|
T30 |
423 |
| auto[1] |
auto[1] |
auto[1] |
280703 |
1 |
|
|
T21 |
1 |
|
T29 |
2 |
|
T30 |
96 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6575712 |
1 |
|
|
T21 |
89 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4442782 |
1 |
|
|
T21 |
44 |
|
T29 |
104 |
|
T30 |
855 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10455944 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
562550 |
1 |
|
|
T21 |
1 |
|
T29 |
8 |
|
T30 |
152 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6577309 |
1 |
|
|
T21 |
96 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4441185 |
1 |
|
|
T21 |
37 |
|
T29 |
169 |
|
T30 |
850 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1932641 |
1 |
|
|
T21 |
24 |
|
T29 |
88 |
|
T30 |
538 |
| auto[1] |
auto[0] |
auto[1] |
280564 |
1 |
|
|
T29 |
6 |
|
T30 |
118 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1945994 |
1 |
|
|
T21 |
12 |
|
T29 |
73 |
|
T30 |
160 |
| auto[1] |
auto[1] |
auto[1] |
281986 |
1 |
|
|
T21 |
1 |
|
T29 |
2 |
|
T30 |
34 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6578409 |
1 |
|
|
T21 |
104 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4440085 |
1 |
|
|
T21 |
29 |
|
T29 |
137 |
|
T30 |
944 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10456461 |
1 |
|
|
T21 |
131 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
562033 |
1 |
|
|
T21 |
2 |
|
T29 |
4 |
|
T30 |
218 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6588590 |
1 |
|
|
T21 |
92 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4429904 |
1 |
|
|
T21 |
41 |
|
T29 |
92 |
|
T30 |
1110 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1939601 |
1 |
|
|
T21 |
36 |
|
T29 |
46 |
|
T30 |
588 |
| auto[1] |
auto[0] |
auto[1] |
281661 |
1 |
|
|
T21 |
2 |
|
T29 |
3 |
|
T30 |
138 |
| auto[1] |
auto[1] |
auto[0] |
1928270 |
1 |
|
|
T21 |
3 |
|
T29 |
42 |
|
T30 |
304 |
| auto[1] |
auto[1] |
auto[1] |
280372 |
1 |
|
|
T29 |
1 |
|
T30 |
80 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6591104 |
1 |
|
|
T21 |
91 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4427390 |
1 |
|
|
T21 |
42 |
|
T29 |
132 |
|
T30 |
1248 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10457275 |
1 |
|
|
T21 |
133 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
561219 |
1 |
|
|
T29 |
9 |
|
T30 |
272 |
|
T1 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6579437 |
1 |
|
|
T21 |
117 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4439057 |
1 |
|
|
T21 |
16 |
|
T29 |
120 |
|
T30 |
1358 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1963332 |
1 |
|
|
T21 |
8 |
|
T29 |
48 |
|
T30 |
478 |
| auto[1] |
auto[0] |
auto[1] |
284957 |
1 |
|
|
T29 |
2 |
|
T30 |
118 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1914506 |
1 |
|
|
T21 |
8 |
|
T29 |
63 |
|
T30 |
608 |
| auto[1] |
auto[1] |
auto[1] |
276262 |
1 |
|
|
T29 |
7 |
|
T30 |
154 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6584546 |
1 |
|
|
T21 |
84 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4433948 |
1 |
|
|
T21 |
49 |
|
T29 |
103 |
|
T30 |
1117 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10461874 |
1 |
|
|
T21 |
131 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
556620 |
1 |
|
|
T21 |
2 |
|
T29 |
10 |
|
T30 |
252 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6612618 |
1 |
|
|
T21 |
106 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4405876 |
1 |
|
|
T21 |
27 |
|
T29 |
115 |
|
T30 |
1296 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1929210 |
1 |
|
|
T21 |
16 |
|
T29 |
59 |
|
T30 |
615 |
| auto[1] |
auto[0] |
auto[1] |
278938 |
1 |
|
|
T21 |
1 |
|
T29 |
6 |
|
T30 |
167 |
| auto[1] |
auto[1] |
auto[0] |
1920046 |
1 |
|
|
T21 |
9 |
|
T29 |
46 |
|
T30 |
429 |
| auto[1] |
auto[1] |
auto[1] |
277682 |
1 |
|
|
T21 |
1 |
|
T29 |
4 |
|
T30 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6573700 |
1 |
|
|
T21 |
95 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4444794 |
1 |
|
|
T21 |
38 |
|
T29 |
141 |
|
T30 |
939 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10459308 |
1 |
|
|
T21 |
131 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
559186 |
1 |
|
|
T21 |
2 |
|
T29 |
4 |
|
T30 |
240 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6594370 |
1 |
|
|
T21 |
83 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4424124 |
1 |
|
|
T21 |
50 |
|
T29 |
106 |
|
T30 |
1228 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1938412 |
1 |
|
|
T21 |
33 |
|
T29 |
36 |
|
T30 |
471 |
| auto[1] |
auto[0] |
auto[1] |
280461 |
1 |
|
|
T21 |
2 |
|
T29 |
2 |
|
T30 |
117 |
| auto[1] |
auto[1] |
auto[0] |
1926526 |
1 |
|
|
T21 |
15 |
|
T29 |
66 |
|
T30 |
517 |
| auto[1] |
auto[1] |
auto[1] |
278725 |
1 |
|
|
T29 |
2 |
|
T30 |
123 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6598371 |
1 |
|
|
T21 |
102 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4420123 |
1 |
|
|
T21 |
31 |
|
T29 |
66 |
|
T30 |
1168 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10454827 |
1 |
|
|
T21 |
131 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
563667 |
1 |
|
|
T21 |
2 |
|
T29 |
4 |
|
T30 |
250 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6568674 |
1 |
|
|
T21 |
78 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4449820 |
1 |
|
|
T21 |
55 |
|
T29 |
100 |
|
T30 |
1300 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1949555 |
1 |
|
|
T21 |
41 |
|
T29 |
71 |
|
T30 |
472 |
| auto[1] |
auto[0] |
auto[1] |
282811 |
1 |
|
|
T21 |
1 |
|
T29 |
4 |
|
T30 |
110 |
| auto[1] |
auto[1] |
auto[0] |
1936598 |
1 |
|
|
T21 |
12 |
|
T29 |
25 |
|
T30 |
578 |
| auto[1] |
auto[1] |
auto[1] |
280856 |
1 |
|
|
T21 |
1 |
|
T30 |
140 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6568520 |
1 |
|
|
T21 |
106 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4449974 |
1 |
|
|
T21 |
27 |
|
T29 |
175 |
|
T30 |
1483 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10454316 |
1 |
|
|
T21 |
131 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
564178 |
1 |
|
|
T21 |
2 |
|
T29 |
6 |
|
T30 |
205 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6561012 |
1 |
|
|
T21 |
91 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4457482 |
1 |
|
|
T21 |
42 |
|
T29 |
139 |
|
T30 |
1024 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1944665 |
1 |
|
|
T21 |
31 |
|
T29 |
42 |
|
T30 |
313 |
| auto[1] |
auto[0] |
auto[1] |
282343 |
1 |
|
|
T21 |
1 |
|
T30 |
77 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1948639 |
1 |
|
|
T21 |
9 |
|
T29 |
91 |
|
T30 |
506 |
| auto[1] |
auto[1] |
auto[1] |
281835 |
1 |
|
|
T21 |
1 |
|
T29 |
6 |
|
T30 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6585251 |
1 |
|
|
T21 |
102 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4433243 |
1 |
|
|
T21 |
31 |
|
T29 |
89 |
|
T30 |
1271 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10455141 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
563353 |
1 |
|
|
T21 |
1 |
|
T29 |
8 |
|
T30 |
292 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6571777 |
1 |
|
|
T21 |
93 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4446717 |
1 |
|
|
T21 |
40 |
|
T29 |
152 |
|
T30 |
1432 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1944035 |
1 |
|
|
T21 |
24 |
|
T29 |
101 |
|
T30 |
547 |
| auto[1] |
auto[0] |
auto[1] |
282267 |
1 |
|
|
T29 |
5 |
|
T30 |
138 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1939329 |
1 |
|
|
T21 |
15 |
|
T29 |
43 |
|
T30 |
593 |
| auto[1] |
auto[1] |
auto[1] |
281086 |
1 |
|
|
T21 |
1 |
|
T29 |
3 |
|
T30 |
154 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6577805 |
1 |
|
|
T21 |
74 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4440689 |
1 |
|
|
T21 |
59 |
|
T29 |
89 |
|
T30 |
837 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10455066 |
1 |
|
|
T21 |
133 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
563428 |
1 |
|
|
T29 |
6 |
|
T30 |
234 |
|
T1 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6570142 |
1 |
|
|
T21 |
115 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4448352 |
1 |
|
|
T21 |
18 |
|
T29 |
129 |
|
T30 |
1157 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1941678 |
1 |
|
|
T21 |
5 |
|
T29 |
87 |
|
T30 |
590 |
| auto[1] |
auto[0] |
auto[1] |
280723 |
1 |
|
|
T29 |
5 |
|
T30 |
145 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1943246 |
1 |
|
|
T21 |
13 |
|
T29 |
36 |
|
T30 |
333 |
| auto[1] |
auto[1] |
auto[1] |
282705 |
1 |
|
|
T29 |
1 |
|
T30 |
89 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6588281 |
1 |
|
|
T21 |
86 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4430213 |
1 |
|
|
T21 |
47 |
|
T29 |
128 |
|
T30 |
1288 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10456883 |
1 |
|
|
T21 |
133 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
561611 |
1 |
|
|
T29 |
3 |
|
T30 |
242 |
|
T1 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6584912 |
1 |
|
|
T21 |
112 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4433582 |
1 |
|
|
T21 |
21 |
|
T29 |
104 |
|
T30 |
1195 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1942921 |
1 |
|
|
T21 |
16 |
|
T29 |
56 |
|
T30 |
490 |
| auto[1] |
auto[0] |
auto[1] |
282058 |
1 |
|
|
T29 |
3 |
|
T30 |
119 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1929050 |
1 |
|
|
T21 |
5 |
|
T29 |
45 |
|
T30 |
463 |
| auto[1] |
auto[1] |
auto[1] |
279553 |
1 |
|
|
T30 |
123 |
|
T1 |
2 |
|
T11 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6590097 |
1 |
|
|
T21 |
59 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4428397 |
1 |
|
|
T21 |
74 |
|
T29 |
89 |
|
T30 |
803 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10454904 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
563590 |
1 |
|
|
T21 |
1 |
|
T29 |
3 |
|
T30 |
292 |