Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6567284 |
1 |
|
|
T21 |
100 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4451210 |
1 |
|
|
T21 |
33 |
|
T29 |
91 |
|
T30 |
1196 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10456520 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
561974 |
1 |
|
|
T21 |
1 |
|
T29 |
5 |
|
T30 |
208 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6575184 |
1 |
|
|
T21 |
94 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4443310 |
1 |
|
|
T21 |
39 |
|
T29 |
107 |
|
T30 |
1077 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1946783 |
1 |
|
|
T21 |
25 |
|
T29 |
65 |
|
T30 |
495 |
| auto[1] |
auto[0] |
auto[1] |
282425 |
1 |
|
|
T21 |
1 |
|
T29 |
2 |
|
T30 |
122 |
| auto[1] |
auto[1] |
auto[0] |
1934553 |
1 |
|
|
T21 |
13 |
|
T29 |
37 |
|
T30 |
374 |
| auto[1] |
auto[1] |
auto[1] |
279549 |
1 |
|
|
T29 |
3 |
|
T30 |
86 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |