Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6585884 |
1 |
|
|
T21 |
84 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4432610 |
1 |
|
|
T21 |
49 |
|
T29 |
107 |
|
T30 |
1542 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10458397 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
560097 |
1 |
|
|
T21 |
1 |
|
T29 |
7 |
|
T30 |
260 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6589311 |
1 |
|
|
T21 |
72 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4429183 |
1 |
|
|
T21 |
61 |
|
T29 |
132 |
|
T30 |
1319 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1947310 |
1 |
|
|
T21 |
30 |
|
T29 |
63 |
|
T30 |
320 |
| auto[1] |
auto[0] |
auto[1] |
282532 |
1 |
|
|
T21 |
1 |
|
T29 |
5 |
|
T30 |
87 |
| auto[1] |
auto[1] |
auto[0] |
1921776 |
1 |
|
|
T21 |
30 |
|
T29 |
62 |
|
T30 |
739 |
| auto[1] |
auto[1] |
auto[1] |
277565 |
1 |
|
|
T29 |
2 |
|
T30 |
173 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |