Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6610445 |
1 |
|
|
T21 |
74 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4408049 |
1 |
|
|
T21 |
59 |
|
T29 |
184 |
|
T30 |
967 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10459724 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
558770 |
1 |
|
|
T21 |
1 |
|
T29 |
4 |
|
T30 |
235 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6596611 |
1 |
|
|
T21 |
94 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4421883 |
1 |
|
|
T21 |
39 |
|
T29 |
100 |
|
T30 |
1209 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1934708 |
1 |
|
|
T21 |
10 |
|
T29 |
25 |
|
T30 |
497 |
| auto[1] |
auto[0] |
auto[1] |
279989 |
1 |
|
|
T21 |
1 |
|
T30 |
113 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1928405 |
1 |
|
|
T21 |
28 |
|
T29 |
71 |
|
T30 |
477 |
| auto[1] |
auto[1] |
auto[1] |
278781 |
1 |
|
|
T29 |
4 |
|
T30 |
122 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |