Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6586094 |
1 |
|
|
T21 |
90 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4432400 |
1 |
|
|
T21 |
43 |
|
T29 |
130 |
|
T30 |
1265 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9124342 |
1 |
|
|
T21 |
119 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1894152 |
1 |
|
|
T21 |
14 |
|
T29 |
91 |
|
T30 |
558 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6568933 |
1 |
|
|
T21 |
108 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4449561 |
1 |
|
|
T21 |
25 |
|
T29 |
160 |
|
T30 |
1136 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1273912 |
1 |
|
|
T21 |
7 |
|
T29 |
24 |
|
T30 |
310 |
| auto[1] |
auto[0] |
auto[1] |
950097 |
1 |
|
|
T21 |
5 |
|
T29 |
47 |
|
T30 |
301 |
| auto[1] |
auto[1] |
auto[0] |
1281497 |
1 |
|
|
T21 |
4 |
|
T29 |
45 |
|
T30 |
268 |
| auto[1] |
auto[1] |
auto[1] |
944055 |
1 |
|
|
T21 |
9 |
|
T29 |
44 |
|
T30 |
257 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |