Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6575049 |
1 |
|
|
T21 |
67 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4443445 |
1 |
|
|
T21 |
66 |
|
T29 |
118 |
|
T30 |
745 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9127096 |
1 |
|
|
T21 |
117 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1891398 |
1 |
|
|
T21 |
16 |
|
T29 |
43 |
|
T30 |
509 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6573113 |
1 |
|
|
T21 |
86 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4445381 |
1 |
|
|
T21 |
47 |
|
T29 |
110 |
|
T30 |
1040 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1277587 |
1 |
|
|
T21 |
12 |
|
T29 |
31 |
|
T30 |
343 |
| auto[1] |
auto[0] |
auto[1] |
947241 |
1 |
|
|
T21 |
6 |
|
T29 |
22 |
|
T30 |
337 |
| auto[1] |
auto[1] |
auto[0] |
1276396 |
1 |
|
|
T21 |
19 |
|
T29 |
36 |
|
T30 |
188 |
| auto[1] |
auto[1] |
auto[1] |
944157 |
1 |
|
|
T21 |
10 |
|
T29 |
21 |
|
T30 |
172 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |