Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6568849 |
1 |
|
|
T21 |
100 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4449645 |
1 |
|
|
T21 |
33 |
|
T29 |
130 |
|
T30 |
1235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9144460 |
1 |
|
|
T21 |
124 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1874034 |
1 |
|
|
T21 |
9 |
|
T29 |
40 |
|
T30 |
619 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6610973 |
1 |
|
|
T21 |
112 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4407521 |
1 |
|
|
T21 |
21 |
|
T29 |
93 |
|
T30 |
1289 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1257821 |
1 |
|
|
T21 |
8 |
|
T29 |
29 |
|
T30 |
307 |
| auto[1] |
auto[0] |
auto[1] |
938480 |
1 |
|
|
T21 |
4 |
|
T29 |
24 |
|
T30 |
283 |
| auto[1] |
auto[1] |
auto[0] |
1275666 |
1 |
|
|
T21 |
4 |
|
T29 |
24 |
|
T30 |
363 |
| auto[1] |
auto[1] |
auto[1] |
935554 |
1 |
|
|
T21 |
5 |
|
T29 |
16 |
|
T30 |
336 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |