Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6589494 |
1 |
|
|
T21 |
86 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4429000 |
1 |
|
|
T21 |
47 |
|
T29 |
163 |
|
T30 |
1023 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9117842 |
1 |
|
|
T21 |
123 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1900652 |
1 |
|
|
T21 |
10 |
|
T29 |
47 |
|
T30 |
514 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6553246 |
1 |
|
|
T21 |
99 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4465248 |
1 |
|
|
T21 |
34 |
|
T29 |
124 |
|
T30 |
1018 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1281427 |
1 |
|
|
T21 |
14 |
|
T29 |
25 |
|
T30 |
312 |
| auto[1] |
auto[0] |
auto[1] |
948818 |
1 |
|
|
T29 |
16 |
|
T30 |
334 |
|
T11 |
282 |
| auto[1] |
auto[1] |
auto[0] |
1283169 |
1 |
|
|
T21 |
10 |
|
T29 |
52 |
|
T30 |
192 |
| auto[1] |
auto[1] |
auto[1] |
951834 |
1 |
|
|
T21 |
10 |
|
T29 |
31 |
|
T30 |
180 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |