Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6574790 |
1 |
|
|
T21 |
98 |
|
T22 |
1 |
|
T23 |
1725 |
auto[1] |
4443704 |
1 |
|
|
T21 |
35 |
|
T29 |
96 |
|
T30 |
1517 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1938864 |
1 |
|
|
T21 |
11 |
|
T29 |
56 |
|
T30 |
747 |
auto[1] |
auto[0] |
auto[1] |
281188 |
1 |
|
|
T29 |
2 |
|
T30 |
181 |
|
T1 |
2 |
auto[1] |
auto[1] |
auto[0] |
1941250 |
1 |
|
|
T21 |
23 |
|
T29 |
37 |
|
T30 |
478 |
auto[1] |
auto[1] |
auto[1] |
282402 |
1 |
|
|
T21 |
1 |
|
T29 |
1 |
|
T30 |
111 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |