Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6601626 |
1 |
|
|
T21 |
94 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4416868 |
1 |
|
|
T21 |
39 |
|
T29 |
110 |
|
T30 |
785 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9133795 |
1 |
|
|
T21 |
103 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1884699 |
1 |
|
|
T21 |
30 |
|
T29 |
76 |
|
T30 |
599 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6591564 |
1 |
|
|
T21 |
97 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4426930 |
1 |
|
|
T21 |
36 |
|
T29 |
147 |
|
T30 |
1199 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1279711 |
1 |
|
|
T21 |
2 |
|
T29 |
38 |
|
T30 |
388 |
| auto[1] |
auto[0] |
auto[1] |
946039 |
1 |
|
|
T21 |
17 |
|
T29 |
60 |
|
T30 |
391 |
| auto[1] |
auto[1] |
auto[0] |
1262520 |
1 |
|
|
T21 |
4 |
|
T29 |
33 |
|
T30 |
212 |
| auto[1] |
auto[1] |
auto[1] |
938660 |
1 |
|
|
T21 |
13 |
|
T29 |
16 |
|
T30 |
208 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |