Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6597319 |
1 |
|
|
T21 |
83 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4421175 |
1 |
|
|
T21 |
50 |
|
T29 |
117 |
|
T30 |
1190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9137784 |
1 |
|
|
T21 |
123 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1880710 |
1 |
|
|
T21 |
10 |
|
T29 |
61 |
|
T30 |
559 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6599195 |
1 |
|
|
T21 |
114 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4419299 |
1 |
|
|
T21 |
19 |
|
T29 |
106 |
|
T30 |
1122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1271981 |
1 |
|
|
T21 |
9 |
|
T29 |
28 |
|
T30 |
250 |
| auto[1] |
auto[0] |
auto[1] |
942867 |
1 |
|
|
T21 |
2 |
|
T29 |
41 |
|
T30 |
259 |
| auto[1] |
auto[1] |
auto[0] |
1266608 |
1 |
|
|
T29 |
17 |
|
T30 |
313 |
|
T1 |
39 |
| auto[1] |
auto[1] |
auto[1] |
937843 |
1 |
|
|
T21 |
8 |
|
T29 |
20 |
|
T30 |
300 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |