Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6575712 |
1 |
|
|
T21 |
89 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4442782 |
1 |
|
|
T21 |
44 |
|
T29 |
104 |
|
T30 |
855 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9132598 |
1 |
|
|
T21 |
126 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1885896 |
1 |
|
|
T21 |
7 |
|
T29 |
72 |
|
T30 |
640 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6568964 |
1 |
|
|
T21 |
112 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4449530 |
1 |
|
|
T21 |
21 |
|
T29 |
140 |
|
T30 |
1196 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1275881 |
1 |
|
|
T21 |
9 |
|
T29 |
42 |
|
T30 |
342 |
| auto[1] |
auto[0] |
auto[1] |
945999 |
1 |
|
|
T21 |
6 |
|
T29 |
43 |
|
T30 |
429 |
| auto[1] |
auto[1] |
auto[0] |
1287753 |
1 |
|
|
T21 |
5 |
|
T29 |
26 |
|
T30 |
214 |
| auto[1] |
auto[1] |
auto[1] |
939897 |
1 |
|
|
T21 |
1 |
|
T29 |
29 |
|
T30 |
211 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |