Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6578409 |
1 |
|
|
T21 |
104 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4440085 |
1 |
|
|
T21 |
29 |
|
T29 |
137 |
|
T30 |
944 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9133916 |
1 |
|
|
T21 |
120 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1884578 |
1 |
|
|
T21 |
13 |
|
T29 |
57 |
|
T30 |
661 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6600072 |
1 |
|
|
T21 |
101 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4418422 |
1 |
|
|
T21 |
32 |
|
T29 |
105 |
|
T30 |
1386 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1274194 |
1 |
|
|
T21 |
15 |
|
T29 |
16 |
|
T30 |
504 |
| auto[1] |
auto[0] |
auto[1] |
947929 |
1 |
|
|
T21 |
11 |
|
T29 |
32 |
|
T30 |
445 |
| auto[1] |
auto[1] |
auto[0] |
1259650 |
1 |
|
|
T21 |
4 |
|
T29 |
32 |
|
T30 |
221 |
| auto[1] |
auto[1] |
auto[1] |
936649 |
1 |
|
|
T21 |
2 |
|
T29 |
25 |
|
T30 |
216 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |