Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6591104 |
1 |
|
|
T21 |
91 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4427390 |
1 |
|
|
T21 |
42 |
|
T29 |
132 |
|
T30 |
1248 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9117786 |
1 |
|
|
T21 |
119 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1900708 |
1 |
|
|
T21 |
14 |
|
T29 |
68 |
|
T30 |
623 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6525723 |
1 |
|
|
T21 |
106 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4492771 |
1 |
|
|
T21 |
27 |
|
T29 |
122 |
|
T30 |
1305 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1304242 |
1 |
|
|
T21 |
9 |
|
T29 |
19 |
|
T30 |
368 |
| auto[1] |
auto[0] |
auto[1] |
955828 |
1 |
|
|
T21 |
7 |
|
T29 |
25 |
|
T30 |
297 |
| auto[1] |
auto[1] |
auto[0] |
1287821 |
1 |
|
|
T21 |
4 |
|
T29 |
35 |
|
T30 |
314 |
| auto[1] |
auto[1] |
auto[1] |
944880 |
1 |
|
|
T21 |
7 |
|
T29 |
43 |
|
T30 |
326 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |