Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6573700 |
1 |
|
|
T21 |
95 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4444794 |
1 |
|
|
T21 |
38 |
|
T29 |
141 |
|
T30 |
939 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9138905 |
1 |
|
|
T21 |
125 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1879589 |
1 |
|
|
T21 |
8 |
|
T29 |
67 |
|
T30 |
445 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6601426 |
1 |
|
|
T21 |
119 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4417068 |
1 |
|
|
T21 |
14 |
|
T29 |
151 |
|
T30 |
888 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1273350 |
1 |
|
|
T29 |
20 |
|
T30 |
254 |
|
T1 |
30 |
| auto[1] |
auto[0] |
auto[1] |
942258 |
1 |
|
|
T21 |
6 |
|
T29 |
29 |
|
T30 |
237 |
| auto[1] |
auto[1] |
auto[0] |
1264129 |
1 |
|
|
T21 |
6 |
|
T29 |
64 |
|
T30 |
189 |
| auto[1] |
auto[1] |
auto[1] |
937331 |
1 |
|
|
T21 |
2 |
|
T29 |
38 |
|
T30 |
208 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |