Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6598371 |
1 |
|
|
T21 |
102 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4420123 |
1 |
|
|
T21 |
31 |
|
T29 |
66 |
|
T30 |
1168 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9126386 |
1 |
|
|
T21 |
116 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1892108 |
1 |
|
|
T21 |
17 |
|
T29 |
81 |
|
T30 |
632 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6564390 |
1 |
|
|
T21 |
111 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4454104 |
1 |
|
|
T21 |
22 |
|
T29 |
161 |
|
T30 |
1226 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1295265 |
1 |
|
|
T21 |
3 |
|
T29 |
61 |
|
T30 |
329 |
| auto[1] |
auto[0] |
auto[1] |
954398 |
1 |
|
|
T21 |
8 |
|
T29 |
53 |
|
T30 |
328 |
| auto[1] |
auto[1] |
auto[0] |
1266731 |
1 |
|
|
T21 |
2 |
|
T29 |
19 |
|
T30 |
265 |
| auto[1] |
auto[1] |
auto[1] |
937710 |
1 |
|
|
T21 |
9 |
|
T29 |
28 |
|
T30 |
304 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |