Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6573313 |
1 |
|
|
T21 |
88 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4445181 |
1 |
|
|
T21 |
45 |
|
T29 |
87 |
|
T30 |
722 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10459194 |
1 |
|
|
T21 |
133 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
559300 |
1 |
|
|
T29 |
8 |
|
T30 |
207 |
|
T1 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6593421 |
1 |
|
|
T21 |
125 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4425073 |
1 |
|
|
T21 |
8 |
|
T29 |
102 |
|
T30 |
1073 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1931933 |
1 |
|
|
T21 |
3 |
|
T29 |
54 |
|
T30 |
613 |
| auto[1] |
auto[0] |
auto[1] |
279071 |
1 |
|
|
T29 |
5 |
|
T30 |
143 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1933840 |
1 |
|
|
T21 |
5 |
|
T29 |
40 |
|
T30 |
253 |
| auto[1] |
auto[1] |
auto[1] |
280229 |
1 |
|
|
T29 |
3 |
|
T30 |
64 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |