Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6577805 |
1 |
|
|
T21 |
74 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4440689 |
1 |
|
|
T21 |
59 |
|
T29 |
89 |
|
T30 |
837 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9140159 |
1 |
|
|
T21 |
117 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
1878335 |
1 |
|
|
T21 |
16 |
|
T29 |
64 |
|
T30 |
365 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6606213 |
1 |
|
|
T21 |
105 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4412281 |
1 |
|
|
T21 |
28 |
|
T29 |
120 |
|
T30 |
782 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1272799 |
1 |
|
|
T21 |
7 |
|
T29 |
40 |
|
T30 |
311 |
| auto[1] |
auto[0] |
auto[1] |
938906 |
1 |
|
|
T21 |
8 |
|
T29 |
37 |
|
T30 |
271 |
| auto[1] |
auto[1] |
auto[0] |
1261147 |
1 |
|
|
T21 |
5 |
|
T29 |
16 |
|
T30 |
106 |
| auto[1] |
auto[1] |
auto[1] |
939429 |
1 |
|
|
T21 |
8 |
|
T29 |
27 |
|
T30 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |