Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6596383 |
1 |
|
|
T21 |
66 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4422111 |
1 |
|
|
T21 |
67 |
|
T29 |
129 |
|
T30 |
1151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10456508 |
1 |
|
|
T21 |
130 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
561986 |
1 |
|
|
T21 |
3 |
|
T29 |
6 |
|
T30 |
263 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6575977 |
1 |
|
|
T21 |
87 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4442517 |
1 |
|
|
T21 |
46 |
|
T29 |
124 |
|
T30 |
1291 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1942994 |
1 |
|
|
T21 |
11 |
|
T29 |
71 |
|
T30 |
586 |
| auto[1] |
auto[0] |
auto[1] |
282262 |
1 |
|
|
T21 |
1 |
|
T29 |
3 |
|
T30 |
154 |
| auto[1] |
auto[1] |
auto[0] |
1937537 |
1 |
|
|
T21 |
32 |
|
T29 |
47 |
|
T30 |
442 |
| auto[1] |
auto[1] |
auto[1] |
279724 |
1 |
|
|
T21 |
2 |
|
T29 |
3 |
|
T30 |
109 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |