Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6580167 |
1 |
|
|
T21 |
75 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4438327 |
1 |
|
|
T21 |
58 |
|
T29 |
172 |
|
T30 |
1115 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10457273 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
561221 |
1 |
|
|
T21 |
1 |
|
T29 |
5 |
|
T30 |
262 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6579813 |
1 |
|
|
T21 |
108 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4438681 |
1 |
|
|
T21 |
25 |
|
T29 |
101 |
|
T30 |
1329 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1948768 |
1 |
|
|
T21 |
17 |
|
T29 |
37 |
|
T30 |
570 |
| auto[1] |
auto[0] |
auto[1] |
281535 |
1 |
|
|
T29 |
2 |
|
T30 |
143 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1928692 |
1 |
|
|
T21 |
7 |
|
T29 |
59 |
|
T30 |
497 |
| auto[1] |
auto[1] |
auto[1] |
279686 |
1 |
|
|
T21 |
1 |
|
T29 |
3 |
|
T30 |
119 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |