Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6587246 |
1 |
|
|
T21 |
92 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4431248 |
1 |
|
|
T21 |
41 |
|
T29 |
91 |
|
T30 |
1402 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10456891 |
1 |
|
|
T21 |
130 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
561603 |
1 |
|
|
T21 |
3 |
|
T29 |
9 |
|
T30 |
150 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6581469 |
1 |
|
|
T21 |
98 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4437025 |
1 |
|
|
T21 |
35 |
|
T29 |
153 |
|
T30 |
816 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1946245 |
1 |
|
|
T21 |
22 |
|
T29 |
85 |
|
T30 |
322 |
| auto[1] |
auto[0] |
auto[1] |
282869 |
1 |
|
|
T21 |
3 |
|
T29 |
4 |
|
T30 |
70 |
| auto[1] |
auto[1] |
auto[0] |
1929177 |
1 |
|
|
T21 |
10 |
|
T29 |
59 |
|
T30 |
344 |
| auto[1] |
auto[1] |
auto[1] |
278734 |
1 |
|
|
T29 |
5 |
|
T30 |
80 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |