Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6582143 |
1 |
|
|
T21 |
72 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4436351 |
1 |
|
|
T21 |
61 |
|
T29 |
127 |
|
T30 |
1178 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10458611 |
1 |
|
|
T21 |
132 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
559883 |
1 |
|
|
T21 |
1 |
|
T29 |
7 |
|
T30 |
232 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6591865 |
1 |
|
|
T21 |
104 |
|
T22 |
1 |
|
T23 |
1725 |
| auto[1] |
4426629 |
1 |
|
|
T21 |
29 |
|
T29 |
113 |
|
T30 |
1229 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1938717 |
1 |
|
|
T21 |
11 |
|
T29 |
59 |
|
T30 |
454 |
| auto[1] |
auto[0] |
auto[1] |
280602 |
1 |
|
|
T21 |
1 |
|
T29 |
4 |
|
T30 |
107 |
| auto[1] |
auto[1] |
auto[0] |
1928029 |
1 |
|
|
T21 |
17 |
|
T29 |
47 |
|
T30 |
543 |
| auto[1] |
auto[1] |
auto[1] |
279281 |
1 |
|
|
T29 |
3 |
|
T30 |
125 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |