Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 938
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T764 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3585907567 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:03 PM PDT 24 22695945 ps
T86 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3171045241 Jun 28 04:43:49 PM PDT 24 Jun 28 04:43:52 PM PDT 24 39498362 ps
T765 /workspace/coverage/cover_reg_top/48.gpio_intr_test.4076431690 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:03 PM PDT 24 24684050 ps
T43 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3135631064 Jun 28 04:43:34 PM PDT 24 Jun 28 04:43:36 PM PDT 24 112372606 ps
T766 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1801504563 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:50 PM PDT 24 21664184 ps
T767 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1599521335 Jun 28 04:44:02 PM PDT 24 Jun 28 04:44:05 PM PDT 24 36668501 ps
T768 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2255991330 Jun 28 04:43:36 PM PDT 24 Jun 28 04:43:38 PM PDT 24 36227619 ps
T87 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2284624809 Jun 28 04:43:49 PM PDT 24 Jun 28 04:43:52 PM PDT 24 16817357 ps
T769 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4255299311 Jun 28 04:43:36 PM PDT 24 Jun 28 04:43:41 PM PDT 24 946408352 ps
T770 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.403011420 Jun 28 04:43:28 PM PDT 24 Jun 28 04:43:30 PM PDT 24 29135232 ps
T88 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.762415871 Jun 28 04:43:29 PM PDT 24 Jun 28 04:43:32 PM PDT 24 50027689 ps
T771 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2723185089 Jun 28 04:43:51 PM PDT 24 Jun 28 04:43:54 PM PDT 24 88588946 ps
T772 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4249893532 Jun 28 04:43:29 PM PDT 24 Jun 28 04:43:32 PM PDT 24 49758750 ps
T773 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2962142769 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:02 PM PDT 24 32441627 ps
T774 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2861778801 Jun 28 04:43:48 PM PDT 24 Jun 28 04:43:52 PM PDT 24 141068776 ps
T89 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3376357066 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:03 PM PDT 24 17178231 ps
T775 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2552175340 Jun 28 04:43:36 PM PDT 24 Jun 28 04:43:38 PM PDT 24 300753662 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1460240416 Jun 28 04:43:31 PM PDT 24 Jun 28 04:43:36 PM PDT 24 187018414 ps
T777 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4086995384 Jun 28 04:43:36 PM PDT 24 Jun 28 04:43:39 PM PDT 24 21262453 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2612685194 Jun 28 04:43:27 PM PDT 24 Jun 28 04:43:30 PM PDT 24 20745819 ps
T779 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1426697780 Jun 28 04:43:39 PM PDT 24 Jun 28 04:43:40 PM PDT 24 24687039 ps
T780 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3890635511 Jun 28 04:43:35 PM PDT 24 Jun 28 04:43:37 PM PDT 24 128823247 ps
T781 /workspace/coverage/cover_reg_top/31.gpio_intr_test.485827593 Jun 28 04:43:58 PM PDT 24 Jun 28 04:44:00 PM PDT 24 32973692 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3865206841 Jun 28 04:43:30 PM PDT 24 Jun 28 04:43:32 PM PDT 24 173613190 ps
T783 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2021049988 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:53 PM PDT 24 2072867431 ps
T784 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3764881314 Jun 28 04:43:34 PM PDT 24 Jun 28 04:43:35 PM PDT 24 110446660 ps
T785 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1717048919 Jun 28 04:43:48 PM PDT 24 Jun 28 04:43:51 PM PDT 24 17592759 ps
T47 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.327149128 Jun 28 04:43:27 PM PDT 24 Jun 28 04:43:30 PM PDT 24 364907956 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2283608149 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:49 PM PDT 24 41984202 ps
T787 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1302026119 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:03 PM PDT 24 19749864 ps
T788 /workspace/coverage/cover_reg_top/10.gpio_intr_test.448323519 Jun 28 04:43:45 PM PDT 24 Jun 28 04:43:47 PM PDT 24 43834764 ps
T789 /workspace/coverage/cover_reg_top/5.gpio_intr_test.69033972 Jun 28 04:43:40 PM PDT 24 Jun 28 04:43:41 PM PDT 24 11354697 ps
T790 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.194497603 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:02 PM PDT 24 87659743 ps
T791 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3994414974 Jun 28 04:43:56 PM PDT 24 Jun 28 04:43:57 PM PDT 24 16950687 ps
T792 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2793450758 Jun 28 04:43:48 PM PDT 24 Jun 28 04:43:51 PM PDT 24 59768352 ps
T793 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.16953370 Jun 28 04:43:29 PM PDT 24 Jun 28 04:43:32 PM PDT 24 35815899 ps
T90 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2238583801 Jun 28 04:43:35 PM PDT 24 Jun 28 04:43:39 PM PDT 24 58701833 ps
T794 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.89905832 Jun 28 04:43:31 PM PDT 24 Jun 28 04:43:33 PM PDT 24 13682183 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.163671349 Jun 28 04:43:34 PM PDT 24 Jun 28 04:43:38 PM PDT 24 265050353 ps
T796 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3136574000 Jun 28 04:43:35 PM PDT 24 Jun 28 04:43:38 PM PDT 24 62294981 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1470387680 Jun 28 04:43:25 PM PDT 24 Jun 28 04:43:27 PM PDT 24 76801319 ps
T798 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3506662851 Jun 28 04:43:31 PM PDT 24 Jun 28 04:43:33 PM PDT 24 65506701 ps
T44 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.426853554 Jun 28 04:43:46 PM PDT 24 Jun 28 04:43:49 PM PDT 24 370992155 ps
T799 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2285219854 Jun 28 04:43:35 PM PDT 24 Jun 28 04:43:37 PM PDT 24 16274481 ps
T800 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3195158660 Jun 28 04:43:38 PM PDT 24 Jun 28 04:43:40 PM PDT 24 37480012 ps
T801 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2504627866 Jun 28 04:43:46 PM PDT 24 Jun 28 04:43:51 PM PDT 24 521746400 ps
T802 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.309959509 Jun 28 04:43:27 PM PDT 24 Jun 28 04:43:30 PM PDT 24 77493133 ps
T803 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3964701827 Jun 28 04:43:45 PM PDT 24 Jun 28 04:43:48 PM PDT 24 15999249 ps
T804 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3566347099 Jun 28 04:43:36 PM PDT 24 Jun 28 04:43:40 PM PDT 24 247231903 ps
T805 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3257584063 Jun 28 04:43:58 PM PDT 24 Jun 28 04:44:00 PM PDT 24 10972055 ps
T806 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1463282501 Jun 28 04:43:45 PM PDT 24 Jun 28 04:43:48 PM PDT 24 41590889 ps
T807 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3006885535 Jun 28 04:43:58 PM PDT 24 Jun 28 04:44:01 PM PDT 24 11968285 ps
T808 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2733213237 Jun 28 04:43:56 PM PDT 24 Jun 28 04:43:57 PM PDT 24 164377842 ps
T809 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.822568161 Jun 28 04:43:28 PM PDT 24 Jun 28 04:43:30 PM PDT 24 23486322 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1877346626 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:50 PM PDT 24 32073664 ps
T811 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3088997654 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:52 PM PDT 24 185772672 ps
T812 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2271828896 Jun 28 04:44:05 PM PDT 24 Jun 28 04:44:06 PM PDT 24 24314624 ps
T813 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4253991341 Jun 28 04:43:36 PM PDT 24 Jun 28 04:43:39 PM PDT 24 34228734 ps
T91 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.428445520 Jun 28 04:43:26 PM PDT 24 Jun 28 04:43:28 PM PDT 24 57241367 ps
T814 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1882554138 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:04 PM PDT 24 67373896 ps
T815 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1911500281 Jun 28 04:44:02 PM PDT 24 Jun 28 04:44:05 PM PDT 24 49118896 ps
T93 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2636070737 Jun 28 04:43:48 PM PDT 24 Jun 28 04:43:51 PM PDT 24 57191955 ps
T92 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2623109091 Jun 28 04:43:29 PM PDT 24 Jun 28 04:43:32 PM PDT 24 15003185 ps
T816 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3058744386 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:01 PM PDT 24 44362954 ps
T817 /workspace/coverage/cover_reg_top/46.gpio_intr_test.481486294 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:01 PM PDT 24 26394679 ps
T818 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1943699006 Jun 28 04:43:34 PM PDT 24 Jun 28 04:43:35 PM PDT 24 16933439 ps
T819 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2741178725 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:51 PM PDT 24 47714767 ps
T45 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.468423120 Jun 28 04:43:46 PM PDT 24 Jun 28 04:43:49 PM PDT 24 75228789 ps
T820 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.566133109 Jun 28 04:43:33 PM PDT 24 Jun 28 04:43:37 PM PDT 24 224732205 ps
T821 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3304884188 Jun 28 04:43:48 PM PDT 24 Jun 28 04:43:51 PM PDT 24 84098965 ps
T822 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2838284422 Jun 28 04:43:35 PM PDT 24 Jun 28 04:43:37 PM PDT 24 14011560 ps
T823 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.546938944 Jun 28 04:43:37 PM PDT 24 Jun 28 04:43:40 PM PDT 24 77837433 ps
T824 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2609381999 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:50 PM PDT 24 356049430 ps
T825 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3391659951 Jun 28 04:43:57 PM PDT 24 Jun 28 04:43:59 PM PDT 24 32447827 ps
T826 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.796875621 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:51 PM PDT 24 166205486 ps
T827 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3936236718 Jun 28 04:43:39 PM PDT 24 Jun 28 04:43:41 PM PDT 24 76434043 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1977891677 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:50 PM PDT 24 61281857 ps
T829 /workspace/coverage/cover_reg_top/2.gpio_intr_test.440768733 Jun 28 04:43:29 PM PDT 24 Jun 28 04:43:32 PM PDT 24 99879174 ps
T830 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2684375354 Jun 28 04:43:41 PM PDT 24 Jun 28 04:43:42 PM PDT 24 14501784 ps
T831 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3133047482 Jun 28 04:43:47 PM PDT 24 Jun 28 04:43:50 PM PDT 24 22495460 ps
T832 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4048550484 Jun 28 04:43:50 PM PDT 24 Jun 28 04:43:52 PM PDT 24 110115151 ps
T833 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1560197035 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:02 PM PDT 24 40705189 ps
T834 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.828280163 Jun 28 04:43:50 PM PDT 24 Jun 28 04:43:54 PM PDT 24 100408256 ps
T835 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2680057141 Jun 28 04:43:38 PM PDT 24 Jun 28 04:43:41 PM PDT 24 247756362 ps
T836 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1474501071 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:03 PM PDT 24 15168432 ps
T105 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3336964293 Jun 28 04:43:28 PM PDT 24 Jun 28 04:43:31 PM PDT 24 502595034 ps
T837 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3915863942 Jun 28 04:43:29 PM PDT 24 Jun 28 04:43:34 PM PDT 24 54953918 ps
T838 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3071321039 Jun 28 04:43:49 PM PDT 24 Jun 28 04:43:53 PM PDT 24 72585782 ps
T839 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4047372858 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:16 PM PDT 24 83153319 ps
T840 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2925306188 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:13 PM PDT 24 177053094 ps
T841 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.351902943 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:18 PM PDT 24 78081761 ps
T842 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1330014482 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:15 PM PDT 24 470372235 ps
T843 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.30478971 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:03 PM PDT 24 67408921 ps
T844 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1756429340 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:18 PM PDT 24 320801679 ps
T845 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4047618551 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:03 PM PDT 24 28668977 ps
T846 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2377580769 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:14 PM PDT 24 45026784 ps
T847 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2044172695 Jun 28 04:44:08 PM PDT 24 Jun 28 04:44:10 PM PDT 24 29869056 ps
T848 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.119015167 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:14 PM PDT 24 80259527 ps
T849 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3520876940 Jun 28 04:44:06 PM PDT 24 Jun 28 04:44:08 PM PDT 24 33613745 ps
T850 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3889688738 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:18 PM PDT 24 84577240 ps
T851 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.872507793 Jun 28 04:44:07 PM PDT 24 Jun 28 04:44:09 PM PDT 24 39822452 ps
T852 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.793392121 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:14 PM PDT 24 147160471 ps
T853 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1013761983 Jun 28 04:44:07 PM PDT 24 Jun 28 04:44:08 PM PDT 24 33829079 ps
T854 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1840595614 Jun 28 04:44:07 PM PDT 24 Jun 28 04:44:09 PM PDT 24 104868923 ps
T855 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.624409657 Jun 28 04:44:01 PM PDT 24 Jun 28 04:44:05 PM PDT 24 127822806 ps
T856 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.858947607 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:03 PM PDT 24 178478509 ps
T857 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.274596907 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:18 PM PDT 24 130710052 ps
T858 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2628316816 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:15 PM PDT 24 176407235 ps
T859 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.780032837 Jun 28 04:44:08 PM PDT 24 Jun 28 04:44:11 PM PDT 24 96409848 ps
T860 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2551820583 Jun 28 04:44:08 PM PDT 24 Jun 28 04:44:10 PM PDT 24 204595515 ps
T861 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623168438 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:18 PM PDT 24 57759429 ps
T862 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.780279748 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:04 PM PDT 24 50816658 ps
T863 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1375291304 Jun 28 04:44:08 PM PDT 24 Jun 28 04:44:10 PM PDT 24 159353638 ps
T864 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.676543187 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:18 PM PDT 24 46396373 ps
T865 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.699529747 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:19 PM PDT 24 35609594 ps
T866 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1428645111 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:14 PM PDT 24 110652669 ps
T867 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3328979141 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:15 PM PDT 24 27591286 ps
T868 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2991802109 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:17 PM PDT 24 57078394 ps
T869 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2640788788 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:13 PM PDT 24 103090376 ps
T870 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.852375245 Jun 28 04:44:06 PM PDT 24 Jun 28 04:44:08 PM PDT 24 202575980 ps
T871 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.80509415 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:17 PM PDT 24 140875203 ps
T872 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1814586221 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:15 PM PDT 24 55909610 ps
T873 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.642191987 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:16 PM PDT 24 39119230 ps
T874 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.637717057 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:16 PM PDT 24 42215833 ps
T875 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3409314800 Jun 28 04:44:14 PM PDT 24 Jun 28 04:44:19 PM PDT 24 148483507 ps
T876 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.847807355 Jun 28 04:44:02 PM PDT 24 Jun 28 04:44:05 PM PDT 24 59636145 ps
T877 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3968990731 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:19 PM PDT 24 137818863 ps
T878 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3953406831 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:17 PM PDT 24 181326483 ps
T879 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3317389320 Jun 28 04:44:01 PM PDT 24 Jun 28 04:44:05 PM PDT 24 187771725 ps
T880 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3711585756 Jun 28 04:44:08 PM PDT 24 Jun 28 04:44:11 PM PDT 24 316092390 ps
T881 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.118903374 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:18 PM PDT 24 57364502 ps
T882 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.21938493 Jun 28 04:44:14 PM PDT 24 Jun 28 04:44:19 PM PDT 24 386974639 ps
T883 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3873378725 Jun 28 04:44:07 PM PDT 24 Jun 28 04:44:10 PM PDT 24 123014501 ps
T884 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4273514079 Jun 28 04:44:14 PM PDT 24 Jun 28 04:44:19 PM PDT 24 274470433 ps
T885 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3701764480 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:03 PM PDT 24 659639850 ps
T886 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.110973426 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:14 PM PDT 24 53455815 ps
T887 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.662899079 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:13 PM PDT 24 80894649 ps
T888 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.332008542 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:13 PM PDT 24 127677549 ps
T889 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1502667588 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:16 PM PDT 24 32341235 ps
T890 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3215742942 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:12 PM PDT 24 35740828 ps
T891 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1078281850 Jun 28 04:44:08 PM PDT 24 Jun 28 04:44:10 PM PDT 24 49939651 ps
T892 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3810589729 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:14 PM PDT 24 30127064 ps
T893 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1471884621 Jun 28 04:44:14 PM PDT 24 Jun 28 04:44:19 PM PDT 24 83176089 ps
T894 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1134087144 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:18 PM PDT 24 54853658 ps
T895 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2892609367 Jun 28 04:43:56 PM PDT 24 Jun 28 04:43:57 PM PDT 24 84229009 ps
T896 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2601208578 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:04 PM PDT 24 111230874 ps
T897 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.139661288 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:13 PM PDT 24 112241781 ps
T898 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4238071409 Jun 28 04:44:14 PM PDT 24 Jun 28 04:44:19 PM PDT 24 155648720 ps
T899 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4182837851 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:13 PM PDT 24 104458924 ps
T900 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2738770270 Jun 28 04:44:02 PM PDT 24 Jun 28 04:44:05 PM PDT 24 118930767 ps
T901 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1471382239 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:18 PM PDT 24 137715139 ps
T902 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1621668375 Jun 28 04:44:08 PM PDT 24 Jun 28 04:44:11 PM PDT 24 31453541 ps
T903 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1978319855 Jun 28 04:44:10 PM PDT 24 Jun 28 04:44:14 PM PDT 24 54912871 ps
T904 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4144225085 Jun 28 04:44:06 PM PDT 24 Jun 28 04:44:08 PM PDT 24 208009421 ps
T905 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2608615439 Jun 28 04:43:58 PM PDT 24 Jun 28 04:44:01 PM PDT 24 57424535 ps
T906 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1491474591 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:04 PM PDT 24 269054664 ps
T907 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.571228465 Jun 28 04:43:58 PM PDT 24 Jun 28 04:44:01 PM PDT 24 52281518 ps
T908 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1975095330 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:16 PM PDT 24 185220582 ps
T909 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.445040718 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:03 PM PDT 24 44085822 ps
T910 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3375528136 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:02 PM PDT 24 45907506 ps
T911 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.408079110 Jun 28 04:44:01 PM PDT 24 Jun 28 04:44:05 PM PDT 24 37536117 ps
T912 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1076303833 Jun 28 04:44:12 PM PDT 24 Jun 28 04:44:18 PM PDT 24 123268205 ps
T913 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3791634660 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:19 PM PDT 24 108527195 ps
T914 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2463874088 Jun 28 04:44:01 PM PDT 24 Jun 28 04:44:05 PM PDT 24 113195350 ps
T915 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1513367413 Jun 28 04:44:01 PM PDT 24 Jun 28 04:44:05 PM PDT 24 322976545 ps
T916 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1042608922 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:04 PM PDT 24 38372876 ps
T917 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1274757859 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:12 PM PDT 24 89271228 ps
T918 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1301446979 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:18 PM PDT 24 243985472 ps
T919 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1747078294 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:16 PM PDT 24 84779309 ps
T920 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1411505078 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:18 PM PDT 24 149866072 ps
T921 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2909285934 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:13 PM PDT 24 80724194 ps
T922 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.248435550 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:13 PM PDT 24 184394013 ps
T923 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3761755149 Jun 28 04:44:14 PM PDT 24 Jun 28 04:44:19 PM PDT 24 254328136 ps
T924 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3764778756 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:04 PM PDT 24 36696696 ps
T925 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4041552314 Jun 28 04:44:14 PM PDT 24 Jun 28 04:44:20 PM PDT 24 52127491 ps
T926 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.402114667 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:02 PM PDT 24 65213582 ps
T927 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.372234926 Jun 28 04:44:08 PM PDT 24 Jun 28 04:44:10 PM PDT 24 177135462 ps
T928 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1412918159 Jun 28 04:44:07 PM PDT 24 Jun 28 04:44:10 PM PDT 24 43764219 ps
T929 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1952117404 Jun 28 04:43:59 PM PDT 24 Jun 28 04:44:03 PM PDT 24 348679394 ps
T930 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.273406135 Jun 28 04:44:00 PM PDT 24 Jun 28 04:44:04 PM PDT 24 84835448 ps
T931 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3974519970 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:11 PM PDT 24 55824853 ps
T932 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1633413326 Jun 28 04:44:13 PM PDT 24 Jun 28 04:44:19 PM PDT 24 69889806 ps
T933 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2308244385 Jun 28 04:44:07 PM PDT 24 Jun 28 04:44:09 PM PDT 24 70329061 ps
T934 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1822919931 Jun 28 04:44:01 PM PDT 24 Jun 28 04:44:05 PM PDT 24 248055581 ps
T935 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.235406625 Jun 28 04:44:05 PM PDT 24 Jun 28 04:44:07 PM PDT 24 145028785 ps
T936 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.6631798 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:13 PM PDT 24 43907742 ps
T937 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.58921203 Jun 28 04:44:11 PM PDT 24 Jun 28 04:44:16 PM PDT 24 176801967 ps
T938 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2455482763 Jun 28 04:44:09 PM PDT 24 Jun 28 04:44:14 PM PDT 24 335675242 ps

Test location /workspace/coverage/default/8.gpio_full_random.1109731458
Short name T21
Test name
Test status
Simulation time 77507821 ps
CPU time 1.01 seconds
Started Jun 28 04:47:16 PM PDT 24
Finished Jun 28 04:47:18 PM PDT 24
Peak memory 198580 kb
Host smart-0972fe0f-b557-436a-a380-df5cbd372327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109731458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1109731458
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2466302852
Short name T23
Test name
Test status
Simulation time 357532172 ps
CPU time 3.65 seconds
Started Jun 28 04:47:59 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 198696 kb
Host smart-ed70dd80-58d8-4b18-94ba-44ace014062c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466302852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2466302852
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2921761475
Short name T31
Test name
Test status
Simulation time 35837263176 ps
CPU time 1070.81 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 05:04:53 PM PDT 24
Peak memory 198896 kb
Host smart-8d422c4c-f804-4942-a221-288aff54baf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2921761475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2921761475
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3078930063
Short name T2
Test name
Test status
Simulation time 3638942608 ps
CPU time 4.46 seconds
Started Jun 28 04:48:09 PM PDT 24
Finished Jun 28 04:48:15 PM PDT 24
Peak memory 198632 kb
Host smart-da25dda1-1b5d-4daa-b1e1-ce9cc3eb3ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078930063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3078930063
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1905063578
Short name T37
Test name
Test status
Simulation time 370076633 ps
CPU time 0.94 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 215252 kb
Host smart-380b05aa-7ef7-44c1-b659-1a68061d2cc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905063578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1905063578
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3220756062
Short name T35
Test name
Test status
Simulation time 441363997 ps
CPU time 1.44 seconds
Started Jun 28 04:43:50 PM PDT 24
Finished Jun 28 04:43:53 PM PDT 24
Peak memory 198592 kb
Host smart-01a9e0ef-902c-4ffd-ab77-5b6d5a0340e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220756062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3220756062
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.543146152
Short name T82
Test name
Test status
Simulation time 91938448 ps
CPU time 0.85 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 196460 kb
Host smart-31b65c0f-75f2-4955-a7d7-b301ba3af929
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543146152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.543146152
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2242086082
Short name T40
Test name
Test status
Simulation time 113107834 ps
CPU time 0.57 seconds
Started Jun 28 04:46:56 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 195380 kb
Host smart-ae2c61de-be95-468b-9c29-3ab0b39668ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242086082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2242086082
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1743940496
Short name T99
Test name
Test status
Simulation time 356837218 ps
CPU time 0.77 seconds
Started Jun 28 04:43:24 PM PDT 24
Finished Jun 28 04:43:26 PM PDT 24
Peak memory 197020 kb
Host smart-7e52255a-f640-4ee6-83d0-0b3908c61986
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743940496 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1743940496
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.426853554
Short name T44
Test name
Test status
Simulation time 370992155 ps
CPU time 1.39 seconds
Started Jun 28 04:43:46 PM PDT 24
Finished Jun 28 04:43:49 PM PDT 24
Peak memory 198596 kb
Host smart-deb47297-fece-469d-b242-76aada636d98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426853554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.426853554
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.595379298
Short name T41
Test name
Test status
Simulation time 102074272 ps
CPU time 1.37 seconds
Started Jun 28 04:43:57 PM PDT 24
Finished Jun 28 04:43:59 PM PDT 24
Peak memory 198644 kb
Host smart-415466d2-3f5d-48c9-b7fc-c9a0f0375753
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595379298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.595379298
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.428445520
Short name T91
Test name
Test status
Simulation time 57241367 ps
CPU time 0.78 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 196760 kb
Host smart-9658e305-0699-46b1-a230-8092b76753d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428445520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.428445520
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1796321652
Short name T760
Test name
Test status
Simulation time 97547109 ps
CPU time 1.5 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:29 PM PDT 24
Peak memory 197324 kb
Host smart-476d187c-c332-4160-b5e8-0af6080bc8fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796321652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1796321652
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.822568161
Short name T809
Test name
Test status
Simulation time 23486322 ps
CPU time 0.64 seconds
Started Jun 28 04:43:28 PM PDT 24
Finished Jun 28 04:43:30 PM PDT 24
Peak memory 195708 kb
Host smart-7fe9e6b9-0fa8-423a-83ae-2bdab5350141
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822568161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.822568161
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3023689759
Short name T755
Test name
Test status
Simulation time 26279669 ps
CPU time 0.82 seconds
Started Jun 28 04:43:25 PM PDT 24
Finished Jun 28 04:43:27 PM PDT 24
Peak memory 198532 kb
Host smart-29700d82-de2d-49dc-8149-1064384e2b67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023689759 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3023689759
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.982654824
Short name T75
Test name
Test status
Simulation time 44570079 ps
CPU time 0.6 seconds
Started Jun 28 04:43:28 PM PDT 24
Finished Jun 28 04:43:30 PM PDT 24
Peak memory 195424 kb
Host smart-a7dcff02-5279-4c81-b86d-4e93b776db52
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982654824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.982654824
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3764881314
Short name T784
Test name
Test status
Simulation time 110446660 ps
CPU time 0.57 seconds
Started Jun 28 04:43:34 PM PDT 24
Finished Jun 28 04:43:35 PM PDT 24
Peak memory 194240 kb
Host smart-43f3e7c6-0c8e-46db-a686-65e5fc170b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764881314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3764881314
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2291160645
Short name T730
Test name
Test status
Simulation time 64422595 ps
CPU time 1.61 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:29 PM PDT 24
Peak memory 198632 kb
Host smart-c4888f92-8054-4369-abc6-831df9aba5db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291160645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2291160645
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.309959509
Short name T802
Test name
Test status
Simulation time 77493133 ps
CPU time 0.86 seconds
Started Jun 28 04:43:27 PM PDT 24
Finished Jun 28 04:43:30 PM PDT 24
Peak memory 197868 kb
Host smart-6a51e7f3-0bc9-4ba0-bb1e-3adf3d32ed77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309959509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.309959509
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1622564542
Short name T757
Test name
Test status
Simulation time 61203283 ps
CPU time 0.76 seconds
Started Jun 28 04:43:30 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 196920 kb
Host smart-cbeaf32e-c96b-4faf-878a-ef20f84534f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622564542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1622564542
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.153987430
Short name T81
Test name
Test status
Simulation time 155645414 ps
CPU time 2.94 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:30 PM PDT 24
Peak memory 197944 kb
Host smart-2b07c251-5d18-4bb2-a6d7-5257463c9aa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153987430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.153987430
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2623109091
Short name T92
Test name
Test status
Simulation time 15003185 ps
CPU time 0.65 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 195332 kb
Host smart-bc5a1178-884a-433f-b7f9-b1e67bfabf7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623109091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2623109091
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3506662851
Short name T798
Test name
Test status
Simulation time 65506701 ps
CPU time 1.02 seconds
Started Jun 28 04:43:31 PM PDT 24
Finished Jun 28 04:43:33 PM PDT 24
Peak memory 198624 kb
Host smart-0bda72b5-81c5-417c-be02-99e6e1c8c7fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506662851 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3506662851
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1677468174
Short name T85
Test name
Test status
Simulation time 48773521 ps
CPU time 0.6 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 195360 kb
Host smart-4f92815b-daa1-461a-bfad-e177436dfc95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677468174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1677468174
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2092881994
Short name T737
Test name
Test status
Simulation time 20347954 ps
CPU time 0.68 seconds
Started Jun 28 04:43:33 PM PDT 24
Finished Jun 28 04:43:34 PM PDT 24
Peak memory 194404 kb
Host smart-e6f6f0d7-a673-48ea-9d50-bb9aab90fcd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092881994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2092881994
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.403011420
Short name T770
Test name
Test status
Simulation time 29135232 ps
CPU time 0.73 seconds
Started Jun 28 04:43:28 PM PDT 24
Finished Jun 28 04:43:30 PM PDT 24
Peak memory 195492 kb
Host smart-a1cc905e-074a-4def-9734-2c34dd2e26c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403011420 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.403011420
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1460240416
Short name T776
Test name
Test status
Simulation time 187018414 ps
CPU time 3.33 seconds
Started Jun 28 04:43:31 PM PDT 24
Finished Jun 28 04:43:36 PM PDT 24
Peak memory 198980 kb
Host smart-abaff25d-837b-4511-a7d0-965808ad8ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460240416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1460240416
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.327149128
Short name T47
Test name
Test status
Simulation time 364907956 ps
CPU time 1.35 seconds
Started Jun 28 04:43:27 PM PDT 24
Finished Jun 28 04:43:30 PM PDT 24
Peak memory 198600 kb
Host smart-4e3b1321-40ec-4c19-8367-97de0efb9edd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327149128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.327149128
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1463282501
Short name T806
Test name
Test status
Simulation time 41590889 ps
CPU time 0.98 seconds
Started Jun 28 04:43:45 PM PDT 24
Finished Jun 28 04:43:48 PM PDT 24
Peak memory 198496 kb
Host smart-912e2743-9b33-483e-bbec-6103a52d3383
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463282501 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1463282501
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2285219854
Short name T799
Test name
Test status
Simulation time 16274481 ps
CPU time 0.6 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:37 PM PDT 24
Peak memory 195824 kb
Host smart-b294879b-e032-4a74-96b4-c182388bcb96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285219854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2285219854
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.448323519
Short name T788
Test name
Test status
Simulation time 43834764 ps
CPU time 0.62 seconds
Started Jun 28 04:43:45 PM PDT 24
Finished Jun 28 04:43:47 PM PDT 24
Peak memory 194424 kb
Host smart-1372d2b8-d82b-43ad-b053-593c8edeb8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448323519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.448323519
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4086995384
Short name T777
Test name
Test status
Simulation time 21262453 ps
CPU time 0.71 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:39 PM PDT 24
Peak memory 195416 kb
Host smart-acde87a9-aaaf-4857-8099-93f06e4a998c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086995384 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.4086995384
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2021049988
Short name T783
Test name
Test status
Simulation time 2072867431 ps
CPU time 2.88 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:53 PM PDT 24
Peak memory 198520 kb
Host smart-292732b7-cb95-444c-891a-3d23c48b0ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021049988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2021049988
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2823108436
Short name T49
Test name
Test status
Simulation time 37469692 ps
CPU time 0.88 seconds
Started Jun 28 04:43:46 PM PDT 24
Finished Jun 28 04:43:48 PM PDT 24
Peak memory 197800 kb
Host smart-dd864200-aa80-4daf-a261-dda6e4e18b64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823108436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2823108436
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2861778801
Short name T774
Test name
Test status
Simulation time 141068776 ps
CPU time 1 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 198592 kb
Host smart-e42562b6-572f-48e0-a998-4decfe5e2bee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861778801 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2861778801
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3384249718
Short name T104
Test name
Test status
Simulation time 12874831 ps
CPU time 0.63 seconds
Started Jun 28 04:43:49 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 195776 kb
Host smart-a0a907cd-6775-4df2-9cd1-b83488072f4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384249718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3384249718
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1246315081
Short name T763
Test name
Test status
Simulation time 18492905 ps
CPU time 0.61 seconds
Started Jun 28 04:43:51 PM PDT 24
Finished Jun 28 04:43:53 PM PDT 24
Peak memory 194296 kb
Host smart-fab5cc5c-375b-457e-9345-13048c069796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246315081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1246315081
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3038358883
Short name T100
Test name
Test status
Simulation time 72685345 ps
CPU time 0.78 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 196876 kb
Host smart-d66078f3-f536-4f7f-869b-177f258ac032
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038358883 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3038358883
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.828280163
Short name T834
Test name
Test status
Simulation time 100408256 ps
CPU time 2.17 seconds
Started Jun 28 04:43:50 PM PDT 24
Finished Jun 28 04:43:54 PM PDT 24
Peak memory 198692 kb
Host smart-2694b30d-86f0-4167-bfa7-aadce52c3dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828280163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.828280163
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.796875621
Short name T826
Test name
Test status
Simulation time 166205486 ps
CPU time 0.91 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 197832 kb
Host smart-bc12788f-30cf-4121-9199-62c5b9456e10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796875621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.796875621
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4123347524
Short name T731
Test name
Test status
Simulation time 33337991 ps
CPU time 0.86 seconds
Started Jun 28 04:43:49 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 198524 kb
Host smart-87453dc1-461b-4a7b-8c75-493e7b925603
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123347524 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.4123347524
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1935565385
Short name T102
Test name
Test status
Simulation time 22347455 ps
CPU time 0.61 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 195120 kb
Host smart-30b2751b-93b0-4aa1-a0ac-a158f79d3d98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935565385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1935565385
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.755666911
Short name T729
Test name
Test status
Simulation time 17239503 ps
CPU time 0.65 seconds
Started Jun 28 04:43:50 PM PDT 24
Finished Jun 28 04:43:53 PM PDT 24
Peak memory 194284 kb
Host smart-423b7104-9506-448a-9410-51d186c2fd42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755666911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.755666911
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2793450758
Short name T792
Test name
Test status
Simulation time 59768352 ps
CPU time 0.88 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 196916 kb
Host smart-333e1129-162f-4aa2-bebd-6a91b7ee9ad3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793450758 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2793450758
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2504627866
Short name T801
Test name
Test status
Simulation time 521746400 ps
CPU time 3.03 seconds
Started Jun 28 04:43:46 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 198576 kb
Host smart-d072df17-5006-4d19-99d9-f31de79e3ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504627866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2504627866
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2609381999
Short name T824
Test name
Test status
Simulation time 356049430 ps
CPU time 1.09 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:50 PM PDT 24
Peak memory 198716 kb
Host smart-4265ee04-2ee2-4eaf-8ff7-866d080cf1ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609381999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2609381999
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2451590997
Short name T732
Test name
Test status
Simulation time 16485914 ps
CPU time 0.66 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 197348 kb
Host smart-75717c80-7652-4600-ab42-db2bd0d3bbc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451590997 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2451590997
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2636070737
Short name T93
Test name
Test status
Simulation time 57191955 ps
CPU time 0.64 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 195580 kb
Host smart-a6f66840-d691-42cf-8773-3316812a1210
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636070737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2636070737
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3964701827
Short name T803
Test name
Test status
Simulation time 15999249 ps
CPU time 0.63 seconds
Started Jun 28 04:43:45 PM PDT 24
Finished Jun 28 04:43:48 PM PDT 24
Peak memory 195256 kb
Host smart-74e879ea-5a20-415e-93bb-f73b1469221f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964701827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3964701827
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3659802629
Short name T97
Test name
Test status
Simulation time 90694132 ps
CPU time 0.79 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 196872 kb
Host smart-bcb3fbf7-a3c3-4d25-9cef-bfd27639e179
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659802629 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3659802629
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3071321039
Short name T838
Test name
Test status
Simulation time 72585782 ps
CPU time 1.35 seconds
Started Jun 28 04:43:49 PM PDT 24
Finished Jun 28 04:43:53 PM PDT 24
Peak memory 198568 kb
Host smart-85cb2576-21e8-4dd9-8345-76b1ed9e31e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071321039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3071321039
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2283608149
Short name T786
Test name
Test status
Simulation time 41984202 ps
CPU time 1 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:49 PM PDT 24
Peak memory 198528 kb
Host smart-b8b495e6-918a-4047-a149-1cf9a0bc3b34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283608149 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2283608149
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3171045241
Short name T86
Test name
Test status
Simulation time 39498362 ps
CPU time 0.61 seconds
Started Jun 28 04:43:49 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 195216 kb
Host smart-9114fce3-ec90-4480-b1de-b43f5a79972b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171045241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3171045241
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4048550484
Short name T832
Test name
Test status
Simulation time 110115151 ps
CPU time 0.61 seconds
Started Jun 28 04:43:50 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 194428 kb
Host smart-6bf9bd07-c64f-498d-8566-635f5346982f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048550484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4048550484
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3133047482
Short name T831
Test name
Test status
Simulation time 22495460 ps
CPU time 0.91 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:50 PM PDT 24
Peak memory 197920 kb
Host smart-34c5d049-55e9-4dcf-a365-7f9469bf9a01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133047482 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3133047482
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2723185089
Short name T771
Test name
Test status
Simulation time 88588946 ps
CPU time 1.27 seconds
Started Jun 28 04:43:51 PM PDT 24
Finished Jun 28 04:43:54 PM PDT 24
Peak memory 198480 kb
Host smart-da1641c1-f60d-4c40-93a9-f3765b9eb749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723185089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2723185089
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3715739783
Short name T48
Test name
Test status
Simulation time 80706963 ps
CPU time 0.89 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 197448 kb
Host smart-12450da9-4265-4c18-97b7-e8835124b5f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715739783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3715739783
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1801504563
Short name T766
Test name
Test status
Simulation time 21664184 ps
CPU time 0.74 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:50 PM PDT 24
Peak memory 198616 kb
Host smart-7947c884-f32c-4ca0-a47b-36c80290972d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801504563 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1801504563
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1641861543
Short name T734
Test name
Test status
Simulation time 41771988 ps
CPU time 0.6 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:49 PM PDT 24
Peak memory 195812 kb
Host smart-d1ec2a9a-4954-48e6-a175-91961e8844ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641861543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1641861543
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2741178725
Short name T819
Test name
Test status
Simulation time 47714767 ps
CPU time 0.59 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 194360 kb
Host smart-9a4ea06e-c25e-41a8-b8d6-9a058df28d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741178725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2741178725
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1977891677
Short name T828
Test name
Test status
Simulation time 61281857 ps
CPU time 0.86 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:50 PM PDT 24
Peak memory 196840 kb
Host smart-634f601c-9465-4bff-a157-d4ef54d05479
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977891677 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1977891677
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3088997654
Short name T811
Test name
Test status
Simulation time 185772672 ps
CPU time 2.98 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 198688 kb
Host smart-ae26b3aa-f992-4bc4-b397-64e7dddb86ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088997654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3088997654
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2766580389
Short name T50
Test name
Test status
Simulation time 250583983 ps
CPU time 1.13 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 198696 kb
Host smart-d7513aa1-33aa-4188-afc3-85807bd781d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766580389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2766580389
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1717048919
Short name T785
Test name
Test status
Simulation time 17592759 ps
CPU time 1.01 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 198592 kb
Host smart-e685f767-2674-4e3b-af85-ab70e889b3be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717048919 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1717048919
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3304884188
Short name T821
Test name
Test status
Simulation time 84098965 ps
CPU time 0.64 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:51 PM PDT 24
Peak memory 195544 kb
Host smart-fa5816d4-b680-41df-91b7-9dcf8cf9bc18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304884188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3304884188
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3535306298
Short name T754
Test name
Test status
Simulation time 13016244 ps
CPU time 0.58 seconds
Started Jun 28 04:43:46 PM PDT 24
Finished Jun 28 04:43:48 PM PDT 24
Peak memory 195068 kb
Host smart-e78092c8-6c05-489b-b048-ed53caf3888f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535306298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3535306298
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.433951253
Short name T98
Test name
Test status
Simulation time 33949434 ps
CPU time 0.81 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:50 PM PDT 24
Peak memory 197048 kb
Host smart-426710c9-975f-40ee-a80c-4b1932c038c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433951253 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.433951253
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2994177627
Short name T751
Test name
Test status
Simulation time 44627688 ps
CPU time 2.28 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 198664 kb
Host smart-36d53bba-69a3-4c34-9e6e-2d94f53035e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994177627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2994177627
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.468423120
Short name T45
Test name
Test status
Simulation time 75228789 ps
CPU time 1.12 seconds
Started Jun 28 04:43:46 PM PDT 24
Finished Jun 28 04:43:49 PM PDT 24
Peak memory 198696 kb
Host smart-8fc4675a-b907-4cfc-9053-cc68e47656dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468423120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.468423120
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2156076524
Short name T756
Test name
Test status
Simulation time 17069974 ps
CPU time 1.01 seconds
Started Jun 28 04:43:44 PM PDT 24
Finished Jun 28 04:43:47 PM PDT 24
Peak memory 198408 kb
Host smart-163bc569-4fa1-4011-b465-743d26c8ffd5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156076524 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2156076524
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2284624809
Short name T87
Test name
Test status
Simulation time 16817357 ps
CPU time 0.64 seconds
Started Jun 28 04:43:49 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 195568 kb
Host smart-a764f3ef-4fd4-4536-b73b-c778fc688166
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284624809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2284624809
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1866925003
Short name T762
Test name
Test status
Simulation time 14394874 ps
CPU time 0.61 seconds
Started Jun 28 04:43:45 PM PDT 24
Finished Jun 28 04:43:47 PM PDT 24
Peak memory 194416 kb
Host smart-8b0c04ec-9700-4f62-87ef-b151d2095ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866925003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1866925003
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1808831916
Short name T79
Test name
Test status
Simulation time 14469673 ps
CPU time 0.63 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 195084 kb
Host smart-e8ba11f8-ca44-4b68-b8d4-44f96c4ea797
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808831916 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1808831916
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1263912319
Short name T746
Test name
Test status
Simulation time 126568829 ps
CPU time 1.9 seconds
Started Jun 28 04:43:48 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 198600 kb
Host smart-826901fd-84d4-4c38-acb1-1cdc5695afcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263912319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1263912319
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2379297102
Short name T728
Test name
Test status
Simulation time 21088312 ps
CPU time 0.72 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 192136 kb
Host smart-cc3a7e81-fa63-4925-95c4-bcbb673fb23d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379297102 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2379297102
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1877346626
Short name T810
Test name
Test status
Simulation time 32073664 ps
CPU time 0.57 seconds
Started Jun 28 04:43:47 PM PDT 24
Finished Jun 28 04:43:50 PM PDT 24
Peak memory 193840 kb
Host smart-8da06af4-5485-497d-8918-6274e736110b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877346626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1877346626
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1474501071
Short name T836
Test name
Test status
Simulation time 15168432 ps
CPU time 0.65 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 195112 kb
Host smart-11448581-a6f1-453d-a6c3-43f66efad1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474501071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1474501071
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1882554138
Short name T814
Test name
Test status
Simulation time 67373896 ps
CPU time 0.67 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 196192 kb
Host smart-34ce64e2-95ad-452e-a47b-a5e2ba7b45b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882554138 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1882554138
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3968450274
Short name T723
Test name
Test status
Simulation time 99902310 ps
CPU time 1.9 seconds
Started Jun 28 04:43:57 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 198696 kb
Host smart-aa6961ed-14b1-48a8-b996-97f20492b8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968450274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3968450274
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2733213237
Short name T808
Test name
Test status
Simulation time 164377842 ps
CPU time 0.83 seconds
Started Jun 28 04:43:56 PM PDT 24
Finished Jun 28 04:43:57 PM PDT 24
Peak memory 198396 kb
Host smart-c7100281-c74b-43e7-9105-234ac39ceb75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733213237 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2733213237
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3376357066
Short name T89
Test name
Test status
Simulation time 17178231 ps
CPU time 0.62 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 195352 kb
Host smart-59a1bf33-a89a-4b53-abb2-fdf2e6c4b232
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376357066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3376357066
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.934527079
Short name T721
Test name
Test status
Simulation time 22518533 ps
CPU time 0.63 seconds
Started Jun 28 04:43:57 PM PDT 24
Finished Jun 28 04:43:59 PM PDT 24
Peak memory 194968 kb
Host smart-a57e5e5e-f9bd-46d2-8267-39026185aedb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934527079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.934527079
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1468271008
Short name T94
Test name
Test status
Simulation time 34243821 ps
CPU time 0.83 seconds
Started Jun 28 04:44:02 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 197064 kb
Host smart-a5f5085d-a1b5-42b7-a32d-a586958a1641
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468271008 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1468271008
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.194497603
Short name T790
Test name
Test status
Simulation time 87659743 ps
CPU time 1.31 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:02 PM PDT 24
Peak memory 198684 kb
Host smart-e54d41fd-ecd1-48d2-9ebc-4d75ea367fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194497603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.194497603
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.176256613
Short name T36
Test name
Test status
Simulation time 86637783 ps
CPU time 1.25 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 198736 kb
Host smart-4414d429-faab-46dc-99a2-ea8ac0267ebb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176256613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.176256613
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.42459303
Short name T74
Test name
Test status
Simulation time 59535138 ps
CPU time 0.82 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 196800 kb
Host smart-bf9b45bb-b794-4731-abc3-dfec2e16f4c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42459303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
gpio_csr_aliasing.42459303
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.163671349
Short name T795
Test name
Test status
Simulation time 265050353 ps
CPU time 3.07 seconds
Started Jun 28 04:43:34 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 197628 kb
Host smart-6050f23a-2291-4740-ba26-59a07088f655
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163671349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.163671349
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1243661983
Short name T80
Test name
Test status
Simulation time 31428424 ps
CPU time 0.64 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 195268 kb
Host smart-79d7c519-1a2d-415c-afdc-687ac2725acb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243661983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1243661983
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.16953370
Short name T793
Test name
Test status
Simulation time 35815899 ps
CPU time 0.96 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 198600 kb
Host smart-46f993fc-d2a2-4b25-9eef-b5e3dc4aa7fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16953370 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.16953370
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1282678360
Short name T103
Test name
Test status
Simulation time 43440422 ps
CPU time 0.62 seconds
Started Jun 28 04:43:31 PM PDT 24
Finished Jun 28 04:43:33 PM PDT 24
Peak memory 195236 kb
Host smart-41051d6d-8816-4eb8-93ad-5334ad9e851c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282678360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1282678360
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.440768733
Short name T829
Test name
Test status
Simulation time 99879174 ps
CPU time 0.59 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 194880 kb
Host smart-ed3633d6-9e91-4f65-afdb-87ce5b03d9c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440768733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.440768733
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1470387680
Short name T797
Test name
Test status
Simulation time 76801319 ps
CPU time 0.62 seconds
Started Jun 28 04:43:25 PM PDT 24
Finished Jun 28 04:43:27 PM PDT 24
Peak memory 195300 kb
Host smart-13960cb8-ddcd-4db9-a459-e56e44e949ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470387680 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1470387680
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3915863942
Short name T837
Test name
Test status
Simulation time 54953918 ps
CPU time 2.89 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:34 PM PDT 24
Peak memory 198692 kb
Host smart-98987fb0-48fb-4972-a681-cb78d035bf37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915863942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3915863942
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3135631064
Short name T43
Test name
Test status
Simulation time 112372606 ps
CPU time 1.47 seconds
Started Jun 28 04:43:34 PM PDT 24
Finished Jun 28 04:43:36 PM PDT 24
Peak memory 198632 kb
Host smart-47fe1c96-f47a-4f30-909d-4e579e362390
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135631064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3135631064
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3257584063
Short name T805
Test name
Test status
Simulation time 10972055 ps
CPU time 0.59 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:44:00 PM PDT 24
Peak memory 194388 kb
Host smart-9415e51b-016e-42ff-a66e-b4a3976d0dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257584063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3257584063
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2275458646
Short name T753
Test name
Test status
Simulation time 12554180 ps
CPU time 0.61 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:02 PM PDT 24
Peak memory 194352 kb
Host smart-d45c99f3-50a7-4ad3-ab88-468c54363230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275458646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2275458646
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1853209272
Short name T727
Test name
Test status
Simulation time 34575965 ps
CPU time 0.6 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:43:59 PM PDT 24
Peak memory 194956 kb
Host smart-894277cf-807b-4a4b-a1a1-40b461032e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853209272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1853209272
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3006885535
Short name T807
Test name
Test status
Simulation time 11968285 ps
CPU time 0.59 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 195208 kb
Host smart-03591f22-4492-40b9-91a4-f6631a92b835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006885535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3006885535
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1599521335
Short name T767
Test name
Test status
Simulation time 36668501 ps
CPU time 0.59 seconds
Started Jun 28 04:44:02 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 194376 kb
Host smart-376da880-dc2a-4727-ae2f-be783c3ec57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599521335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1599521335
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3994414974
Short name T791
Test name
Test status
Simulation time 16950687 ps
CPU time 0.65 seconds
Started Jun 28 04:43:56 PM PDT 24
Finished Jun 28 04:43:57 PM PDT 24
Peak memory 195016 kb
Host smart-171f374b-9aa1-4fe5-99af-e2513a26d882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994414974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3994414974
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1992158637
Short name T739
Test name
Test status
Simulation time 20981450 ps
CPU time 0.59 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 194912 kb
Host smart-d2f5cdae-7834-494d-89a8-e47998cc37f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992158637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1992158637
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2351514840
Short name T742
Test name
Test status
Simulation time 12675665 ps
CPU time 0.59 seconds
Started Jun 28 04:43:57 PM PDT 24
Finished Jun 28 04:43:59 PM PDT 24
Peak memory 194352 kb
Host smart-58281d4c-5ecf-45f9-9fd3-f7cd0a0145b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351514840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2351514840
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3758131898
Short name T745
Test name
Test status
Simulation time 25254277 ps
CPU time 0.6 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 194424 kb
Host smart-6df021f1-c024-4e92-867d-4c63806cb50a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758131898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3758131898
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2065667445
Short name T758
Test name
Test status
Simulation time 32181890 ps
CPU time 0.6 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:44:00 PM PDT 24
Peak memory 194980 kb
Host smart-4b0f51cf-4f82-4eca-a2a5-c451f55f4394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065667445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2065667445
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.566133109
Short name T820
Test name
Test status
Simulation time 224732205 ps
CPU time 2.45 seconds
Started Jun 28 04:43:33 PM PDT 24
Finished Jun 28 04:43:37 PM PDT 24
Peak memory 198532 kb
Host smart-c19add8e-4572-41a4-888f-2b8d00f20a59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566133109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.566133109
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.762415871
Short name T88
Test name
Test status
Simulation time 50027689 ps
CPU time 0.66 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 195248 kb
Host smart-305afee6-13b0-436a-b16d-d458126cb0c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762415871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.762415871
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2988631793
Short name T744
Test name
Test status
Simulation time 68292898 ps
CPU time 1.01 seconds
Started Jun 28 04:43:30 PM PDT 24
Finished Jun 28 04:43:33 PM PDT 24
Peak memory 198488 kb
Host smart-86ee9749-a06d-463a-bd2c-dec837d32be1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988631793 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2988631793
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3270223296
Short name T77
Test name
Test status
Simulation time 19076374 ps
CPU time 0.64 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 195496 kb
Host smart-d8dc18a8-8e36-4a81-9493-7617c053a5fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270223296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3270223296
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3033940369
Short name T743
Test name
Test status
Simulation time 59826713 ps
CPU time 0.58 seconds
Started Jun 28 04:43:28 PM PDT 24
Finished Jun 28 04:43:31 PM PDT 24
Peak memory 194900 kb
Host smart-3c4cd65b-bb54-487f-9a2f-a2b8068bb7fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033940369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3033940369
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.89905832
Short name T794
Test name
Test status
Simulation time 13682183 ps
CPU time 0.66 seconds
Started Jun 28 04:43:31 PM PDT 24
Finished Jun 28 04:43:33 PM PDT 24
Peak memory 195560 kb
Host smart-5ac911d6-accf-4458-b39d-ec9d7ecbeec6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89905832 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.gpio_same_csr_outstanding.89905832
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2391472768
Short name T720
Test name
Test status
Simulation time 55896722 ps
CPU time 2.97 seconds
Started Jun 28 04:43:34 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 198624 kb
Host smart-bb76656c-77a6-4b10-9446-ef4abf5c19cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391472768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2391472768
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2839739236
Short name T34
Test name
Test status
Simulation time 82726977 ps
CPU time 1.17 seconds
Started Jun 28 04:43:28 PM PDT 24
Finished Jun 28 04:43:31 PM PDT 24
Peak memory 198644 kb
Host smart-1e1e5ef0-0f3d-46ff-be2c-87866d94c09e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839739236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2839739236
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1280593815
Short name T735
Test name
Test status
Simulation time 39779726 ps
CPU time 0.6 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:44:00 PM PDT 24
Peak memory 194364 kb
Host smart-27bfd79f-b8c0-48bc-9fa3-e335eb1e023e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280593815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1280593815
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.485827593
Short name T781
Test name
Test status
Simulation time 32973692 ps
CPU time 0.6 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:44:00 PM PDT 24
Peak memory 194448 kb
Host smart-e348dcc2-b9b0-40c0-be3b-ab00fe311a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485827593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.485827593
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.31924763
Short name T725
Test name
Test status
Simulation time 71032127 ps
CPU time 0.59 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 194388 kb
Host smart-ebb97a49-5552-4fd9-9004-ff989d696263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31924763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.31924763
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.822252414
Short name T722
Test name
Test status
Simulation time 58812799 ps
CPU time 0.64 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 195128 kb
Host smart-f747e11f-6b57-458e-ad1f-f59fb18c727b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822252414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.822252414
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3585907567
Short name T764
Test name
Test status
Simulation time 22695945 ps
CPU time 0.58 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 194828 kb
Host smart-30e8c97e-feab-4cf2-9bd9-06efa8157b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585907567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3585907567
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1911500281
Short name T815
Test name
Test status
Simulation time 49118896 ps
CPU time 0.64 seconds
Started Jun 28 04:44:02 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 195024 kb
Host smart-2e18115f-69b5-4f0c-af24-a0d16ed77918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911500281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1911500281
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.406208041
Short name T719
Test name
Test status
Simulation time 42542860 ps
CPU time 0.66 seconds
Started Jun 28 04:44:02 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 194436 kb
Host smart-544c09ad-873b-4940-926a-7640b033b445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406208041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.406208041
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1302026119
Short name T787
Test name
Test status
Simulation time 19749864 ps
CPU time 0.6 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 194452 kb
Host smart-50f91217-a53c-4b27-ae6c-af5b09b036c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302026119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1302026119
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3683018114
Short name T741
Test name
Test status
Simulation time 19369277 ps
CPU time 0.59 seconds
Started Jun 28 04:43:57 PM PDT 24
Finished Jun 28 04:43:59 PM PDT 24
Peak memory 194372 kb
Host smart-61ccaa9f-9267-415e-bb0f-2e04a76e29b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683018114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3683018114
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1061168822
Short name T747
Test name
Test status
Simulation time 17903519 ps
CPU time 0.62 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 194320 kb
Host smart-55bb4745-62bc-4796-9452-6cdd907e644a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061168822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1061168822
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3506613735
Short name T76
Test name
Test status
Simulation time 31512984 ps
CPU time 0.9 seconds
Started Jun 28 04:43:31 PM PDT 24
Finished Jun 28 04:43:33 PM PDT 24
Peak memory 196656 kb
Host smart-b6aff817-64fe-40cd-9f97-eba3daf98bda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506613735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3506613735
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2238583801
Short name T90
Test name
Test status
Simulation time 58701833 ps
CPU time 2.29 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:39 PM PDT 24
Peak memory 198664 kb
Host smart-9a526438-0986-48db-98e6-ebfeb17944bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238583801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2238583801
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2835978884
Short name T733
Test name
Test status
Simulation time 34340290 ps
CPU time 0.61 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:37 PM PDT 24
Peak memory 195336 kb
Host smart-132a8de3-a77e-45c5-9c8f-d14c6a5e60ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835978884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2835978884
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2612685194
Short name T778
Test name
Test status
Simulation time 20745819 ps
CPU time 0.92 seconds
Started Jun 28 04:43:27 PM PDT 24
Finished Jun 28 04:43:30 PM PDT 24
Peak memory 198600 kb
Host smart-afae458c-2d10-422a-8f6f-a3bba4a99e23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612685194 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2612685194
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4249893532
Short name T772
Test name
Test status
Simulation time 49758750 ps
CPU time 0.68 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 196240 kb
Host smart-d331c24c-1832-4eed-af79-785e4f5c86d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249893532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.4249893532
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2838284422
Short name T822
Test name
Test status
Simulation time 14011560 ps
CPU time 0.57 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:37 PM PDT 24
Peak memory 194376 kb
Host smart-acd741f1-43c4-4e81-95e5-9e736ea34aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838284422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2838284422
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3865206841
Short name T782
Test name
Test status
Simulation time 173613190 ps
CPU time 0.65 seconds
Started Jun 28 04:43:30 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 195572 kb
Host smart-4d82bbdb-d962-43e2-ac8c-176fb0edb6de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865206841 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3865206841
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3462999909
Short name T761
Test name
Test status
Simulation time 174982362 ps
CPU time 3.19 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:34 PM PDT 24
Peak memory 198736 kb
Host smart-71576f2c-c5f1-492f-9694-5ddac7089d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462999909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3462999909
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3336964293
Short name T105
Test name
Test status
Simulation time 502595034 ps
CPU time 1.07 seconds
Started Jun 28 04:43:28 PM PDT 24
Finished Jun 28 04:43:31 PM PDT 24
Peak memory 198632 kb
Host smart-82941dd9-9819-4eff-819e-82d4de205969
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336964293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3336964293
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.206120417
Short name T738
Test name
Test status
Simulation time 11320844 ps
CPU time 0.59 seconds
Started Jun 28 04:44:05 PM PDT 24
Finished Jun 28 04:44:06 PM PDT 24
Peak memory 194260 kb
Host smart-525acc54-bbb9-4f43-b2b5-59e67f4b8333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206120417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.206120417
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.326754090
Short name T726
Test name
Test status
Simulation time 36916526 ps
CPU time 0.62 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:02 PM PDT 24
Peak memory 194688 kb
Host smart-6c63564a-ebc8-43c2-b3e3-f94fdcbfb457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326754090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.326754090
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1560197035
Short name T833
Test name
Test status
Simulation time 40705189 ps
CPU time 0.58 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:02 PM PDT 24
Peak memory 194352 kb
Host smart-10fa88b2-344e-48f6-8afd-190481108566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560197035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1560197035
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3058744386
Short name T816
Test name
Test status
Simulation time 44362954 ps
CPU time 0.59 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 194288 kb
Host smart-77db6948-fde0-4e09-8568-ac137780db29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058744386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3058744386
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3391659951
Short name T825
Test name
Test status
Simulation time 32447827 ps
CPU time 0.6 seconds
Started Jun 28 04:43:57 PM PDT 24
Finished Jun 28 04:43:59 PM PDT 24
Peak memory 194484 kb
Host smart-b0ef6c61-fdb3-4c8a-b678-3eab97b664c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391659951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3391659951
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.4113775006
Short name T748
Test name
Test status
Simulation time 60380017 ps
CPU time 0.64 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 195172 kb
Host smart-0bed60ab-a970-4511-b7c7-be0ab050ab26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113775006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.4113775006
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.481486294
Short name T817
Test name
Test status
Simulation time 26394679 ps
CPU time 0.58 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 194244 kb
Host smart-02e8b735-8d18-4ba6-8133-8774002166a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481486294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.481486294
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2962142769
Short name T773
Test name
Test status
Simulation time 32441627 ps
CPU time 0.58 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:02 PM PDT 24
Peak memory 194372 kb
Host smart-09172e2c-7188-4131-a54d-a3259f7212bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962142769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2962142769
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4076431690
Short name T765
Test name
Test status
Simulation time 24684050 ps
CPU time 0.62 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 194916 kb
Host smart-1725ec79-89eb-4f50-a57a-bc93a18c0fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076431690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4076431690
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2271828896
Short name T812
Test name
Test status
Simulation time 24314624 ps
CPU time 0.6 seconds
Started Jun 28 04:44:05 PM PDT 24
Finished Jun 28 04:44:06 PM PDT 24
Peak memory 194916 kb
Host smart-3555d3a2-82fa-4d33-8c28-5166d47b838a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271828896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2271828896
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1590549674
Short name T740
Test name
Test status
Simulation time 30544453 ps
CPU time 0.82 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:37 PM PDT 24
Peak memory 198728 kb
Host smart-d2c9a1bb-057e-434d-8f76-95467a2f0d13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590549674 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1590549674
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1428793182
Short name T83
Test name
Test status
Simulation time 19438387 ps
CPU time 0.64 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:39 PM PDT 24
Peak memory 195780 kb
Host smart-97ef953d-4a54-4908-99a1-15ea436a169f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428793182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1428793182
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.69033972
Short name T789
Test name
Test status
Simulation time 11354697 ps
CPU time 0.59 seconds
Started Jun 28 04:43:40 PM PDT 24
Finished Jun 28 04:43:41 PM PDT 24
Peak memory 194284 kb
Host smart-bad0fc28-c53b-4933-8350-4cbc93106845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69033972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.69033972
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2489390844
Short name T78
Test name
Test status
Simulation time 28922936 ps
CPU time 0.79 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 196852 kb
Host smart-48c68270-c178-400b-853c-aa9deba49d05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489390844 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2489390844
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2971405997
Short name T759
Test name
Test status
Simulation time 43274885 ps
CPU time 2.02 seconds
Started Jun 28 04:43:37 PM PDT 24
Finished Jun 28 04:43:40 PM PDT 24
Peak memory 198708 kb
Host smart-23ba1211-18c1-4d71-bb4f-6a583d4ff9d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971405997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2971405997
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2552175340
Short name T775
Test name
Test status
Simulation time 300753662 ps
CPU time 0.88 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 197900 kb
Host smart-8944d852-1c5a-448e-a2b2-9c637b44a6c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552175340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2552175340
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1426697780
Short name T779
Test name
Test status
Simulation time 24687039 ps
CPU time 0.77 seconds
Started Jun 28 04:43:39 PM PDT 24
Finished Jun 28 04:43:40 PM PDT 24
Peak memory 198500 kb
Host smart-9071c7fd-b912-4bb7-8576-a177751079dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426697780 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1426697780
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.537643976
Short name T84
Test name
Test status
Simulation time 35123194 ps
CPU time 0.59 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 194100 kb
Host smart-99c00975-6476-442b-9e34-39794fcb650e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537643976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.537643976
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1943699006
Short name T818
Test name
Test status
Simulation time 16933439 ps
CPU time 0.6 seconds
Started Jun 28 04:43:34 PM PDT 24
Finished Jun 28 04:43:35 PM PDT 24
Peak memory 194464 kb
Host smart-e0aacff3-dc7a-455f-bdb4-250bbb8cbc92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943699006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1943699006
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.572876028
Short name T95
Test name
Test status
Simulation time 61908194 ps
CPU time 0.77 seconds
Started Jun 28 04:43:38 PM PDT 24
Finished Jun 28 04:43:40 PM PDT 24
Peak memory 196816 kb
Host smart-f3470dc6-2bc4-46ba-b198-da12b06798ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572876028 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.572876028
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4255299311
Short name T769
Test name
Test status
Simulation time 946408352 ps
CPU time 3.17 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:41 PM PDT 24
Peak memory 198692 kb
Host smart-25e055b7-5bfc-4496-a666-843e7dabe110
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255299311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4255299311
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2599662831
Short name T42
Test name
Test status
Simulation time 550511640 ps
CPU time 1.36 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 198712 kb
Host smart-6413be5f-5fc1-4812-8c77-30b62a5f153f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599662831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2599662831
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1844793936
Short name T736
Test name
Test status
Simulation time 35848544 ps
CPU time 1.52 seconds
Started Jun 28 04:43:34 PM PDT 24
Finished Jun 28 04:43:36 PM PDT 24
Peak memory 198764 kb
Host smart-f6df4894-114d-49f7-9a52-6df9d28c9bf3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844793936 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1844793936
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2041075355
Short name T750
Test name
Test status
Simulation time 23060706 ps
CPU time 0.57 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 195276 kb
Host smart-0137a506-2ef2-45d3-a305-5eac7216bdb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041075355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2041075355
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2255991330
Short name T768
Test name
Test status
Simulation time 36227619 ps
CPU time 0.57 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 194388 kb
Host smart-dc2e648b-2dcd-494e-b73f-97a42a8dd5cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255991330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2255991330
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3195158660
Short name T800
Test name
Test status
Simulation time 37480012 ps
CPU time 0.82 seconds
Started Jun 28 04:43:38 PM PDT 24
Finished Jun 28 04:43:40 PM PDT 24
Peak memory 197592 kb
Host smart-a38b8f02-0bce-4657-bffa-e6a2bf9fad52
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195158660 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3195158660
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2033282892
Short name T724
Test name
Test status
Simulation time 192047736 ps
CPU time 2.66 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:39 PM PDT 24
Peak memory 198676 kb
Host smart-39c96030-5304-49d1-897b-fb576d78a5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033282892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2033282892
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.535018565
Short name T46
Test name
Test status
Simulation time 160406889 ps
CPU time 1.2 seconds
Started Jun 28 04:43:38 PM PDT 24
Finished Jun 28 04:43:41 PM PDT 24
Peak memory 198556 kb
Host smart-098b8bf3-d045-4230-880d-6043d69c2e97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535018565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.535018565
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3136574000
Short name T796
Test name
Test status
Simulation time 62294981 ps
CPU time 1.46 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 198704 kb
Host smart-e8282488-b0a1-4a5d-a3c7-eea96a7a3ea7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136574000 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3136574000
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2684375354
Short name T830
Test name
Test status
Simulation time 14501784 ps
CPU time 0.62 seconds
Started Jun 28 04:43:41 PM PDT 24
Finished Jun 28 04:43:42 PM PDT 24
Peak memory 195452 kb
Host smart-66f1dc79-0bf8-412c-8cde-e30d144fe83a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684375354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2684375354
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.263232654
Short name T752
Test name
Test status
Simulation time 13840147 ps
CPU time 0.55 seconds
Started Jun 28 04:43:37 PM PDT 24
Finished Jun 28 04:43:39 PM PDT 24
Peak memory 194356 kb
Host smart-441b1044-bc28-423c-99a0-b6353b19b774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263232654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.263232654
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2926966671
Short name T101
Test name
Test status
Simulation time 18180110 ps
CPU time 0.75 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 197480 kb
Host smart-5cea73f6-8a80-4483-be04-6751e29b6896
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926966671 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2926966671
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2680057141
Short name T835
Test name
Test status
Simulation time 247756362 ps
CPU time 1.52 seconds
Started Jun 28 04:43:38 PM PDT 24
Finished Jun 28 04:43:41 PM PDT 24
Peak memory 198732 kb
Host smart-52846a7a-9244-49de-bd4c-f416dcaf34f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680057141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2680057141
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.546938944
Short name T823
Test name
Test status
Simulation time 77837433 ps
CPU time 0.89 seconds
Started Jun 28 04:43:37 PM PDT 24
Finished Jun 28 04:43:40 PM PDT 24
Peak memory 197712 kb
Host smart-226b2fea-c80f-48d0-922a-608fc7cbce34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546938944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.546938944
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3890635511
Short name T780
Test name
Test status
Simulation time 128823247 ps
CPU time 0.72 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:37 PM PDT 24
Peak memory 198596 kb
Host smart-6ee5f73a-b577-48a0-bba7-eaaac57f988c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890635511 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3890635511
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4253991341
Short name T813
Test name
Test status
Simulation time 34228734 ps
CPU time 0.63 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:39 PM PDT 24
Peak memory 195188 kb
Host smart-a04a0c4f-3b9a-4183-8949-42774712b936
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253991341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.4253991341
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2301558298
Short name T749
Test name
Test status
Simulation time 69263349 ps
CPU time 0.6 seconds
Started Jun 28 04:43:35 PM PDT 24
Finished Jun 28 04:43:37 PM PDT 24
Peak memory 194284 kb
Host smart-76ee3d50-63a7-42c8-9b87-ea0c3a4b49af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301558298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2301558298
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2635615745
Short name T96
Test name
Test status
Simulation time 49254769 ps
CPU time 0.71 seconds
Started Jun 28 04:43:34 PM PDT 24
Finished Jun 28 04:43:36 PM PDT 24
Peak memory 197416 kb
Host smart-cac38dc8-6d24-4691-ab7f-0c67c28399ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635615745 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2635615745
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3566347099
Short name T804
Test name
Test status
Simulation time 247231903 ps
CPU time 2.6 seconds
Started Jun 28 04:43:36 PM PDT 24
Finished Jun 28 04:43:40 PM PDT 24
Peak memory 198576 kb
Host smart-796b4711-9d03-4c86-85ee-3e3d58905e72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566347099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3566347099
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3936236718
Short name T827
Test name
Test status
Simulation time 76434043 ps
CPU time 1.15 seconds
Started Jun 28 04:43:39 PM PDT 24
Finished Jun 28 04:43:41 PM PDT 24
Peak memory 198184 kb
Host smart-5127ed07-e5d9-4b0b-a03e-2a93c563f621
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936236718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3936236718
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4280216999
Short name T448
Test name
Test status
Simulation time 19257718 ps
CPU time 0.61 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:46:59 PM PDT 24
Peak memory 194944 kb
Host smart-89c80ac5-1e87-4e7e-818f-d6510a8c0d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280216999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4280216999
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.876605621
Short name T640
Test name
Test status
Simulation time 76613120 ps
CPU time 0.86 seconds
Started Jun 28 04:46:40 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 197928 kb
Host smart-f1ffd656-09fc-4316-aa32-749964e8cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876605621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.876605621
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.173491598
Short name T360
Test name
Test status
Simulation time 767094860 ps
CPU time 19.56 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:47:15 PM PDT 24
Peak memory 196232 kb
Host smart-e4b5f60e-373d-41e3-b1b8-720b931f7fad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173491598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.173491598
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2973989288
Short name T717
Test name
Test status
Simulation time 120176760 ps
CPU time 0.73 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 196064 kb
Host smart-b9c7adb8-e105-4ae8-9ada-5a88822c1618
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973989288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2973989288
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1126237893
Short name T480
Test name
Test status
Simulation time 312231996 ps
CPU time 0.75 seconds
Started Jun 28 04:46:48 PM PDT 24
Finished Jun 28 04:46:49 PM PDT 24
Peak memory 196152 kb
Host smart-8be755a2-c90c-4af6-b893-0f8768b0b37c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126237893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1126237893
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2712995672
Short name T685
Test name
Test status
Simulation time 82880390 ps
CPU time 1.81 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 198676 kb
Host smart-39a6e7d0-5186-4b4d-98e3-8468bc604553
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712995672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2712995672
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2896106474
Short name T464
Test name
Test status
Simulation time 98664943 ps
CPU time 2.72 seconds
Started Jun 28 04:46:50 PM PDT 24
Finished Jun 28 04:46:54 PM PDT 24
Peak memory 196532 kb
Host smart-9f5ca9a9-0ccf-461a-a3b0-6ff352c41fb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896106474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2896106474
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2092605165
Short name T266
Test name
Test status
Simulation time 16955570 ps
CPU time 0.77 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:00 PM PDT 24
Peak memory 196016 kb
Host smart-8a4f7a3d-6131-45b4-88f6-3c1de8ac974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092605165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2092605165
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.48086078
Short name T59
Test name
Test status
Simulation time 197159052 ps
CPU time 1.14 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:46:59 PM PDT 24
Peak memory 196652 kb
Host smart-99d598e6-9f00-4591-85c4-6a2301142bd2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48086078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_p
ulldown.48086078
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.4244196418
Short name T264
Test name
Test status
Simulation time 94751807 ps
CPU time 4.27 seconds
Started Jun 28 04:46:52 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 198576 kb
Host smart-85b68973-d949-47d0-b0dd-39c7a7e3bd11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244196418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.4244196418
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3991003532
Short name T52
Test name
Test status
Simulation time 62261822 ps
CPU time 0.88 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 215108 kb
Host smart-14e38ee9-85b9-4ef8-b4e7-6aaa24e7da21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991003532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3991003532
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2842167752
Short name T248
Test name
Test status
Simulation time 32801759 ps
CPU time 0.94 seconds
Started Jun 28 04:46:37 PM PDT 24
Finished Jun 28 04:46:40 PM PDT 24
Peak memory 196272 kb
Host smart-d3aa4e62-dd60-48e6-bee5-4581a7fe8f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842167752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2842167752
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2556550454
Short name T359
Test name
Test status
Simulation time 48667371 ps
CPU time 1.13 seconds
Started Jun 28 04:46:56 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 196388 kb
Host smart-effdd06d-fdd2-48b5-91ab-48639b96c892
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556550454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2556550454
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1763573275
Short name T558
Test name
Test status
Simulation time 16375402399 ps
CPU time 139.96 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:49:17 PM PDT 24
Peak memory 198808 kb
Host smart-5e3eeef4-b95a-49de-84d6-0e634b72f417
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763573275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1763573275
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.114363785
Short name T357
Test name
Test status
Simulation time 18103922 ps
CPU time 0.66 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 195324 kb
Host smart-bd60a38a-70f4-4699-8799-a307fc583786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114363785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.114363785
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.823278807
Short name T146
Test name
Test status
Simulation time 955433670 ps
CPU time 12.26 seconds
Started Jun 28 04:46:51 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 196140 kb
Host smart-3d77d1ff-5e8d-4334-8789-f80d34b74a45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823278807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.823278807
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1577555463
Short name T149
Test name
Test status
Simulation time 76475175 ps
CPU time 0.67 seconds
Started Jun 28 04:47:01 PM PDT 24
Finished Jun 28 04:47:04 PM PDT 24
Peak memory 195168 kb
Host smart-87abc850-3bb1-41ac-b3a8-26942a97320a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577555463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1577555463
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3958995200
Short name T225
Test name
Test status
Simulation time 34626385 ps
CPU time 1.01 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 196720 kb
Host smart-c0d219e3-af26-4992-ac40-74014dfd3498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958995200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3958995200
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3119244468
Short name T141
Test name
Test status
Simulation time 170350426 ps
CPU time 3.46 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:46:54 PM PDT 24
Peak memory 198676 kb
Host smart-8b737c95-7ef8-4c5c-bbe8-d39cacd92416
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119244468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3119244468
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2714269623
Short name T199
Test name
Test status
Simulation time 248564089 ps
CPU time 1.35 seconds
Started Jun 28 04:46:56 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 196388 kb
Host smart-a5caebd3-f324-4596-a194-1c848dda12f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714269623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2714269623
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1623569877
Short name T236
Test name
Test status
Simulation time 27646052 ps
CPU time 0.84 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:56 PM PDT 24
Peak memory 195944 kb
Host smart-bd76b6e3-6975-4814-8a42-f98740506271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623569877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1623569877
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3666553428
Short name T71
Test name
Test status
Simulation time 208586797 ps
CPU time 1.21 seconds
Started Jun 28 04:47:02 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 197744 kb
Host smart-3cdee91d-eef8-467f-80ef-86846002fe70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666553428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3666553428
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3255514615
Short name T683
Test name
Test status
Simulation time 2268196659 ps
CPU time 5.34 seconds
Started Jun 28 04:46:52 PM PDT 24
Finished Jun 28 04:47:00 PM PDT 24
Peak memory 198712 kb
Host smart-b22ec470-276d-4fe0-9b36-0891d5c27cd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255514615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3255514615
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.112380250
Short name T263
Test name
Test status
Simulation time 168136217 ps
CPU time 1.26 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 196224 kb
Host smart-9c9448f5-bd57-4d14-bb1d-c4b9ac07deff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112380250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.112380250
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3610695918
Short name T555
Test name
Test status
Simulation time 54885817 ps
CPU time 1.1 seconds
Started Jun 28 04:46:52 PM PDT 24
Finished Jun 28 04:46:56 PM PDT 24
Peak memory 196792 kb
Host smart-cb111e7b-8c78-45d8-97e2-365a4aa41d9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610695918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3610695918
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.776954170
Short name T524
Test name
Test status
Simulation time 15186413763 ps
CPU time 45.98 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:47:42 PM PDT 24
Peak memory 198700 kb
Host smart-2d2f1d89-c208-43ae-865e-ee33549d248e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776954170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.776954170
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3349474206
Short name T33
Test name
Test status
Simulation time 381661407174 ps
CPU time 2015.7 seconds
Started Jun 28 04:46:47 PM PDT 24
Finished Jun 28 05:20:24 PM PDT 24
Peak memory 198916 kb
Host smart-ec418a70-2a22-4a70-b5f2-84f26f6a3aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3349474206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3349474206
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2334536704
Short name T399
Test name
Test status
Simulation time 15371375 ps
CPU time 0.62 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 194588 kb
Host smart-591c0888-f7b2-48f1-aafa-3ebc60eee2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334536704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2334536704
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1922751527
Short name T376
Test name
Test status
Simulation time 67179626 ps
CPU time 0.62 seconds
Started Jun 28 04:47:10 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 195260 kb
Host smart-4f42bee8-75c8-4cbd-9cd1-8b82c0ceed79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922751527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1922751527
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1232983929
Short name T384
Test name
Test status
Simulation time 607545123 ps
CPU time 3.45 seconds
Started Jun 28 04:47:15 PM PDT 24
Finished Jun 28 04:47:19 PM PDT 24
Peak memory 196692 kb
Host smart-3abd1f43-1028-4351-b937-d16147620aba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232983929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1232983929
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2926460539
Short name T9
Test name
Test status
Simulation time 36529427 ps
CPU time 0.68 seconds
Started Jun 28 04:47:06 PM PDT 24
Finished Jun 28 04:47:07 PM PDT 24
Peak memory 195392 kb
Host smart-ab33dac8-d0c2-4d08-9610-1b58525e22b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926460539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2926460539
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3031377694
Short name T553
Test name
Test status
Simulation time 54557476 ps
CPU time 1.01 seconds
Started Jun 28 04:47:08 PM PDT 24
Finished Jun 28 04:47:10 PM PDT 24
Peak memory 196720 kb
Host smart-26fdab31-3811-4697-ab88-cc17920742b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031377694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3031377694
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.817004959
Short name T187
Test name
Test status
Simulation time 195412344 ps
CPU time 1.79 seconds
Started Jun 28 04:47:01 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 198696 kb
Host smart-8762d254-ae38-4545-9343-d5e8b686bf9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817004959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.817004959
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.622307050
Short name T621
Test name
Test status
Simulation time 138018531 ps
CPU time 2.86 seconds
Started Jun 28 04:47:18 PM PDT 24
Finished Jun 28 04:47:22 PM PDT 24
Peak memory 197912 kb
Host smart-f6d801ca-1954-4127-87b9-cba0d7d949d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622307050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
622307050
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2085356957
Short name T320
Test name
Test status
Simulation time 99816003 ps
CPU time 0.82 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 196072 kb
Host smart-207f3d3a-9be1-49e5-ba1e-1d466fb1509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085356957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2085356957
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.283582633
Short name T254
Test name
Test status
Simulation time 27079595 ps
CPU time 1.06 seconds
Started Jun 28 04:47:10 PM PDT 24
Finished Jun 28 04:47:12 PM PDT 24
Peak memory 196752 kb
Host smart-7d7b7b22-2b50-458b-aebd-3876ed369f15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283582633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.283582633
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.415389046
Short name T3
Test name
Test status
Simulation time 2187286065 ps
CPU time 3.34 seconds
Started Jun 28 04:47:10 PM PDT 24
Finished Jun 28 04:47:15 PM PDT 24
Peak memory 198896 kb
Host smart-9e280a19-b34c-4eeb-86af-743904a628e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415389046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.415389046
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3403197838
Short name T209
Test name
Test status
Simulation time 133842450 ps
CPU time 1.08 seconds
Started Jun 28 04:47:00 PM PDT 24
Finished Jun 28 04:47:04 PM PDT 24
Peak memory 196636 kb
Host smart-1dcd32e5-a317-44d2-9699-6efbe869960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403197838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3403197838
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2247119175
Short name T389
Test name
Test status
Simulation time 92282133 ps
CPU time 1.34 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 198740 kb
Host smart-973f4fdc-eb6a-45ac-91b3-6e7da653e657
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247119175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2247119175
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.922804336
Short name T473
Test name
Test status
Simulation time 14722811610 ps
CPU time 162.11 seconds
Started Jun 28 04:47:03 PM PDT 24
Finished Jun 28 04:49:46 PM PDT 24
Peak memory 198816 kb
Host smart-64fcb021-f19d-47b1-875c-ed221d23cf3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922804336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.922804336
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.24196263
Short name T32
Test name
Test status
Simulation time 67669472967 ps
CPU time 1035.31 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 05:04:23 PM PDT 24
Peak memory 198768 kb
Host smart-05e7a50f-0ec3-4add-bb44-f4b860d21801
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=24196263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.24196263
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3454735622
Short name T210
Test name
Test status
Simulation time 34457239 ps
CPU time 0.6 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 194560 kb
Host smart-78721b1d-6590-4983-a6e3-8d9dad033bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454735622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3454735622
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1389385780
Short name T601
Test name
Test status
Simulation time 97262038 ps
CPU time 0.91 seconds
Started Jun 28 04:47:05 PM PDT 24
Finished Jun 28 04:47:07 PM PDT 24
Peak memory 196512 kb
Host smart-cb57c6a2-a305-4021-a2ce-47632ee907b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389385780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1389385780
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1537862195
Short name T697
Test name
Test status
Simulation time 2415311300 ps
CPU time 25.59 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 197200 kb
Host smart-1d1cd8ee-6401-46b7-901a-2ac69973bd03
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537862195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1537862195
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1108660597
Short name T20
Test name
Test status
Simulation time 65333625 ps
CPU time 0.71 seconds
Started Jun 28 04:47:20 PM PDT 24
Finished Jun 28 04:47:22 PM PDT 24
Peak memory 195228 kb
Host smart-037c5d0b-da7b-486f-abb3-c034c668460e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108660597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1108660597
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.357901077
Short name T213
Test name
Test status
Simulation time 104407462 ps
CPU time 0.84 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 197152 kb
Host smart-0e33e2cb-4962-4bcb-b57e-9956c02005eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357901077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.357901077
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1947762034
Short name T481
Test name
Test status
Simulation time 288958091 ps
CPU time 2.92 seconds
Started Jun 28 04:47:00 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 198636 kb
Host smart-30c94d24-d144-49de-96b0-3ead2f652024
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947762034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1947762034
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2547003355
Short name T592
Test name
Test status
Simulation time 82181452 ps
CPU time 1.78 seconds
Started Jun 28 04:47:16 PM PDT 24
Finished Jun 28 04:47:18 PM PDT 24
Peak memory 197432 kb
Host smart-77e96350-51c1-45fc-b24e-e69e2b4fdf3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547003355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2547003355
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.174735321
Short name T158
Test name
Test status
Simulation time 18721225 ps
CPU time 0.66 seconds
Started Jun 28 04:47:00 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 195620 kb
Host smart-f77ca2e1-7eae-4ea8-9936-a8773e06983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174735321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.174735321
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2035284337
Short name T186
Test name
Test status
Simulation time 43944826 ps
CPU time 0.71 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:14 PM PDT 24
Peak memory 195888 kb
Host smart-125129a8-f992-43c7-af95-cbf928a86957
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035284337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2035284337
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.134074402
Short name T427
Test name
Test status
Simulation time 675195644 ps
CPU time 4.65 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:15 PM PDT 24
Peak memory 198860 kb
Host smart-e85db808-550e-4161-b032-3819415efd78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134074402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.134074402
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3301928239
Short name T136
Test name
Test status
Simulation time 39283740 ps
CPU time 1.12 seconds
Started Jun 28 04:46:56 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 196472 kb
Host smart-4de36f0d-b2a8-43cf-9de7-3336c9359694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301928239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3301928239
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3884347938
Short name T445
Test name
Test status
Simulation time 137564713 ps
CPU time 1.33 seconds
Started Jun 28 04:47:03 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 198688 kb
Host smart-3e9faa83-c1f3-4cd1-8598-eb6363be62f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884347938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3884347938
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2753795448
Short name T542
Test name
Test status
Simulation time 8500561584 ps
CPU time 49.95 seconds
Started Jun 28 04:47:23 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 198700 kb
Host smart-36d5bdd1-818f-4e7d-9d1a-76fcd47c26bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753795448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2753795448
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.3812162442
Short name T62
Test name
Test status
Simulation time 354911676484 ps
CPU time 1712.73 seconds
Started Jun 28 04:47:20 PM PDT 24
Finished Jun 28 05:15:55 PM PDT 24
Peak memory 198820 kb
Host smart-185c36e7-1119-40ff-a360-a7be6605b97f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3812162442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.3812162442
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1431602784
Short name T356
Test name
Test status
Simulation time 43390427 ps
CPU time 0.58 seconds
Started Jun 28 04:47:12 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 194876 kb
Host smart-865841ed-d07a-48ac-b85f-2732fdb84578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431602784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1431602784
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2382391600
Short name T57
Test name
Test status
Simulation time 31705117 ps
CPU time 0.69 seconds
Started Jun 28 04:47:11 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 194756 kb
Host smart-0f49f809-d1fb-4a5d-aeba-159f18419f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382391600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2382391600
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3648099621
Short name T477
Test name
Test status
Simulation time 391307756 ps
CPU time 18.93 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 197408 kb
Host smart-b6765bb9-4ff0-43aa-831c-6a2725c94ea7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648099621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3648099621
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3623033064
Short name T482
Test name
Test status
Simulation time 466697791 ps
CPU time 0.97 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:21 PM PDT 24
Peak memory 197428 kb
Host smart-522c253d-4a29-407c-ad9d-cfa5ea41fd7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623033064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3623033064
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1704959060
Short name T701
Test name
Test status
Simulation time 60426543 ps
CPU time 0.95 seconds
Started Jun 28 04:47:16 PM PDT 24
Finished Jun 28 04:47:18 PM PDT 24
Peak memory 197296 kb
Host smart-35fa9c05-736f-43fc-b73d-7d3b7f250a39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704959060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1704959060
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.655242546
Short name T604
Test name
Test status
Simulation time 323436965 ps
CPU time 3.28 seconds
Started Jun 28 04:47:20 PM PDT 24
Finished Jun 28 04:47:26 PM PDT 24
Peak memory 198556 kb
Host smart-cc8fd871-d47a-4e6d-9eb6-d62072bd3363
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655242546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.655242546
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2649553463
Short name T462
Test name
Test status
Simulation time 149464399 ps
CPU time 1.28 seconds
Started Jun 28 04:47:11 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 196912 kb
Host smart-693fe2de-e352-4c98-997d-d6b05b95b69c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649553463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2649553463
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.4167694951
Short name T611
Test name
Test status
Simulation time 27381949 ps
CPU time 0.99 seconds
Started Jun 28 04:47:10 PM PDT 24
Finished Jun 28 04:47:12 PM PDT 24
Peak memory 196712 kb
Host smart-f42f2060-078d-4867-9580-57f27b3afc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167694951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.4167694951
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.970015295
Short name T547
Test name
Test status
Simulation time 52587346 ps
CPU time 0.77 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 195924 kb
Host smart-ab324f89-036b-4c83-9c7e-15e1ce13e4fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970015295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.970015295
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.276625929
Short name T525
Test name
Test status
Simulation time 197831096 ps
CPU time 3.27 seconds
Started Jun 28 04:47:20 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 198608 kb
Host smart-c89ae408-2003-49c8-8f83-bbfa337db3bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276625929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.276625929
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.342477566
Short name T439
Test name
Test status
Simulation time 247941738 ps
CPU time 1.26 seconds
Started Jun 28 04:47:10 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 197024 kb
Host smart-f690c594-940d-46c5-86a1-a2c4bda8d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342477566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.342477566
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.650385935
Short name T353
Test name
Test status
Simulation time 47455447 ps
CPU time 0.96 seconds
Started Jun 28 04:47:23 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 196956 kb
Host smart-0a7f593c-c106-412c-a574-8ccf22a5c408
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650385935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.650385935
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2031751666
Short name T500
Test name
Test status
Simulation time 19813982996 ps
CPU time 124.94 seconds
Started Jun 28 04:47:21 PM PDT 24
Finished Jun 28 04:49:28 PM PDT 24
Peak memory 198816 kb
Host smart-f7b71796-2d91-4dcf-ab07-afbef5ff0b37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031751666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2031751666
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1167166545
Short name T437
Test name
Test status
Simulation time 12384822 ps
CPU time 0.59 seconds
Started Jun 28 04:47:12 PM PDT 24
Finished Jun 28 04:47:14 PM PDT 24
Peak memory 194576 kb
Host smart-5356d9ce-2971-438c-a87e-0df3ad13a11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167166545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1167166545
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3219195531
Short name T358
Test name
Test status
Simulation time 161835849 ps
CPU time 0.94 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:21 PM PDT 24
Peak memory 196488 kb
Host smart-ee9c0a7d-1013-46cf-9e94-928f334f821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219195531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3219195531
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2048870867
Short name T631
Test name
Test status
Simulation time 663898107 ps
CPU time 12.7 seconds
Started Jun 28 04:47:11 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 197684 kb
Host smart-eb5fe9cd-6300-48fd-ba16-55c0c3e948d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048870867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2048870867
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2972252725
Short name T219
Test name
Test status
Simulation time 95409183 ps
CPU time 1.08 seconds
Started Jun 28 04:47:16 PM PDT 24
Finished Jun 28 04:47:18 PM PDT 24
Peak memory 197076 kb
Host smart-4169448f-cbe6-4a05-8b8f-66c1cb794606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972252725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2972252725
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1849333765
Short name T139
Test name
Test status
Simulation time 38348698 ps
CPU time 1.16 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:22 PM PDT 24
Peak memory 197084 kb
Host smart-1ef0c50f-8f3f-4ca9-8398-4f07b52eac95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849333765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1849333765
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.414453650
Short name T122
Test name
Test status
Simulation time 54084353 ps
CPU time 2.01 seconds
Started Jun 28 04:47:16 PM PDT 24
Finished Jun 28 04:47:18 PM PDT 24
Peak memory 198704 kb
Host smart-1bb14d7a-a9e7-46ca-8216-0746bccc8b97
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414453650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.414453650
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2013001351
Short name T233
Test name
Test status
Simulation time 470519559 ps
CPU time 2.33 seconds
Started Jun 28 04:47:26 PM PDT 24
Finished Jun 28 04:47:29 PM PDT 24
Peak memory 197544 kb
Host smart-009525fc-dd67-4225-8355-0d987eadf4be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013001351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2013001351
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.627273176
Short name T269
Test name
Test status
Simulation time 78035389 ps
CPU time 0.92 seconds
Started Jun 28 04:47:20 PM PDT 24
Finished Jun 28 04:47:23 PM PDT 24
Peak memory 196500 kb
Host smart-589a2cdb-a68b-4fa2-a507-2c231e51bc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627273176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.627273176
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3044813523
Short name T441
Test name
Test status
Simulation time 17117267 ps
CPU time 0.64 seconds
Started Jun 28 04:47:17 PM PDT 24
Finished Jun 28 04:47:18 PM PDT 24
Peak memory 195628 kb
Host smart-6e62c3e7-289b-479a-bb12-cb4f03a67e87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044813523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3044813523
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.751184241
Short name T577
Test name
Test status
Simulation time 3323203327 ps
CPU time 5.26 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:19 PM PDT 24
Peak memory 198744 kb
Host smart-b983301b-7cba-4025-a7a4-9a5f25730e68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751184241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.751184241
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2409397876
Short name T128
Test name
Test status
Simulation time 51888486 ps
CPU time 1.37 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:16 PM PDT 24
Peak memory 197340 kb
Host smart-aa84a05d-cd5b-4fdd-b943-ebf971851c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409397876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2409397876
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.653505971
Short name T585
Test name
Test status
Simulation time 82448203 ps
CPU time 1.27 seconds
Started Jun 28 04:47:15 PM PDT 24
Finished Jun 28 04:47:17 PM PDT 24
Peak memory 196492 kb
Host smart-4c6f77f3-fa78-4e37-ba4b-62473a97a9ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653505971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.653505971
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.263073235
Short name T429
Test name
Test status
Simulation time 6800845320 ps
CPU time 94.96 seconds
Started Jun 28 04:47:35 PM PDT 24
Finished Jun 28 04:49:12 PM PDT 24
Peak memory 198732 kb
Host smart-9ae80b12-3792-4540-b652-0d3deb95c3ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263073235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.263073235
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3752129239
Short name T561
Test name
Test status
Simulation time 58000883 ps
CPU time 0.6 seconds
Started Jun 28 04:47:12 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 194696 kb
Host smart-1c595df6-377f-4073-b075-abfb538eab67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752129239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3752129239
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2117110987
Short name T395
Test name
Test status
Simulation time 44386366 ps
CPU time 0.78 seconds
Started Jun 28 04:47:14 PM PDT 24
Finished Jun 28 04:47:15 PM PDT 24
Peak memory 195976 kb
Host smart-2bb011bc-9af0-4ed8-8c7e-eca66de52be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117110987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2117110987
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.190261978
Short name T584
Test name
Test status
Simulation time 1866812793 ps
CPU time 24.75 seconds
Started Jun 28 04:47:14 PM PDT 24
Finished Jun 28 04:47:39 PM PDT 24
Peak memory 197336 kb
Host smart-ce636d1c-7d64-428c-b76c-b962cff2a6df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190261978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.190261978
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1044584666
Short name T190
Test name
Test status
Simulation time 118225693 ps
CPU time 1.11 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:21 PM PDT 24
Peak memory 197116 kb
Host smart-d84c8499-ceee-4e99-a6f9-a2648eba8097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044584666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1044584666
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3689651865
Short name T29
Test name
Test status
Simulation time 131920815 ps
CPU time 1.23 seconds
Started Jun 28 04:47:21 PM PDT 24
Finished Jun 28 04:47:24 PM PDT 24
Peak memory 197432 kb
Host smart-eb663c91-ecf1-4214-8a37-442c961322f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689651865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3689651865
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.724843013
Short name T275
Test name
Test status
Simulation time 55570701 ps
CPU time 2.2 seconds
Started Jun 28 04:47:16 PM PDT 24
Finished Jun 28 04:47:19 PM PDT 24
Peak memory 198696 kb
Host smart-415ce5cf-83d5-4f9c-bcde-3d6b1e339361
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724843013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.724843013
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2739796027
Short name T400
Test name
Test status
Simulation time 324174898 ps
CPU time 2 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:16 PM PDT 24
Peak memory 196756 kb
Host smart-7e4eb04e-9eb6-42c6-a138-81ee3050e641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739796027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2739796027
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.4160918981
Short name T185
Test name
Test status
Simulation time 309056804 ps
CPU time 0.95 seconds
Started Jun 28 04:47:23 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 196628 kb
Host smart-19246627-1a6a-4b77-ac4d-efa0f88ebccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160918981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.4160918981
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3331359584
Short name T324
Test name
Test status
Simulation time 29017289 ps
CPU time 0.99 seconds
Started Jun 28 04:47:15 PM PDT 24
Finished Jun 28 04:47:17 PM PDT 24
Peak memory 196556 kb
Host smart-3aca13db-4b20-4cd3-8f9a-12b27be00d62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331359584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3331359584
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.892943461
Short name T588
Test name
Test status
Simulation time 1951054573 ps
CPU time 5.23 seconds
Started Jun 28 04:47:15 PM PDT 24
Finished Jun 28 04:47:21 PM PDT 24
Peak memory 198664 kb
Host smart-7a2d41de-7579-4373-a3f3-d6a3c88d7853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892943461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.892943461
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2755249550
Short name T660
Test name
Test status
Simulation time 370605262 ps
CPU time 1.26 seconds
Started Jun 28 04:47:12 PM PDT 24
Finished Jun 28 04:47:14 PM PDT 24
Peak memory 197492 kb
Host smart-ff3b79bf-96a9-40d8-b467-dd4585cefba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755249550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2755249550
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.96269473
Short name T639
Test name
Test status
Simulation time 289242002 ps
CPU time 1.32 seconds
Started Jun 28 04:47:22 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 198700 kb
Host smart-70d86cfe-2161-43ae-a3bd-38fbbb17b474
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96269473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.96269473
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.168065465
Short name T116
Test name
Test status
Simulation time 61065401185 ps
CPU time 101.4 seconds
Started Jun 28 04:47:20 PM PDT 24
Finished Jun 28 04:49:04 PM PDT 24
Peak memory 198804 kb
Host smart-2fef0a67-b4f9-4a78-92f0-e3461a790130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168065465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.168065465
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3809508988
Short name T454
Test name
Test status
Simulation time 33445845 ps
CPU time 0.57 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:20 PM PDT 24
Peak memory 194840 kb
Host smart-3585812c-18ec-49a9-8f60-0efb593706e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809508988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3809508988
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3567820476
Short name T505
Test name
Test status
Simulation time 20645337 ps
CPU time 0.64 seconds
Started Jun 28 04:47:21 PM PDT 24
Finished Jun 28 04:47:23 PM PDT 24
Peak memory 194732 kb
Host smart-4a68ef48-2923-4e1f-b47a-95032b2fd85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567820476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3567820476
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3936613006
Short name T203
Test name
Test status
Simulation time 293657026 ps
CPU time 8.75 seconds
Started Jun 28 04:47:20 PM PDT 24
Finished Jun 28 04:47:31 PM PDT 24
Peak memory 198832 kb
Host smart-1917621a-2408-4023-bf50-824cac4927e9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936613006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3936613006
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.383734214
Short name T370
Test name
Test status
Simulation time 256908486 ps
CPU time 1.07 seconds
Started Jun 28 04:47:22 PM PDT 24
Finished Jun 28 04:47:24 PM PDT 24
Peak memory 196952 kb
Host smart-fc26a044-f57c-4d86-825d-77ab5c996a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383734214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.383734214
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3079438697
Short name T492
Test name
Test status
Simulation time 76276656 ps
CPU time 1.14 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:16 PM PDT 24
Peak memory 197204 kb
Host smart-d2fc705e-3059-47d3-9363-3d9a761fd4e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079438697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3079438697
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.10496884
Short name T684
Test name
Test status
Simulation time 169491846 ps
CPU time 3.51 seconds
Started Jun 28 04:47:18 PM PDT 24
Finished Jun 28 04:47:23 PM PDT 24
Peak memory 198716 kb
Host smart-7a98155f-ecfe-4e38-b557-06ccd64b53b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10496884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.gpio_intr_with_filter_rand_intr_event.10496884
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1049845330
Short name T108
Test name
Test status
Simulation time 214865421 ps
CPU time 1.9 seconds
Started Jun 28 04:47:21 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 197840 kb
Host smart-d036460b-41ca-4021-bfe6-74c1d4fca86f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049845330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1049845330
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1582039607
Short name T528
Test name
Test status
Simulation time 118716042 ps
CPU time 1.24 seconds
Started Jun 28 04:47:20 PM PDT 24
Finished Jun 28 04:47:23 PM PDT 24
Peak memory 196536 kb
Host smart-9d49ae9b-4d1b-4bf8-9882-d4dca17ef4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582039607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1582039607
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3399890575
Short name T61
Test name
Test status
Simulation time 70668170 ps
CPU time 0.84 seconds
Started Jun 28 04:47:11 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 197824 kb
Host smart-b51c9f7f-2b94-41d9-86a9-99a4cf430e6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399890575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3399890575
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3320891565
Short name T511
Test name
Test status
Simulation time 583617011 ps
CPU time 2.73 seconds
Started Jun 28 04:47:25 PM PDT 24
Finished Jun 28 04:47:29 PM PDT 24
Peak memory 198544 kb
Host smart-3fc4c74b-1325-489c-a914-b537edf1276f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320891565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3320891565
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3022248944
Short name T157
Test name
Test status
Simulation time 52048948 ps
CPU time 0.99 seconds
Started Jun 28 04:47:22 PM PDT 24
Finished Jun 28 04:47:24 PM PDT 24
Peak memory 196144 kb
Host smart-e92c8797-55a7-4488-8571-7562d6b3c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022248944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3022248944
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3593563433
Short name T620
Test name
Test status
Simulation time 65941648 ps
CPU time 1.2 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:22 PM PDT 24
Peak memory 196236 kb
Host smart-17638a26-ac2e-49ff-8618-33a8fc2a8055
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593563433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3593563433
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2428379971
Short name T512
Test name
Test status
Simulation time 6480351312 ps
CPU time 84.13 seconds
Started Jun 28 04:47:17 PM PDT 24
Finished Jun 28 04:48:42 PM PDT 24
Peak memory 198744 kb
Host smart-5a2fee88-4a8e-466a-a653-fba59db2b78b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428379971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2428379971
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2832678530
Short name T195
Test name
Test status
Simulation time 12750081 ps
CPU time 0.62 seconds
Started Jun 28 04:47:25 PM PDT 24
Finished Jun 28 04:47:27 PM PDT 24
Peak memory 194556 kb
Host smart-64452963-f757-4ff7-a727-290763139401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832678530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2832678530
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.474442377
Short name T451
Test name
Test status
Simulation time 47474915 ps
CPU time 0.68 seconds
Started Jun 28 04:47:23 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 195260 kb
Host smart-80d26972-21bb-4b62-8b77-d5a365469f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474442377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.474442377
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.519564102
Short name T549
Test name
Test status
Simulation time 882234292 ps
CPU time 23.71 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:38 PM PDT 24
Peak memory 197592 kb
Host smart-515d1203-d099-4790-bfe2-224322a93dc2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519564102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.519564102
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3698757620
Short name T540
Test name
Test status
Simulation time 18210842 ps
CPU time 0.62 seconds
Started Jun 28 04:47:27 PM PDT 24
Finished Jun 28 04:47:29 PM PDT 24
Peak memory 194984 kb
Host smart-fe3c008a-53fc-404f-9159-27399b59f3b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698757620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3698757620
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2739034901
Short name T602
Test name
Test status
Simulation time 188806771 ps
CPU time 1.45 seconds
Started Jun 28 04:47:21 PM PDT 24
Finished Jun 28 04:47:24 PM PDT 24
Peak memory 196496 kb
Host smart-0457abaf-8f8a-435b-878d-0000e2413c32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739034901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2739034901
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1243021270
Short name T443
Test name
Test status
Simulation time 363830070 ps
CPU time 3.54 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:17 PM PDT 24
Peak memory 198628 kb
Host smart-b9d6f7b3-da6c-4440-a3ba-95db35c641e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243021270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1243021270
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.980845732
Short name T659
Test name
Test status
Simulation time 212319880 ps
CPU time 1.38 seconds
Started Jun 28 04:47:15 PM PDT 24
Finished Jun 28 04:47:18 PM PDT 24
Peak memory 197556 kb
Host smart-ec265844-a613-45aa-8acc-0b6161009887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980845732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
980845732
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2270191458
Short name T643
Test name
Test status
Simulation time 64922286 ps
CPU time 0.95 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:20 PM PDT 24
Peak memory 197400 kb
Host smart-7bf95ac0-9689-43fc-ab23-858e6ebd8ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270191458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2270191458
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.830438268
Short name T120
Test name
Test status
Simulation time 130087985 ps
CPU time 1.14 seconds
Started Jun 28 04:47:16 PM PDT 24
Finished Jun 28 04:47:18 PM PDT 24
Peak memory 196552 kb
Host smart-393b8a5a-8a5d-4a81-82b8-73c4bf597a1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830438268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.830438268
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4218230073
Short name T304
Test name
Test status
Simulation time 1193170761 ps
CPU time 3.73 seconds
Started Jun 28 04:47:23 PM PDT 24
Finished Jun 28 04:47:28 PM PDT 24
Peak memory 198704 kb
Host smart-0b67e7a8-aed3-4454-bd03-0561c5a3c761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218230073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4218230073
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3854538455
Short name T416
Test name
Test status
Simulation time 44396239 ps
CPU time 1.27 seconds
Started Jun 28 04:47:21 PM PDT 24
Finished Jun 28 04:47:24 PM PDT 24
Peak memory 196452 kb
Host smart-aab06bf9-6ac4-4f34-a985-7bae467db4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854538455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3854538455
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2422351121
Short name T535
Test name
Test status
Simulation time 150366291 ps
CPU time 1.11 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:22 PM PDT 24
Peak memory 196192 kb
Host smart-8900df0b-d7bb-43a6-80d1-3bac9151cc40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422351121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2422351121
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2614176813
Short name T8
Test name
Test status
Simulation time 35344229612 ps
CPU time 204.32 seconds
Started Jun 28 04:47:18 PM PDT 24
Finished Jun 28 04:50:43 PM PDT 24
Peak memory 198832 kb
Host smart-05f1861a-65e9-4fd1-a5bc-c86e9c8fcf52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614176813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2614176813
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1340190828
Short name T64
Test name
Test status
Simulation time 19763695407 ps
CPU time 428.89 seconds
Started Jun 28 04:47:25 PM PDT 24
Finished Jun 28 04:54:35 PM PDT 24
Peak memory 198836 kb
Host smart-aac26d95-9eb7-438a-9393-95a5d27499f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1340190828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1340190828
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3887926109
Short name T72
Test name
Test status
Simulation time 24706768 ps
CPU time 0.58 seconds
Started Jun 28 04:47:31 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 194684 kb
Host smart-ac07e074-5c62-4034-85b9-fbbf47050612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887926109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3887926109
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3507992593
Short name T161
Test name
Test status
Simulation time 16909180 ps
CPU time 0.64 seconds
Started Jun 28 04:47:29 PM PDT 24
Finished Jun 28 04:47:31 PM PDT 24
Peak memory 195252 kb
Host smart-97568c3a-c72a-4d62-a078-67b1aa155e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507992593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3507992593
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.92252258
Short name T475
Test name
Test status
Simulation time 179585196 ps
CPU time 4.01 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:58 PM PDT 24
Peak memory 196308 kb
Host smart-44f454d2-c7b1-4d72-a877-922fa61e629d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92252258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stress
.92252258
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1125190661
Short name T672
Test name
Test status
Simulation time 39172895 ps
CPU time 0.73 seconds
Started Jun 28 04:47:26 PM PDT 24
Finished Jun 28 04:47:27 PM PDT 24
Peak memory 195276 kb
Host smart-eebf3ce0-d018-4035-9a8f-041c40b04029
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125190661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1125190661
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2552158249
Short name T242
Test name
Test status
Simulation time 117172228 ps
CPU time 0.93 seconds
Started Jun 28 04:47:27 PM PDT 24
Finished Jun 28 04:47:29 PM PDT 24
Peak memory 197668 kb
Host smart-e04f5a33-132f-4dc6-89c5-ec1c06e990fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552158249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2552158249
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3682996148
Short name T508
Test name
Test status
Simulation time 187569594 ps
CPU time 3.96 seconds
Started Jun 28 04:47:28 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 198548 kb
Host smart-e7092274-6423-4e78-9761-0921426fa98f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682996148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3682996148
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1003852486
Short name T156
Test name
Test status
Simulation time 172824797 ps
CPU time 3.39 seconds
Started Jun 28 04:47:38 PM PDT 24
Finished Jun 28 04:47:43 PM PDT 24
Peak memory 197568 kb
Host smart-da1060ad-b2fb-435f-b3d8-8a921898b042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003852486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1003852486
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2850875074
Short name T609
Test name
Test status
Simulation time 216299146 ps
CPU time 1.29 seconds
Started Jun 28 04:47:14 PM PDT 24
Finished Jun 28 04:47:16 PM PDT 24
Peak memory 198028 kb
Host smart-75f5b019-0029-4ce8-8474-a54b89748590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850875074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2850875074
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.157729051
Short name T214
Test name
Test status
Simulation time 53415507 ps
CPU time 1.06 seconds
Started Jun 28 04:47:24 PM PDT 24
Finished Jun 28 04:47:26 PM PDT 24
Peak memory 196708 kb
Host smart-89c5e20d-2941-4594-8781-f380fd644cfa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157729051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.157729051
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.685591554
Short name T502
Test name
Test status
Simulation time 54495494 ps
CPU time 2.49 seconds
Started Jun 28 04:47:28 PM PDT 24
Finished Jun 28 04:47:32 PM PDT 24
Peak memory 198708 kb
Host smart-2c08195a-ad08-4d75-831e-8cdf342de0bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685591554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.685591554
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2160999392
Short name T284
Test name
Test status
Simulation time 175561384 ps
CPU time 1.29 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:21 PM PDT 24
Peak memory 198716 kb
Host smart-6c9881bd-1261-4539-ac74-23f511e8c480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160999392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2160999392
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1447115542
Short name T696
Test name
Test status
Simulation time 28270013 ps
CPU time 0.75 seconds
Started Jun 28 04:47:29 PM PDT 24
Finished Jun 28 04:47:31 PM PDT 24
Peak memory 195692 kb
Host smart-2fbc7488-0370-4c17-b7ee-c064bb6d7949
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447115542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1447115542
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1163465432
Short name T117
Test name
Test status
Simulation time 66711340463 ps
CPU time 78.46 seconds
Started Jun 28 04:47:30 PM PDT 24
Finished Jun 28 04:48:50 PM PDT 24
Peak memory 198852 kb
Host smart-f3ef3f13-2d22-40ab-9e63-c87e4b057c53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163465432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1163465432
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2726098894
Short name T565
Test name
Test status
Simulation time 50935070232 ps
CPU time 917.33 seconds
Started Jun 28 04:47:33 PM PDT 24
Finished Jun 28 05:02:51 PM PDT 24
Peak memory 198980 kb
Host smart-1382dcc9-5334-47b3-b70c-85a294805ff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2726098894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2726098894
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2869791465
Short name T559
Test name
Test status
Simulation time 41596810 ps
CPU time 0.58 seconds
Started Jun 28 04:47:41 PM PDT 24
Finished Jun 28 04:47:43 PM PDT 24
Peak memory 195448 kb
Host smart-d0675919-e296-4ec0-8661-0c551f641785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869791465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2869791465
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1815357869
Short name T557
Test name
Test status
Simulation time 33708007 ps
CPU time 0.8 seconds
Started Jun 28 04:47:40 PM PDT 24
Finished Jun 28 04:47:41 PM PDT 24
Peak memory 196788 kb
Host smart-c73ec405-1dac-4799-8fa3-457cc650415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815357869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1815357869
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.512499424
Short name T24
Test name
Test status
Simulation time 892630158 ps
CPU time 12.43 seconds
Started Jun 28 04:47:40 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 197864 kb
Host smart-34a0b127-5c73-4e08-9367-78b9993d4d3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512499424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.512499424
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.773126648
Short name T706
Test name
Test status
Simulation time 355037459 ps
CPU time 1.05 seconds
Started Jun 28 04:47:35 PM PDT 24
Finished Jun 28 04:47:38 PM PDT 24
Peak memory 197148 kb
Host smart-1b298240-e230-4426-8311-521ebbc5b40e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773126648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.773126648
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.94258817
Short name T307
Test name
Test status
Simulation time 107819716 ps
CPU time 1.45 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:51 PM PDT 24
Peak memory 197736 kb
Host smart-4cd25af2-0b2a-4e9d-a327-54123f2a5e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94258817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.94258817
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3385367303
Short name T521
Test name
Test status
Simulation time 75050073 ps
CPU time 1.01 seconds
Started Jun 28 04:47:36 PM PDT 24
Finished Jun 28 04:47:38 PM PDT 24
Peak memory 196896 kb
Host smart-572eae82-c25b-4f12-974f-2f7460199c6b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385367303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3385367303
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.481822908
Short name T551
Test name
Test status
Simulation time 202178491 ps
CPU time 3.03 seconds
Started Jun 28 04:47:32 PM PDT 24
Finished Jun 28 04:47:36 PM PDT 24
Peak memory 197724 kb
Host smart-86b756c7-8fe1-4d5d-8003-3bf0bade52d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481822908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
481822908
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3977600421
Short name T298
Test name
Test status
Simulation time 46019402 ps
CPU time 1.07 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:51 PM PDT 24
Peak memory 196708 kb
Host smart-c340d95f-cfbb-4f1a-8be7-9c8fbf1b9058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977600421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3977600421
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1161206402
Short name T526
Test name
Test status
Simulation time 51274693 ps
CPU time 1.1 seconds
Started Jun 28 04:47:37 PM PDT 24
Finished Jun 28 04:47:40 PM PDT 24
Peak memory 197316 kb
Host smart-03ab27ff-8db6-4d81-b512-5fe5d853edf8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161206402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1161206402
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3857591838
Short name T204
Test name
Test status
Simulation time 62224139 ps
CPU time 2.93 seconds
Started Jun 28 04:47:28 PM PDT 24
Finished Jun 28 04:47:32 PM PDT 24
Peak memory 198668 kb
Host smart-f10e47ca-d275-4575-9241-27c2b9c99b17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857591838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3857591838
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.923150355
Short name T280
Test name
Test status
Simulation time 73674656 ps
CPU time 1.22 seconds
Started Jun 28 04:47:31 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 196476 kb
Host smart-8ed161bd-ae60-4fdf-9e25-f45bdd15b191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923150355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.923150355
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1041559363
Short name T191
Test name
Test status
Simulation time 198581377 ps
CPU time 1.21 seconds
Started Jun 28 04:47:38 PM PDT 24
Finished Jun 28 04:47:40 PM PDT 24
Peak memory 196428 kb
Host smart-ce2aee2b-2c43-400f-810e-edcc2b9e94d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041559363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1041559363
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.4048641315
Short name T293
Test name
Test status
Simulation time 35272876129 ps
CPU time 223.08 seconds
Started Jun 28 04:47:30 PM PDT 24
Finished Jun 28 04:51:15 PM PDT 24
Peak memory 198804 kb
Host smart-202f91c4-8c9e-41d0-bfb7-246cc7a6a93a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048641315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.4048641315
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3230070697
Short name T63
Test name
Test status
Simulation time 205700438941 ps
CPU time 1558.57 seconds
Started Jun 28 04:47:27 PM PDT 24
Finished Jun 28 05:13:27 PM PDT 24
Peak memory 198844 kb
Host smart-f314c21c-539a-4118-8acb-539add2bed5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3230070697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3230070697
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3569621200
Short name T665
Test name
Test status
Simulation time 42897411 ps
CPU time 0.58 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:49 PM PDT 24
Peak memory 195372 kb
Host smart-cf1ef83b-f003-4ac5-af65-3e15e9f43d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569621200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3569621200
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3422380449
Short name T14
Test name
Test status
Simulation time 29167413 ps
CPU time 0.61 seconds
Started Jun 28 04:47:31 PM PDT 24
Finished Jun 28 04:47:32 PM PDT 24
Peak memory 194448 kb
Host smart-ca9b78db-37a0-48d1-aa0f-75cb3fbcb741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422380449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3422380449
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.438796763
Short name T180
Test name
Test status
Simulation time 960456975 ps
CPU time 26.84 seconds
Started Jun 28 04:47:25 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 197492 kb
Host smart-db086e31-f354-48bd-8e68-4efe05e3485d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438796763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.438796763
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3266231342
Short name T147
Test name
Test status
Simulation time 24323207 ps
CPU time 0.68 seconds
Started Jun 28 04:47:30 PM PDT 24
Finished Jun 28 04:47:32 PM PDT 24
Peak memory 195936 kb
Host smart-090c0ca2-c4e0-4385-8499-bb68b7b21b8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266231342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3266231342
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2061018073
Short name T319
Test name
Test status
Simulation time 87599871 ps
CPU time 0.87 seconds
Started Jun 28 04:47:32 PM PDT 24
Finished Jun 28 04:47:34 PM PDT 24
Peak memory 197208 kb
Host smart-c8f302ba-faf6-4529-8236-45a6a4324934
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061018073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2061018073
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2464423450
Short name T383
Test name
Test status
Simulation time 210882771 ps
CPU time 2.43 seconds
Started Jun 28 04:47:29 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 198780 kb
Host smart-d7c7c652-0b1c-4b84-b8c2-9bfc276cb17c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464423450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2464423450
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.92208721
Short name T467
Test name
Test status
Simulation time 88077379 ps
CPU time 0.89 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:51 PM PDT 24
Peak memory 194964 kb
Host smart-12f92187-90a0-448c-bf5a-bcc55552aedd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92208721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.92208721
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2073994757
Short name T183
Test name
Test status
Simulation time 72311686 ps
CPU time 0.72 seconds
Started Jun 28 04:47:31 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 195696 kb
Host smart-07c25481-6b70-4f65-9c90-af3d8a1495bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073994757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2073994757
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2754590170
Short name T446
Test name
Test status
Simulation time 114437603 ps
CPU time 1.13 seconds
Started Jun 28 04:47:35 PM PDT 24
Finished Jun 28 04:47:38 PM PDT 24
Peak memory 197620 kb
Host smart-ced54f5b-5eee-4da8-99af-dff0eb086223
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754590170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2754590170
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1650117721
Short name T346
Test name
Test status
Simulation time 166786267 ps
CPU time 2.11 seconds
Started Jun 28 04:47:38 PM PDT 24
Finished Jun 28 04:47:41 PM PDT 24
Peak memory 198540 kb
Host smart-9d6f0fc6-c177-4889-8853-fd652e5123b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650117721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1650117721
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1898891097
Short name T636
Test name
Test status
Simulation time 172343208 ps
CPU time 0.93 seconds
Started Jun 28 04:47:41 PM PDT 24
Finished Jun 28 04:47:42 PM PDT 24
Peak memory 197128 kb
Host smart-d3136703-698b-43e4-b3cf-d8245cabea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898891097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1898891097
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3972409786
Short name T166
Test name
Test status
Simulation time 224889139 ps
CPU time 1.28 seconds
Started Jun 28 04:47:34 PM PDT 24
Finished Jun 28 04:47:36 PM PDT 24
Peak memory 197392 kb
Host smart-8f6a0992-634d-4e17-b048-67d9084c9272
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972409786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3972409786
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2704293271
Short name T51
Test name
Test status
Simulation time 16566587559 ps
CPU time 56.4 seconds
Started Jun 28 04:47:44 PM PDT 24
Finished Jun 28 04:48:44 PM PDT 24
Peak memory 198784 kb
Host smart-ffb49e10-d7c6-44c9-912a-d9ade0428a56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704293271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2704293271
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3235633358
Short name T22
Test name
Test status
Simulation time 13947976 ps
CPU time 0.61 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 195344 kb
Host smart-2d3fc298-c65b-44ca-b92e-a54267741712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235633358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3235633358
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.911951156
Short name T317
Test name
Test status
Simulation time 39751151 ps
CPU time 0.8 seconds
Started Jun 28 04:46:51 PM PDT 24
Finished Jun 28 04:46:54 PM PDT 24
Peak memory 196004 kb
Host smart-74f07932-6609-48d0-8847-04e6b3a80e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911951156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.911951156
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.240290838
Short name T440
Test name
Test status
Simulation time 2864306187 ps
CPU time 19.51 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:47:15 PM PDT 24
Peak memory 197344 kb
Host smart-06b8adc5-95b3-4589-a225-6540556eec39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240290838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.240290838
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1770881172
Short name T246
Test name
Test status
Simulation time 30600583 ps
CPU time 0.73 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:00 PM PDT 24
Peak memory 195448 kb
Host smart-e97355e4-a5c7-4588-9446-e506ecd51c42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770881172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1770881172
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3042790676
Short name T589
Test name
Test status
Simulation time 296428924 ps
CPU time 1.16 seconds
Started Jun 28 04:46:56 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 196772 kb
Host smart-1b9bb447-5d49-4c06-9c58-ca897191ed70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042790676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3042790676
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2011998513
Short name T661
Test name
Test status
Simulation time 66850023 ps
CPU time 2.65 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 198596 kb
Host smart-b2871e44-59bf-4ce8-bc1a-f12d07f83d25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011998513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2011998513
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2550808988
Short name T606
Test name
Test status
Simulation time 103142342 ps
CPU time 1.19 seconds
Started Jun 28 04:46:52 PM PDT 24
Finished Jun 28 04:46:55 PM PDT 24
Peak memory 196404 kb
Host smart-be3885a8-f61d-43f7-a583-e707f5fefc55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550808988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2550808988
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.776020820
Short name T517
Test name
Test status
Simulation time 160579615 ps
CPU time 0.95 seconds
Started Jun 28 04:46:52 PM PDT 24
Finished Jun 28 04:46:55 PM PDT 24
Peak memory 196632 kb
Host smart-c3d6979b-acc6-434d-8901-febeba1cf294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776020820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.776020820
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2433623866
Short name T301
Test name
Test status
Simulation time 93451645 ps
CPU time 0.98 seconds
Started Jun 28 04:46:59 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 196416 kb
Host smart-378555b0-8684-4b34-ad99-38c115a317b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433623866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2433623866
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2579731769
Short name T495
Test name
Test status
Simulation time 298502789 ps
CPU time 1.39 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:00 PM PDT 24
Peak memory 198544 kb
Host smart-9ba874a4-6d3f-408e-9056-ffb72240af8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579731769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2579731769
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3842937611
Short name T53
Test name
Test status
Simulation time 251491365 ps
CPU time 0.89 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 214204 kb
Host smart-c5dfe9ec-0c0a-465d-8a07-67f683b8ab1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842937611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3842937611
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.28897582
Short name T251
Test name
Test status
Simulation time 42743491 ps
CPU time 1.32 seconds
Started Jun 28 04:46:51 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 197312 kb
Host smart-15e6ec5c-7a52-40ce-9f15-60b334939ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28897582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.28897582
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3783838911
Short name T313
Test name
Test status
Simulation time 49572081 ps
CPU time 0.96 seconds
Started Jun 28 04:47:04 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 196456 kb
Host smart-8f02e9ad-68f8-4ef0-a014-77e6ff1318b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783838911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3783838911
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3959881835
Short name T369
Test name
Test status
Simulation time 10474472099 ps
CPU time 65.31 seconds
Started Jun 28 04:46:51 PM PDT 24
Finished Jun 28 04:47:58 PM PDT 24
Peak memory 198672 kb
Host smart-99d9789f-06e5-454a-9407-53560f15da70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959881835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3959881835
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2332793167
Short name T208
Test name
Test status
Simulation time 24876304 ps
CPU time 0.61 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 195368 kb
Host smart-2cbef44e-6606-4ec8-8641-29730498da69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332793167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2332793167
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1101897493
Short name T144
Test name
Test status
Simulation time 99620647 ps
CPU time 0.79 seconds
Started Jun 28 04:47:31 PM PDT 24
Finished Jun 28 04:47:32 PM PDT 24
Peak memory 195792 kb
Host smart-9b047ba6-0306-4a32-9fac-c813e7ce32da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101897493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1101897493
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.330321731
Short name T461
Test name
Test status
Simulation time 4906797007 ps
CPU time 20.05 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:48:03 PM PDT 24
Peak memory 197412 kb
Host smart-4a822019-71b9-40ab-b630-7bc1da2ddb79
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330321731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.330321731
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2812326038
Short name T570
Test name
Test status
Simulation time 318086796 ps
CPU time 0.99 seconds
Started Jun 28 04:47:35 PM PDT 24
Finished Jun 28 04:47:38 PM PDT 24
Peak memory 197292 kb
Host smart-a29f6bad-c052-4c9d-878b-ea7d7913856c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812326038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2812326038
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.660184227
Short name T600
Test name
Test status
Simulation time 29725825 ps
CPU time 0.91 seconds
Started Jun 28 04:47:39 PM PDT 24
Finished Jun 28 04:47:41 PM PDT 24
Peak memory 198172 kb
Host smart-34a0d059-76d0-49f9-89bc-03f20299926c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660184227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.660184227
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1251488216
Short name T107
Test name
Test status
Simulation time 295075415 ps
CPU time 2.34 seconds
Started Jun 28 04:47:29 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 198572 kb
Host smart-b69030cc-ce40-434f-afb3-5f5ef81b6c12
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251488216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1251488216
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3615384192
Short name T223
Test name
Test status
Simulation time 24413493 ps
CPU time 0.9 seconds
Started Jun 28 04:47:32 PM PDT 24
Finished Jun 28 04:47:34 PM PDT 24
Peak memory 196848 kb
Host smart-e4057545-c09e-4a60-9619-1d6a7adf668c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615384192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3615384192
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.335403914
Short name T287
Test name
Test status
Simulation time 135233404 ps
CPU time 1.31 seconds
Started Jun 28 04:47:33 PM PDT 24
Finished Jun 28 04:47:35 PM PDT 24
Peak memory 197160 kb
Host smart-8e07b9dc-e023-489e-aff1-de8ec4bd00cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335403914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.335403914
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2874463821
Short name T110
Test name
Test status
Simulation time 29049501 ps
CPU time 0.99 seconds
Started Jun 28 04:47:39 PM PDT 24
Finished Jun 28 04:47:41 PM PDT 24
Peak memory 196560 kb
Host smart-2a2bbbeb-8c4f-4424-aa77-7faf5764cf7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874463821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2874463821
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.54945118
Short name T571
Test name
Test status
Simulation time 526278478 ps
CPU time 3.28 seconds
Started Jun 28 04:47:33 PM PDT 24
Finished Jun 28 04:47:37 PM PDT 24
Peak memory 198564 kb
Host smart-54a112bd-013c-40dc-be8d-8fd65358fd6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54945118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand
om_long_reg_writes_reg_reads.54945118
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1986303232
Short name T17
Test name
Test status
Simulation time 175325971 ps
CPU time 1.18 seconds
Started Jun 28 04:47:28 PM PDT 24
Finished Jun 28 04:47:31 PM PDT 24
Peak memory 196420 kb
Host smart-bed35eb8-32d1-4bf8-9070-3439d9b45fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986303232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1986303232
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.504574477
Short name T235
Test name
Test status
Simulation time 40854657 ps
CPU time 0.94 seconds
Started Jun 28 04:47:28 PM PDT 24
Finished Jun 28 04:47:30 PM PDT 24
Peak memory 197076 kb
Host smart-d091d37a-493d-489f-88aa-4e1a16e42a03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504574477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.504574477
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2283150583
Short name T651
Test name
Test status
Simulation time 15033395737 ps
CPU time 47.6 seconds
Started Jun 28 04:47:41 PM PDT 24
Finished Jun 28 04:48:29 PM PDT 24
Peak memory 198808 kb
Host smart-1e728b6b-731f-4e9b-aff0-1f276c30975d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283150583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2283150583
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2654326755
Short name T362
Test name
Test status
Simulation time 23003986 ps
CPU time 0.6 seconds
Started Jun 28 04:47:38 PM PDT 24
Finished Jun 28 04:47:40 PM PDT 24
Peak memory 194848 kb
Host smart-40cb3cb5-7821-4764-92af-5927f0bf964c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654326755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2654326755
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1651935478
Short name T314
Test name
Test status
Simulation time 74708149 ps
CPU time 0.7 seconds
Started Jun 28 04:47:36 PM PDT 24
Finished Jun 28 04:47:39 PM PDT 24
Peak memory 194636 kb
Host smart-e390eb94-5040-4fff-b648-417bd2336e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651935478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1651935478
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.214012531
Short name T310
Test name
Test status
Simulation time 2646081121 ps
CPU time 24.27 seconds
Started Jun 28 04:47:27 PM PDT 24
Finished Jun 28 04:47:52 PM PDT 24
Peak memory 197472 kb
Host smart-58147fd0-2c65-4609-bc3b-e43dc460cac5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214012531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.214012531
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1135968172
Short name T352
Test name
Test status
Simulation time 224288808 ps
CPU time 0.95 seconds
Started Jun 28 04:47:31 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 198448 kb
Host smart-a18c7004-5263-4dc9-98d3-e477c7b2354d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135968172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1135968172
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4016884776
Short name T527
Test name
Test status
Simulation time 20710316 ps
CPU time 0.69 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:47:44 PM PDT 24
Peak memory 195776 kb
Host smart-b70d9da3-852d-4f11-8971-2460c3713350
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016884776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4016884776
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.334390499
Short name T582
Test name
Test status
Simulation time 78610589 ps
CPU time 2.81 seconds
Started Jun 28 04:47:41 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 197008 kb
Host smart-7463fa0f-0bc4-4f0d-b229-4dd74572fec0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334390499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.334390499
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3902245251
Short name T333
Test name
Test status
Simulation time 191764412 ps
CPU time 2.67 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:58 PM PDT 24
Peak memory 196488 kb
Host smart-586fe328-102e-465a-af68-19f1bee68c67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902245251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3902245251
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1203520423
Short name T153
Test name
Test status
Simulation time 78517997 ps
CPU time 0.95 seconds
Started Jun 28 04:47:38 PM PDT 24
Finished Jun 28 04:47:40 PM PDT 24
Peak memory 196632 kb
Host smart-f8e07d83-7cd9-4a11-af30-f9cf4e62d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203520423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1203520423
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2576278901
Short name T350
Test name
Test status
Simulation time 54822679 ps
CPU time 1.11 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 196412 kb
Host smart-beb0bf7d-ff66-48ba-bd90-60673f42dcf8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576278901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2576278901
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1025088128
Short name T673
Test name
Test status
Simulation time 111725460 ps
CPU time 4.67 seconds
Started Jun 28 04:47:26 PM PDT 24
Finished Jun 28 04:47:31 PM PDT 24
Peak memory 198480 kb
Host smart-36f96b6d-9e3e-4814-b93a-32b18b946c5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025088128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1025088128
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4151261081
Short name T424
Test name
Test status
Simulation time 29546444 ps
CPU time 0.98 seconds
Started Jun 28 04:47:30 PM PDT 24
Finished Jun 28 04:47:32 PM PDT 24
Peak memory 196380 kb
Host smart-121142f8-0e3a-466e-ad39-47d64816ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151261081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4151261081
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3604323450
Short name T398
Test name
Test status
Simulation time 36868116 ps
CPU time 1.11 seconds
Started Jun 28 04:47:31 PM PDT 24
Finished Jun 28 04:47:33 PM PDT 24
Peak memory 196372 kb
Host smart-50a926b7-7659-4fff-8a89-4d8957b2419e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604323450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3604323450
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.473952446
Short name T330
Test name
Test status
Simulation time 5173400946 ps
CPU time 55.13 seconds
Started Jun 28 04:47:33 PM PDT 24
Finished Jun 28 04:48:29 PM PDT 24
Peak memory 198836 kb
Host smart-e60b21bc-0a05-4456-abd4-f550be157db7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473952446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.473952446
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1361657011
Short name T19
Test name
Test status
Simulation time 315736553730 ps
CPU time 1007.33 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 05:04:36 PM PDT 24
Peak memory 207196 kb
Host smart-763277d1-81f3-430c-adf4-2ab16f6064cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1361657011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1361657011
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.507010117
Short name T586
Test name
Test status
Simulation time 38461837 ps
CPU time 0.55 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:51 PM PDT 24
Peak memory 193464 kb
Host smart-fccdcaa8-6ca0-4291-aee1-7271de70bb62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507010117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.507010117
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2872865241
Short name T507
Test name
Test status
Simulation time 72704782 ps
CPU time 0.65 seconds
Started Jun 28 04:47:41 PM PDT 24
Finished Jun 28 04:47:42 PM PDT 24
Peak memory 194732 kb
Host smart-17329d97-33da-44c2-895d-db4d45a436f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872865241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2872865241
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2030279772
Short name T627
Test name
Test status
Simulation time 1731338501 ps
CPU time 3.78 seconds
Started Jun 28 04:47:28 PM PDT 24
Finished Jun 28 04:47:32 PM PDT 24
Peak memory 197240 kb
Host smart-6722f224-f220-43c1-a40c-355a153e4b2c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030279772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2030279772
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1370579712
Short name T290
Test name
Test status
Simulation time 96942069 ps
CPU time 1.13 seconds
Started Jun 28 04:47:44 PM PDT 24
Finished Jun 28 04:47:49 PM PDT 24
Peak memory 197124 kb
Host smart-09955665-7b99-41b5-aa12-1dc659dce588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370579712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1370579712
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2728603466
Short name T354
Test name
Test status
Simulation time 352131741 ps
CPU time 1.36 seconds
Started Jun 28 04:47:44 PM PDT 24
Finished Jun 28 04:47:49 PM PDT 24
Peak memory 197880 kb
Host smart-9cb71d63-51a9-4d26-bb70-5621abbeac49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728603466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2728603466
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2831086326
Short name T278
Test name
Test status
Simulation time 79435869 ps
CPU time 0.93 seconds
Started Jun 28 04:47:44 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 196936 kb
Host smart-ec236de9-86c4-4445-88eb-5344de4f08de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831086326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2831086326
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.325657927
Short name T686
Test name
Test status
Simulation time 454790410 ps
CPU time 2.92 seconds
Started Jun 28 04:47:38 PM PDT 24
Finished Jun 28 04:47:42 PM PDT 24
Peak memory 198716 kb
Host smart-367d6867-2d57-44da-bf6f-5c8010353a87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325657927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
325657927
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.59384694
Short name T614
Test name
Test status
Simulation time 48460229 ps
CPU time 0.79 seconds
Started Jun 28 04:47:32 PM PDT 24
Finished Jun 28 04:47:34 PM PDT 24
Peak memory 196592 kb
Host smart-1fa75f5f-ab9e-49b3-923b-8f84afb22252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59384694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.59384694
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1791975909
Short name T646
Test name
Test status
Simulation time 38458126 ps
CPU time 0.96 seconds
Started Jun 28 04:47:28 PM PDT 24
Finished Jun 28 04:47:30 PM PDT 24
Peak memory 197128 kb
Host smart-08111b65-3a3c-40f4-9f93-0219e3336ce3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791975909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1791975909
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3450085837
Short name T334
Test name
Test status
Simulation time 125183291 ps
CPU time 1.85 seconds
Started Jun 28 04:47:35 PM PDT 24
Finished Jun 28 04:47:39 PM PDT 24
Peak memory 198648 kb
Host smart-2e902232-b555-405c-9662-8b89f833a813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450085837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3450085837
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.562609870
Short name T566
Test name
Test status
Simulation time 73561115 ps
CPU time 1.1 seconds
Started Jun 28 04:47:40 PM PDT 24
Finished Jun 28 04:47:42 PM PDT 24
Peak memory 198748 kb
Host smart-ded02d73-88ec-43e5-98e0-500b7ad6e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562609870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.562609870
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3242198756
Short name T387
Test name
Test status
Simulation time 251253113 ps
CPU time 1.27 seconds
Started Jun 28 04:47:32 PM PDT 24
Finished Jun 28 04:47:34 PM PDT 24
Peak memory 196468 kb
Host smart-cb832101-9968-4b5b-8717-a7d448bca01a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242198756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3242198756
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.842279184
Short name T391
Test name
Test status
Simulation time 3253575692 ps
CPU time 91.87 seconds
Started Jun 28 04:47:44 PM PDT 24
Finished Jun 28 04:49:18 PM PDT 24
Peak memory 198672 kb
Host smart-9db7a49d-f454-40a6-a42d-2518788ba388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842279184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.842279184
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3950133798
Short name T630
Test name
Test status
Simulation time 11512405 ps
CPU time 0.55 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:49 PM PDT 24
Peak memory 195360 kb
Host smart-181179a2-d674-49d2-9afb-3e337af32824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950133798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3950133798
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.64786770
Short name T487
Test name
Test status
Simulation time 37329139 ps
CPU time 0.94 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:47:52 PM PDT 24
Peak memory 197848 kb
Host smart-009000c5-dedc-4146-adca-c88be5b08111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64786770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.64786770
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4026012433
Short name T491
Test name
Test status
Simulation time 422331390 ps
CPU time 5.2 seconds
Started Jun 28 04:47:35 PM PDT 24
Finished Jun 28 04:47:42 PM PDT 24
Peak memory 197368 kb
Host smart-e5e4945b-8a0c-4d56-8a80-ed286eb99820
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026012433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4026012433
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.777279006
Short name T390
Test name
Test status
Simulation time 218042701 ps
CPU time 0.87 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:47:46 PM PDT 24
Peak memory 197460 kb
Host smart-3cde02c5-0941-4267-b025-06741a082cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777279006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.777279006
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3285203975
Short name T216
Test name
Test status
Simulation time 64159523 ps
CPU time 1.23 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:50 PM PDT 24
Peak memory 197532 kb
Host smart-a882f3db-801c-4e80-942d-ebae9d03580a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285203975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3285203975
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.257935824
Short name T691
Test name
Test status
Simulation time 94451057 ps
CPU time 3.67 seconds
Started Jun 28 04:48:02 PM PDT 24
Finished Jun 28 04:48:07 PM PDT 24
Peak memory 198688 kb
Host smart-e77fbde3-5f5f-43ad-b15d-d8ac121973a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257935824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.257935824
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3788530562
Short name T668
Test name
Test status
Simulation time 163561497 ps
CPU time 2.96 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 197884 kb
Host smart-51d9ce5a-721f-4d7d-9f1d-3177aa88244c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788530562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3788530562
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1020130903
Short name T336
Test name
Test status
Simulation time 71373427 ps
CPU time 0.88 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 196708 kb
Host smart-085ac315-381b-4976-abcf-483e36a3f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020130903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1020130903
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.66329953
Short name T155
Test name
Test status
Simulation time 26303048 ps
CPU time 0.91 seconds
Started Jun 28 04:47:37 PM PDT 24
Finished Jun 28 04:47:40 PM PDT 24
Peak memory 197200 kb
Host smart-075868ec-48e0-4207-8c5d-ab08aa9bb9d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66329953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup_
pulldown.66329953
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1059560032
Short name T624
Test name
Test status
Simulation time 3197937524 ps
CPU time 5.67 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 198740 kb
Host smart-443fb6b6-f75c-43b1-a97d-c3ebf0096d7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059560032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1059560032
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.124683025
Short name T179
Test name
Test status
Simulation time 77852236 ps
CPU time 1.49 seconds
Started Jun 28 04:47:44 PM PDT 24
Finished Jun 28 04:47:49 PM PDT 24
Peak memory 197228 kb
Host smart-4491a21a-209a-47b5-8321-42276713c57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124683025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.124683025
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3792372717
Short name T361
Test name
Test status
Simulation time 157163000 ps
CPU time 1.35 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:47:47 PM PDT 24
Peak memory 196148 kb
Host smart-8e9af9a9-6cbe-4d78-b7b2-3ad9be0a157c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792372717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3792372717
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3464786987
Short name T241
Test name
Test status
Simulation time 11445066036 ps
CPU time 148.49 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:50:14 PM PDT 24
Peak memory 198640 kb
Host smart-3ee7080e-3438-4ebf-8efd-e040e02a4b1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464786987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3464786987
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2549865885
Short name T312
Test name
Test status
Simulation time 87292336 ps
CPU time 0.57 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 194564 kb
Host smart-dc2c18fa-ef5c-4871-bdb9-bcd8992ed497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549865885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2549865885
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3368444202
Short name T694
Test name
Test status
Simulation time 240895460 ps
CPU time 0.91 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:49 PM PDT 24
Peak memory 197932 kb
Host smart-5b2c383d-fc1b-4c54-addc-b689fddc8d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368444202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3368444202
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3346293919
Short name T252
Test name
Test status
Simulation time 813119257 ps
CPU time 7.68 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:48:02 PM PDT 24
Peak memory 198624 kb
Host smart-b68e579e-8356-47c5-8da4-e501669d9f24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346293919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3346293919
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4153187226
Short name T675
Test name
Test status
Simulation time 89749182 ps
CPU time 0.65 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 195912 kb
Host smart-467b8e31-a3a2-433d-a83b-7deefafac051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153187226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4153187226
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.241666066
Short name T569
Test name
Test status
Simulation time 33356362 ps
CPU time 0.98 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 196712 kb
Host smart-63d9136e-a6ef-4187-8bbe-7c5cf23aae9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241666066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.241666066
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1480024310
Short name T617
Test name
Test status
Simulation time 89587853 ps
CPU time 3.68 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 198788 kb
Host smart-075c9043-1970-4236-96f5-22514e3e0a75
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480024310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1480024310
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.461190347
Short name T300
Test name
Test status
Simulation time 120162256 ps
CPU time 1.57 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 197160 kb
Host smart-8a8b34c0-7cfd-4aad-acc3-d2fabf405a3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461190347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
461190347
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.271862521
Short name T474
Test name
Test status
Simulation time 27010409 ps
CPU time 1.04 seconds
Started Jun 28 04:47:53 PM PDT 24
Finished Jun 28 04:47:58 PM PDT 24
Peak memory 196748 kb
Host smart-5cb10def-ab0b-48dd-9875-b0141086096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271862521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.271862521
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3600627657
Short name T124
Test name
Test status
Simulation time 74289830 ps
CPU time 1.27 seconds
Started Jun 28 04:47:44 PM PDT 24
Finished Jun 28 04:47:49 PM PDT 24
Peak memory 197720 kb
Host smart-d37e58da-7e16-430c-a413-a1d6fd3e6690
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600627657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3600627657
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2273135945
Short name T165
Test name
Test status
Simulation time 152538307 ps
CPU time 2.62 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:47:46 PM PDT 24
Peak memory 198460 kb
Host smart-3519938c-a42e-4fd1-91c1-3d9a0d765a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273135945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2273135945
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3227940167
Short name T340
Test name
Test status
Simulation time 350139401 ps
CPU time 0.98 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:51 PM PDT 24
Peak memory 196036 kb
Host smart-4b2ca17b-bd52-4a76-9d51-e41e5c85d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227940167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3227940167
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3799953141
Short name T466
Test name
Test status
Simulation time 56883530 ps
CPU time 1.17 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:50 PM PDT 24
Peak memory 196512 kb
Host smart-a26937cf-1ec0-41bb-bf8c-dbdb89fa7053
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799953141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3799953141
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2818835544
Short name T410
Test name
Test status
Simulation time 19618229856 ps
CPU time 140.57 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:50:15 PM PDT 24
Peak memory 198808 kb
Host smart-ff66af0e-bf2e-4ef2-a942-9f08fadda1cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818835544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2818835544
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2827990044
Short name T67
Test name
Test status
Simulation time 25077218591 ps
CPU time 544.12 seconds
Started Jun 28 04:47:55 PM PDT 24
Finished Jun 28 04:57:02 PM PDT 24
Peak memory 198852 kb
Host smart-a0455786-aae0-424c-a280-9d324f2fcd62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2827990044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2827990044
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.273756099
Short name T653
Test name
Test status
Simulation time 38846095 ps
CPU time 0.55 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 195412 kb
Host smart-f6f76851-fffa-4895-9577-2668d0c68716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273756099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.273756099
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1953234537
Short name T476
Test name
Test status
Simulation time 27684991 ps
CPU time 0.73 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 196488 kb
Host smart-823c782a-57b9-447e-a7dc-b9f0e87b78f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953234537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1953234537
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.736646387
Short name T404
Test name
Test status
Simulation time 1641265005 ps
CPU time 14.81 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:48:05 PM PDT 24
Peak memory 197420 kb
Host smart-d14bac8b-3077-4f4a-9e02-160e91d946d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736646387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.736646387
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1979758870
Short name T54
Test name
Test status
Simulation time 67814934 ps
CPU time 1.02 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:47:46 PM PDT 24
Peak memory 197048 kb
Host smart-dca2d2f9-ad04-42d2-9147-df54bd324fcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979758870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1979758870
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.624787571
Short name T245
Test name
Test status
Simulation time 22657057 ps
CPU time 0.73 seconds
Started Jun 28 04:47:44 PM PDT 24
Finished Jun 28 04:47:48 PM PDT 24
Peak memory 196140 kb
Host smart-58758cef-f380-4b89-b91b-00ee9a4b2674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624787571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.624787571
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3213014309
Short name T106
Test name
Test status
Simulation time 133945227 ps
CPU time 1.45 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 198740 kb
Host smart-d31e924e-82b6-4108-9d37-8914a1ef9ddb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213014309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3213014309
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.814883749
Short name T215
Test name
Test status
Simulation time 239853122 ps
CPU time 3.82 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:47:50 PM PDT 24
Peak memory 197724 kb
Host smart-a374730a-beb0-4ab2-ab2e-cbf50d2a56f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814883749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
814883749
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.503870618
Short name T374
Test name
Test status
Simulation time 154490965 ps
CPU time 1.03 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 196520 kb
Host smart-d7ba75e2-9109-4afc-8ff5-3f3bf26ddeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503870618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.503870618
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4218224429
Short name T56
Test name
Test status
Simulation time 83632461 ps
CPU time 1.3 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 197632 kb
Host smart-2ccff94f-f569-49f7-aee4-d37ae3afebfb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218224429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4218224429
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2009802172
Short name T123
Test name
Test status
Simulation time 172687151 ps
CPU time 1.89 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 198588 kb
Host smart-1abbda35-68d7-4db2-b74f-485ead5f9248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009802172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2009802172
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2836203882
Short name T612
Test name
Test status
Simulation time 127696614 ps
CPU time 1.01 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 196452 kb
Host smart-74d13fdf-9551-4b7b-832e-810ec4717393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836203882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2836203882
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3983101033
Short name T138
Test name
Test status
Simulation time 63277691 ps
CPU time 1.15 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:47:46 PM PDT 24
Peak memory 197164 kb
Host smart-ee9f9baf-ad2c-400e-a9f7-3dc39f7ccdac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983101033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3983101033
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1214101231
Short name T325
Test name
Test status
Simulation time 22229083886 ps
CPU time 51.42 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:48:40 PM PDT 24
Peak memory 198804 kb
Host smart-0d6e48da-c52b-4f67-a881-042bc406bc43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214101231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1214101231
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1226603557
Short name T367
Test name
Test status
Simulation time 52612501551 ps
CPU time 269.3 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:52:14 PM PDT 24
Peak memory 198940 kb
Host smart-9491bfce-edab-42d5-aa57-bbc00beffa4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1226603557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1226603557
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3945577721
Short name T168
Test name
Test status
Simulation time 48855361 ps
CPU time 0.59 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 194860 kb
Host smart-2d3dfe85-43a7-49a6-b717-42990b7a0cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945577721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3945577721
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3724637600
Short name T292
Test name
Test status
Simulation time 23919541 ps
CPU time 0.68 seconds
Started Jun 28 04:47:40 PM PDT 24
Finished Jun 28 04:47:41 PM PDT 24
Peak memory 194804 kb
Host smart-ce63c153-f26a-4fdf-903a-4657ecb632f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724637600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3724637600
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1831444227
Short name T170
Test name
Test status
Simulation time 1300061751 ps
CPU time 3.68 seconds
Started Jun 28 04:47:41 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 196316 kb
Host smart-117d7326-7de9-4f2c-adb0-e22c57adea9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831444227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1831444227
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2655199175
Short name T364
Test name
Test status
Simulation time 24723839 ps
CPU time 0.66 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 195256 kb
Host smart-9509b29f-cee9-46cc-be48-4a8a700e70b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655199175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2655199175
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.885625709
Short name T224
Test name
Test status
Simulation time 49408446 ps
CPU time 1.27 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 197764 kb
Host smart-c01927b5-a083-47e0-a545-fe6a161e64c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885625709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.885625709
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3184678881
Short name T328
Test name
Test status
Simulation time 35521483 ps
CPU time 1.55 seconds
Started Jun 28 04:47:58 PM PDT 24
Finished Jun 28 04:48:01 PM PDT 24
Peak memory 198692 kb
Host smart-853ae5b3-0f78-4ad3-98e7-3c80de98d662
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184678881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3184678881
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2928035290
Short name T109
Test name
Test status
Simulation time 762433192 ps
CPU time 3.4 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:57 PM PDT 24
Peak memory 196520 kb
Host smart-2f5de800-fba1-4f88-8b83-ebac828440d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928035290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2928035290
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3853004916
Short name T316
Test name
Test status
Simulation time 63501674 ps
CPU time 1.2 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:51 PM PDT 24
Peak memory 197316 kb
Host smart-3d4cc46a-7e07-456c-afe9-9b2d96f09db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853004916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3853004916
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4141312506
Short name T498
Test name
Test status
Simulation time 78233536 ps
CPU time 0.86 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 197340 kb
Host smart-79bd5a84-70d9-4366-a222-5fa3ac90252c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141312506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4141312506
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2992592927
Short name T552
Test name
Test status
Simulation time 265190998 ps
CPU time 3.25 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:52 PM PDT 24
Peak memory 198656 kb
Host smart-28a67e77-89f4-408e-9ec6-ad3071b90913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992592927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2992592927
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2775281599
Short name T671
Test name
Test status
Simulation time 341064876 ps
CPU time 1.31 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:47:47 PM PDT 24
Peak memory 196208 kb
Host smart-5d5e3f2b-d18e-4c6c-8b74-ff5e20e34462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775281599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2775281599
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1711317845
Short name T385
Test name
Test status
Simulation time 68352145 ps
CPU time 1.2 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:50 PM PDT 24
Peak memory 198664 kb
Host smart-0d03fc65-a8d2-4384-b0bd-fb4b6769c4f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711317845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1711317845
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3010612121
Short name T277
Test name
Test status
Simulation time 80597068848 ps
CPU time 210.46 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:51:22 PM PDT 24
Peak memory 198812 kb
Host smart-cf623201-9b22-4b23-9960-d8204f0c0ac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010612121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3010612121
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1652400266
Short name T66
Test name
Test status
Simulation time 12209220177 ps
CPU time 284.39 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:52:37 PM PDT 24
Peak memory 198904 kb
Host smart-34922737-e838-4b2b-bd81-01d0456fec8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1652400266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1652400266
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3063720488
Short name T550
Test name
Test status
Simulation time 20405947 ps
CPU time 0.62 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 194544 kb
Host smart-abbe7a2e-cb60-4330-8cb3-4ec51cbc9bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063720488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3063720488
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1120179553
Short name T338
Test name
Test status
Simulation time 405371410 ps
CPU time 0.88 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 197184 kb
Host smart-38b3ab78-4343-4b43-bc91-19f83c22aa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120179553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1120179553
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.490423529
Short name T678
Test name
Test status
Simulation time 1070091020 ps
CPU time 9 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 197456 kb
Host smart-2f52f0ed-4864-412a-b1bb-e28d72c88152
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490423529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.490423529
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.982481297
Short name T412
Test name
Test status
Simulation time 150153864 ps
CPU time 0.79 seconds
Started Jun 28 04:47:54 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 195796 kb
Host smart-24c39df7-7bad-4cb9-98c8-4cd3a9a753db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982481297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.982481297
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.243756604
Short name T590
Test name
Test status
Simulation time 17981802 ps
CPU time 0.67 seconds
Started Jun 28 04:47:55 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 195588 kb
Host smart-3d882e53-9241-4465-b366-e0a541ed2fab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243756604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.243756604
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2738679158
Short name T222
Test name
Test status
Simulation time 86136618 ps
CPU time 3.25 seconds
Started Jun 28 04:47:45 PM PDT 24
Finished Jun 28 04:47:52 PM PDT 24
Peak memory 196992 kb
Host smart-fd45b164-c3ae-458b-9f68-d91b5b121e90
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738679158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2738679158
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.980123308
Short name T230
Test name
Test status
Simulation time 66351149 ps
CPU time 2.14 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 198724 kb
Host smart-9bfcc3cf-967e-49e7-b2b1-00e93eb8684a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980123308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
980123308
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2837030077
Short name T483
Test name
Test status
Simulation time 58029058 ps
CPU time 0.63 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:50 PM PDT 24
Peak memory 195092 kb
Host smart-eeb1c8b8-abe3-471b-b3e3-172c59ccef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837030077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2837030077
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.303530359
Short name T142
Test name
Test status
Simulation time 109384763 ps
CPU time 1.19 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:47:53 PM PDT 24
Peak memory 197912 kb
Host smart-c0e5940a-c1c7-4840-8299-83a6141fba42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303530359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.303530359
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1306785536
Short name T175
Test name
Test status
Simulation time 89640563 ps
CPU time 1.79 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 198600 kb
Host smart-5375ebef-4e02-4105-9527-93781020c437
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306785536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1306785536
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3958718703
Short name T192
Test name
Test status
Simulation time 311367264 ps
CPU time 0.93 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 197204 kb
Host smart-c398875a-f50c-406a-8de5-df27d3fab912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958718703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3958718703
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.447191758
Short name T432
Test name
Test status
Simulation time 285731488 ps
CPU time 1.24 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 196496 kb
Host smart-ebc80f4e-859f-4b5c-bd13-1770d195b6ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447191758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.447191758
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.413525744
Short name T426
Test name
Test status
Simulation time 37180302358 ps
CPU time 215.24 seconds
Started Jun 28 04:47:42 PM PDT 24
Finished Jun 28 04:51:19 PM PDT 24
Peak memory 199004 kb
Host smart-6aa06c6d-976c-4d96-9e0d-adcee70c2ba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413525744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.413525744
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.4073822110
Short name T430
Test name
Test status
Simulation time 13113748 ps
CPU time 0.62 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 194740 kb
Host smart-a586d5b5-3adc-4b0d-b8db-7227230b114d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073822110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.4073822110
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3705916123
Short name T459
Test name
Test status
Simulation time 62587379 ps
CPU time 0.68 seconds
Started Jun 28 04:47:43 PM PDT 24
Finished Jun 28 04:47:45 PM PDT 24
Peak memory 194668 kb
Host smart-c0af12c8-dfc7-4983-b3c2-ad98de0415be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705916123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3705916123
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1053573368
Short name T126
Test name
Test status
Simulation time 313516724 ps
CPU time 14.86 seconds
Started Jun 28 04:48:01 PM PDT 24
Finished Jun 28 04:48:18 PM PDT 24
Peak memory 197472 kb
Host smart-e6532e39-12ba-45db-a2ac-86f75b648992
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053573368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1053573368
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1080585274
Short name T479
Test name
Test status
Simulation time 34131583 ps
CPU time 0.74 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 196020 kb
Host smart-aed01a6f-000e-47c6-adb8-cd81221cb234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080585274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1080585274
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3954689124
Short name T655
Test name
Test status
Simulation time 104513930 ps
CPU time 1.37 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:52 PM PDT 24
Peak memory 197612 kb
Host smart-38329823-eda9-49a3-afcb-016a76d5becc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954689124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3954689124
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.919166982
Short name T371
Test name
Test status
Simulation time 36712632 ps
CPU time 1.38 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 196984 kb
Host smart-ae1a3c4b-9d2d-4268-ad68-e145e884d2d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919166982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.919166982
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2283818992
Short name T164
Test name
Test status
Simulation time 77672244 ps
CPU time 1.39 seconds
Started Jun 28 04:47:54 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 197560 kb
Host smart-772cfd15-8cd5-4558-9bb7-4245c439355a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283818992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2283818992
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.93620880
Short name T211
Test name
Test status
Simulation time 53614336 ps
CPU time 1.35 seconds
Started Jun 28 04:47:36 PM PDT 24
Finished Jun 28 04:47:40 PM PDT 24
Peak memory 198660 kb
Host smart-b8f02296-23ba-4273-8035-42f78e51744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93620880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.93620880
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.393259970
Short name T580
Test name
Test status
Simulation time 32685406 ps
CPU time 1.23 seconds
Started Jun 28 04:47:54 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 196604 kb
Host smart-302c8d0d-3e15-4498-9d63-8de35c5d3a07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393259970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.393259970
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.842566113
Short name T237
Test name
Test status
Simulation time 486609605 ps
CPU time 2.33 seconds
Started Jun 28 04:48:01 PM PDT 24
Finished Jun 28 04:48:05 PM PDT 24
Peak memory 198796 kb
Host smart-f2883310-4ac5-4717-9884-0976f44a39db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842566113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.842566113
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1272546510
Short name T159
Test name
Test status
Simulation time 177442942 ps
CPU time 0.99 seconds
Started Jun 28 04:47:46 PM PDT 24
Finished Jun 28 04:47:52 PM PDT 24
Peak memory 197212 kb
Host smart-c8495639-3a9f-4640-bc83-cb535b8552e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272546510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1272546510
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1457884697
Short name T27
Test name
Test status
Simulation time 60203155 ps
CPU time 0.93 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 196344 kb
Host smart-0b1b2116-2d2f-4c32-9337-fcb239f0e9a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457884697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1457884697
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3443347234
Short name T501
Test name
Test status
Simulation time 44745309902 ps
CPU time 144.89 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:50:19 PM PDT 24
Peak memory 198808 kb
Host smart-9660d2b4-5597-41f3-93d8-20ec65288857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443347234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3443347234
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.272146576
Short name T548
Test name
Test status
Simulation time 52198026844 ps
CPU time 1460.16 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 05:12:22 PM PDT 24
Peak memory 198908 kb
Host smart-171121b5-0b2a-427f-aba3-55e474f49682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=272146576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.272146576
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.100512919
Short name T447
Test name
Test status
Simulation time 14006830 ps
CPU time 0.61 seconds
Started Jun 28 04:48:05 PM PDT 24
Finished Jun 28 04:48:07 PM PDT 24
Peak memory 195576 kb
Host smart-3e465026-1a6f-4244-bab4-6bd747dd48d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100512919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.100512919
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3763002485
Short name T151
Test name
Test status
Simulation time 32586582 ps
CPU time 0.79 seconds
Started Jun 28 04:47:55 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 196060 kb
Host smart-ec1c8fda-67f0-4660-b9be-695296788b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763002485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3763002485
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2648914720
Short name T554
Test name
Test status
Simulation time 2671604814 ps
CPU time 18.82 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 197588 kb
Host smart-0feb667a-c7ac-4745-9e76-903a84af646d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648914720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2648914720
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3143413995
Short name T595
Test name
Test status
Simulation time 373307714 ps
CPU time 0.9 seconds
Started Jun 28 04:47:55 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 197748 kb
Host smart-634c3cf0-c2fb-479a-b627-d794d1241763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143413995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3143413995
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.444778877
Short name T329
Test name
Test status
Simulation time 18343678 ps
CPU time 0.72 seconds
Started Jun 28 04:47:54 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 194940 kb
Host smart-162b2cae-08e1-4a22-aabb-c0505de7888f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444778877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.444778877
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.742098849
Short name T135
Test name
Test status
Simulation time 139640074 ps
CPU time 2.92 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 197060 kb
Host smart-67da3951-b659-4878-8d74-cbce5fad70ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742098849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.742098849
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3142463188
Short name T711
Test name
Test status
Simulation time 553475007 ps
CPU time 2.73 seconds
Started Jun 28 04:47:51 PM PDT 24
Finished Jun 28 04:47:58 PM PDT 24
Peak memory 198792 kb
Host smart-b2854d83-530b-44bd-bb4c-59ff18955d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142463188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3142463188
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1760763316
Short name T431
Test name
Test status
Simulation time 29952102 ps
CPU time 1.11 seconds
Started Jun 28 04:47:58 PM PDT 24
Finished Jun 28 04:48:01 PM PDT 24
Peak memory 196780 kb
Host smart-15cab32e-4583-4aa0-8bf7-b689de1d4757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760763316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1760763316
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3619265591
Short name T635
Test name
Test status
Simulation time 33212459 ps
CPU time 0.7 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 194896 kb
Host smart-5fc4c486-fc25-457c-a5f5-c51a1f5ef852
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619265591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3619265591
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.863369779
Short name T202
Test name
Test status
Simulation time 952613444 ps
CPU time 3.69 seconds
Started Jun 28 04:48:01 PM PDT 24
Finished Jun 28 04:48:06 PM PDT 24
Peak memory 198612 kb
Host smart-f12c26d9-ae51-4966-b434-de4e6bee61de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863369779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.863369779
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1334364801
Short name T513
Test name
Test status
Simulation time 173931974 ps
CPU time 1.1 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:02 PM PDT 24
Peak memory 196504 kb
Host smart-98d4b085-56eb-4079-bbb3-ba22a93e7847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334364801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1334364801
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3651471335
Short name T326
Test name
Test status
Simulation time 124304627 ps
CPU time 1.13 seconds
Started Jun 28 04:47:56 PM PDT 24
Finished Jun 28 04:48:00 PM PDT 24
Peak memory 196236 kb
Host smart-ada1163c-6fba-48b3-92dc-6203f676455f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651471335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3651471335
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2620541581
Short name T282
Test name
Test status
Simulation time 61333660681 ps
CPU time 126.8 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:50:14 PM PDT 24
Peak memory 198796 kb
Host smart-51314ad6-3692-488e-bcfc-802cf3b45315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620541581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2620541581
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.356067772
Short name T244
Test name
Test status
Simulation time 32681696 ps
CPU time 0.58 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 194716 kb
Host smart-2b4b5924-644a-4489-9238-b85f6d45f037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356067772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.356067772
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3660999363
Short name T543
Test name
Test status
Simulation time 48602620 ps
CPU time 0.84 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 197108 kb
Host smart-0c94f539-04d4-4065-b772-8dbe0c82c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660999363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3660999363
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.431602692
Short name T629
Test name
Test status
Simulation time 635823623 ps
CPU time 6.11 seconds
Started Jun 28 04:46:56 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 198684 kb
Host smart-bffc53ca-d612-4a64-926a-44be75ea50d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431602692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.431602692
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2163598569
Short name T131
Test name
Test status
Simulation time 192997005 ps
CPU time 0.88 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:46:59 PM PDT 24
Peak memory 196728 kb
Host smart-79863720-81c8-4873-a251-c95c9e11027b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163598569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2163598569
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1762799696
Short name T306
Test name
Test status
Simulation time 52330527 ps
CPU time 1.37 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:57 PM PDT 24
Peak memory 197864 kb
Host smart-838524a7-9f41-472e-90a4-9846d3f18d58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762799696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1762799696
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.672565446
Short name T645
Test name
Test status
Simulation time 273094473 ps
CPU time 3.04 seconds
Started Jun 28 04:46:56 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 198628 kb
Host smart-07bf5c84-5e98-4a5f-a70c-e0f045c8b7b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672565446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.672565446
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3498622516
Short name T596
Test name
Test status
Simulation time 100439469 ps
CPU time 1.03 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 196284 kb
Host smart-f51b6915-1444-4b12-a4fb-52dd091ea621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498622516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3498622516
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3152339426
Short name T388
Test name
Test status
Simulation time 60748690 ps
CPU time 1.06 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:00 PM PDT 24
Peak memory 198704 kb
Host smart-7de8028c-2e69-4b94-8e04-22cbb74c31ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152339426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3152339426
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.521154269
Short name T423
Test name
Test status
Simulation time 407361261 ps
CPU time 1.35 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:57 PM PDT 24
Peak memory 197640 kb
Host smart-42a83ef6-a67e-4e3d-b6f9-aba0731c5555
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521154269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.521154269
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1210717929
Short name T449
Test name
Test status
Simulation time 547740695 ps
CPU time 5.85 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:04 PM PDT 24
Peak memory 198660 kb
Host smart-56c67165-b270-472d-8b1a-e902b2e34d7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210717929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1210717929
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2364527224
Short name T38
Test name
Test status
Simulation time 254917612 ps
CPU time 0.8 seconds
Started Jun 28 04:46:52 PM PDT 24
Finished Jun 28 04:46:54 PM PDT 24
Peak memory 214224 kb
Host smart-f5020e93-b6ff-4b01-8075-5dd930c3ed18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364527224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2364527224
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1834770841
Short name T394
Test name
Test status
Simulation time 151816997 ps
CPU time 1.13 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:57 PM PDT 24
Peak memory 196376 kb
Host smart-62b5b509-2bbd-4182-8b34-5877d72bfbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834770841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1834770841
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2263895586
Short name T522
Test name
Test status
Simulation time 164211908 ps
CPU time 1.36 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:57 PM PDT 24
Peak memory 198560 kb
Host smart-182572ef-4043-421d-8063-6b0829f1d518
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263895586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2263895586
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1241029833
Short name T605
Test name
Test status
Simulation time 2878996302 ps
CPU time 40.52 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:47:36 PM PDT 24
Peak memory 198700 kb
Host smart-dbc67011-8cb5-4040-96e0-bc9352278efe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241029833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1241029833
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3582816639
Short name T13
Test name
Test status
Simulation time 13162082 ps
CPU time 0.58 seconds
Started Jun 28 04:47:57 PM PDT 24
Finished Jun 28 04:48:00 PM PDT 24
Peak memory 194692 kb
Host smart-d6c63651-61c2-40af-b031-22c5b41b1d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582816639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3582816639
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3408777587
Short name T494
Test name
Test status
Simulation time 69273733 ps
CPU time 0.87 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 197636 kb
Host smart-e33424be-77b9-4a8f-addf-72d6c41de7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408777587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3408777587
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.4262241655
Short name T690
Test name
Test status
Simulation time 528555721 ps
CPU time 6.28 seconds
Started Jun 28 04:47:54 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 196120 kb
Host smart-19ca7c67-72b5-4c5a-a6d9-35e22716b138
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262241655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.4262241655
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1311827927
Short name T702
Test name
Test status
Simulation time 168926165 ps
CPU time 0.79 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 196624 kb
Host smart-701df844-e51e-4313-81ce-deb1568f4abb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311827927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1311827927
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.362756707
Short name T434
Test name
Test status
Simulation time 179151725 ps
CPU time 1.31 seconds
Started Jun 28 04:47:53 PM PDT 24
Finished Jun 28 04:47:58 PM PDT 24
Peak memory 197792 kb
Host smart-7b784736-da19-426d-b045-07c266e2e3f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362756707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.362756707
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.633486469
Short name T514
Test name
Test status
Simulation time 233422967 ps
CPU time 2.46 seconds
Started Jun 28 04:47:56 PM PDT 24
Finished Jun 28 04:48:01 PM PDT 24
Peak memory 198484 kb
Host smart-54188d00-edba-4adf-8e3e-59d62abb82ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633486469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.633486469
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.184421736
Short name T137
Test name
Test status
Simulation time 132993710 ps
CPU time 2.5 seconds
Started Jun 28 04:47:58 PM PDT 24
Finished Jun 28 04:48:02 PM PDT 24
Peak memory 197604 kb
Host smart-b43824c1-0ee8-44b6-98c6-f120316e5706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184421736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
184421736
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2101772266
Short name T289
Test name
Test status
Simulation time 31104025 ps
CPU time 0.88 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:02 PM PDT 24
Peak memory 196168 kb
Host smart-1b9f25fc-e370-4775-bd9b-45c762953882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101772266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2101772266
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2915770294
Short name T58
Test name
Test status
Simulation time 45503375 ps
CPU time 0.78 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 196148 kb
Host smart-74fa9e14-135e-4fd2-89c7-ae9bd7b296d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915770294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2915770294
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2296908312
Short name T453
Test name
Test status
Simulation time 787332806 ps
CPU time 4.15 seconds
Started Jun 28 04:47:57 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 198648 kb
Host smart-f9641376-b629-45e0-b144-0e540f1c152b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296908312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2296908312
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2086514948
Short name T286
Test name
Test status
Simulation time 146616256 ps
CPU time 0.96 seconds
Started Jun 28 04:47:54 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 196104 kb
Host smart-50021039-d890-4a8e-a78b-84436122fdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086514948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2086514948
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.555789625
Short name T411
Test name
Test status
Simulation time 28365622 ps
CPU time 0.9 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 197128 kb
Host smart-f4724505-18d2-4f2c-9098-2110c4ddbdcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555789625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.555789625
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3852742303
Short name T469
Test name
Test status
Simulation time 29879176853 ps
CPU time 193.2 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:51:21 PM PDT 24
Peak memory 198812 kb
Host smart-52df6bb5-a16c-403c-9186-8a5fb2b0fcd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852742303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3852742303
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3662117870
Short name T485
Test name
Test status
Simulation time 103428856 ps
CPU time 0.61 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:47:52 PM PDT 24
Peak memory 194680 kb
Host smart-2157c2f7-0503-4418-9ceb-56c4a82fbdb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662117870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3662117870
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2825465023
Short name T197
Test name
Test status
Simulation time 49119364 ps
CPU time 0.92 seconds
Started Jun 28 04:47:56 PM PDT 24
Finished Jun 28 04:48:00 PM PDT 24
Peak memory 197140 kb
Host smart-c5c22afc-4c6c-400e-a03b-2a8ca6a4f72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825465023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2825465023
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.4119153756
Short name T654
Test name
Test status
Simulation time 117442306 ps
CPU time 5.51 seconds
Started Jun 28 04:47:51 PM PDT 24
Finished Jun 28 04:48:01 PM PDT 24
Peak memory 197404 kb
Host smart-e50c7916-c478-4799-b50a-b5eb4a8d3952
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119153756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.4119153756
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2667775376
Short name T652
Test name
Test status
Simulation time 168388712 ps
CPU time 0.79 seconds
Started Jun 28 04:47:51 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 197128 kb
Host smart-d7245f0c-eef5-4360-a0e5-fff60801337d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667775376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2667775376
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2713807506
Short name T240
Test name
Test status
Simulation time 286172299 ps
CPU time 0.77 seconds
Started Jun 28 04:47:54 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 196072 kb
Host smart-885bdb86-cf7a-4796-8f4f-f3d2a7342670
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713807506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2713807506
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.508601256
Short name T365
Test name
Test status
Simulation time 55372718 ps
CPU time 2.19 seconds
Started Jun 28 04:47:52 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 198648 kb
Host smart-faf4245c-2c35-49cb-bdf9-4dbf5b0a2e90
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508601256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.508601256
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2685090788
Short name T408
Test name
Test status
Simulation time 55554231 ps
CPU time 1.82 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 197392 kb
Host smart-081e6ca9-77c4-4d11-8754-124e6899495e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685090788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2685090788
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3343987357
Short name T272
Test name
Test status
Simulation time 277020883 ps
CPU time 1.22 seconds
Started Jun 28 04:47:55 PM PDT 24
Finished Jun 28 04:48:00 PM PDT 24
Peak memory 196572 kb
Host smart-5925b6de-5ed8-4426-9b68-348c761325f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343987357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3343987357
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3294373467
Short name T260
Test name
Test status
Simulation time 52704977 ps
CPU time 1.25 seconds
Started Jun 28 04:47:51 PM PDT 24
Finished Jun 28 04:47:57 PM PDT 24
Peak memory 197336 kb
Host smart-c4c8b48e-30aa-460f-8677-d906b127159b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294373467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3294373467
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3999783699
Short name T714
Test name
Test status
Simulation time 1715045695 ps
CPU time 4.93 seconds
Started Jun 28 04:47:56 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 198556 kb
Host smart-9854437c-cfc7-408c-a2d1-d4c7a11abb42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999783699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3999783699
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2099920847
Short name T510
Test name
Test status
Simulation time 162305058 ps
CPU time 1.18 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 196928 kb
Host smart-5caf00f2-87ab-472a-9d0e-d462daf43130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099920847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2099920847
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2476708979
Short name T231
Test name
Test status
Simulation time 41976158 ps
CPU time 1.23 seconds
Started Jun 28 04:47:50 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 198660 kb
Host smart-b165e079-819f-4600-8dc4-aacff10281dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476708979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2476708979
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2386951190
Short name T378
Test name
Test status
Simulation time 12206962948 ps
CPU time 105.63 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:49:57 PM PDT 24
Peak memory 198808 kb
Host smart-5d1e9c3f-5405-4ac1-9be2-c70a6deab5b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386951190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2386951190
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2860055874
Short name T634
Test name
Test status
Simulation time 12340112 ps
CPU time 0.57 seconds
Started Jun 28 04:48:11 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 194764 kb
Host smart-8bdfd3a7-2d3e-4fa9-b2d1-434ed9ac582c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860055874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2860055874
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.4133951352
Short name T698
Test name
Test status
Simulation time 183279973 ps
CPU time 0.88 seconds
Started Jun 28 04:48:01 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 197028 kb
Host smart-f16b956d-0533-438c-ab6f-f9a91c9c694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133951352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.4133951352
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3047411972
Short name T463
Test name
Test status
Simulation time 720030271 ps
CPU time 26.3 seconds
Started Jun 28 04:47:47 PM PDT 24
Finished Jun 28 04:48:18 PM PDT 24
Peak memory 197632 kb
Host smart-db934dce-29ab-4a26-9ccd-fb245866c221
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047411972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3047411972
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3216681924
Short name T15
Test name
Test status
Simulation time 113039840 ps
CPU time 0.76 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:48:09 PM PDT 24
Peak memory 195572 kb
Host smart-be77fa8d-94f9-42f1-aed4-80e8cc804d8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216681924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3216681924
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3159862879
Short name T662
Test name
Test status
Simulation time 59470744 ps
CPU time 0.96 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:10 PM PDT 24
Peak memory 196784 kb
Host smart-79a8d82d-b15a-44e2-af53-16f15a6f8dd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159862879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3159862879
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3612356626
Short name T484
Test name
Test status
Simulation time 91832843 ps
CPU time 3.31 seconds
Started Jun 28 04:48:05 PM PDT 24
Finished Jun 28 04:48:09 PM PDT 24
Peak memory 198700 kb
Host smart-9b01c3a9-1081-4475-a922-c7b0635c8708
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612356626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3612356626
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.787773066
Short name T633
Test name
Test status
Simulation time 729552910 ps
CPU time 3 seconds
Started Jun 28 04:47:48 PM PDT 24
Finished Jun 28 04:47:56 PM PDT 24
Peak memory 197820 kb
Host smart-b213b66b-5626-4f46-9602-aa6d54dd11a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787773066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
787773066
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3388629380
Short name T243
Test name
Test status
Simulation time 143639625 ps
CPU time 1.01 seconds
Started Jun 28 04:47:55 PM PDT 24
Finished Jun 28 04:47:59 PM PDT 24
Peak memory 196592 kb
Host smart-ed42abb4-ab8b-4790-9934-fda8eb38bcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388629380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3388629380
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1700053526
Short name T496
Test name
Test status
Simulation time 37713041 ps
CPU time 0.98 seconds
Started Jun 28 04:47:51 PM PDT 24
Finished Jun 28 04:47:57 PM PDT 24
Peak memory 196700 kb
Host smart-c6e754f8-7134-41da-af6d-940c82084efb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700053526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1700053526
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2638737645
Short name T414
Test name
Test status
Simulation time 177327429 ps
CPU time 1.24 seconds
Started Jun 28 04:48:03 PM PDT 24
Finished Jun 28 04:48:06 PM PDT 24
Peak memory 198680 kb
Host smart-113429a9-7494-4b74-ace3-b274f43518a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638737645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2638737645
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1716485167
Short name T613
Test name
Test status
Simulation time 165041029 ps
CPU time 1.34 seconds
Started Jun 28 04:47:52 PM PDT 24
Finished Jun 28 04:47:58 PM PDT 24
Peak memory 197392 kb
Host smart-aae849e3-69fe-49c7-b1f8-03ee0a5f6e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716485167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1716485167
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.842997899
Short name T713
Test name
Test status
Simulation time 163745700 ps
CPU time 1.29 seconds
Started Jun 28 04:47:59 PM PDT 24
Finished Jun 28 04:48:02 PM PDT 24
Peak memory 197404 kb
Host smart-c0d040c5-031b-4f5c-9218-a502a75d74ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842997899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.842997899
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3545787288
Short name T295
Test name
Test status
Simulation time 46268815265 ps
CPU time 214.66 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:51:45 PM PDT 24
Peak memory 198832 kb
Host smart-77e5f127-6615-4036-ab90-82492ddec1f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545787288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3545787288
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.4065631753
Short name T218
Test name
Test status
Simulation time 18942489 ps
CPU time 0.57 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:02 PM PDT 24
Peak memory 194488 kb
Host smart-3c01c5bd-1fec-4164-adfd-4c77eeb09ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065631753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.4065631753
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3984856688
Short name T196
Test name
Test status
Simulation time 79116075 ps
CPU time 0.65 seconds
Started Jun 28 04:48:02 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 194656 kb
Host smart-104f596f-037b-4b5f-b0b0-c977d8efa79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984856688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3984856688
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1055040416
Short name T291
Test name
Test status
Simulation time 797524004 ps
CPU time 27.21 seconds
Started Jun 28 04:47:56 PM PDT 24
Finished Jun 28 04:48:30 PM PDT 24
Peak memory 197416 kb
Host smart-ade76b67-b0c3-412c-8ec0-f292479af7ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055040416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1055040416
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.466838267
Short name T355
Test name
Test status
Simulation time 895932395 ps
CPU time 0.96 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:03 PM PDT 24
Peak memory 197076 kb
Host smart-94e2fbfd-10dd-49de-8616-2ec0fe1bdfe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466838267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.466838267
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.331444424
Short name T337
Test name
Test status
Simulation time 226202468 ps
CPU time 1.06 seconds
Started Jun 28 04:48:02 PM PDT 24
Finished Jun 28 04:48:05 PM PDT 24
Peak memory 197388 kb
Host smart-3bde25b6-9efc-40c1-9fd7-6aee632f6768
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331444424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.331444424
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.970391060
Short name T392
Test name
Test status
Simulation time 56773724 ps
CPU time 2.25 seconds
Started Jun 28 04:47:59 PM PDT 24
Finished Jun 28 04:48:03 PM PDT 24
Peak memory 198672 kb
Host smart-56e0d25d-426c-4823-a2a9-8da379aff849
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970391060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.970391060
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1179805757
Short name T273
Test name
Test status
Simulation time 2093026418 ps
CPU time 2.06 seconds
Started Jun 28 04:48:06 PM PDT 24
Finished Jun 28 04:48:09 PM PDT 24
Peak memory 197444 kb
Host smart-890f48d1-e332-4925-ad9b-2cacbc20a334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179805757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1179805757
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1533934548
Short name T373
Test name
Test status
Simulation time 84391933 ps
CPU time 1.04 seconds
Started Jun 28 04:48:05 PM PDT 24
Finished Jun 28 04:48:07 PM PDT 24
Peak memory 196716 kb
Host smart-6eaa55fe-6731-4b6c-ba24-c52ff8d3ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533934548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1533934548
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.365943304
Short name T705
Test name
Test status
Simulation time 69879749 ps
CPU time 1.29 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 04:48:23 PM PDT 24
Peak memory 197708 kb
Host smart-28702dd9-b08c-432a-bf72-e75443b3039a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365943304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.365943304
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2643296670
Short name T670
Test name
Test status
Simulation time 164338579 ps
CPU time 3.55 seconds
Started Jun 28 04:47:58 PM PDT 24
Finished Jun 28 04:48:03 PM PDT 24
Peak memory 198244 kb
Host smart-87f35dfb-5782-4daf-999c-8762be7c984e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643296670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2643296670
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1266159350
Short name T493
Test name
Test status
Simulation time 46620626 ps
CPU time 1.28 seconds
Started Jun 28 04:48:16 PM PDT 24
Finished Jun 28 04:48:18 PM PDT 24
Peak memory 197532 kb
Host smart-04e6d264-2ccd-4764-b5ce-47c995a2481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266159350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1266159350
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.698029682
Short name T133
Test name
Test status
Simulation time 266870385 ps
CPU time 0.94 seconds
Started Jun 28 04:47:49 PM PDT 24
Finished Jun 28 04:47:55 PM PDT 24
Peak memory 196948 kb
Host smart-045faae7-a8c2-42ec-a836-8d482be26792
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698029682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.698029682
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1539506732
Short name T380
Test name
Test status
Simulation time 3951555259 ps
CPU time 95.76 seconds
Started Jun 28 04:48:01 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 198712 kb
Host smart-f687aded-d9ef-4931-801c-02fcdb1c4fa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539506732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1539506732
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.592602586
Short name T516
Test name
Test status
Simulation time 42068755 ps
CPU time 0.57 seconds
Started Jun 28 04:48:02 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 195260 kb
Host smart-0ef283dd-d020-4dfb-b120-103500285270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592602586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.592602586
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3394244756
Short name T377
Test name
Test status
Simulation time 37197053 ps
CPU time 0.85 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:10 PM PDT 24
Peak memory 196872 kb
Host smart-dda4fcb7-460a-43df-a36c-07ded8da9e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394244756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3394244756
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.233853017
Short name T69
Test name
Test status
Simulation time 1089459865 ps
CPU time 18.5 seconds
Started Jun 28 04:48:01 PM PDT 24
Finished Jun 28 04:48:22 PM PDT 24
Peak memory 197448 kb
Host smart-e08eb918-92a4-432c-8d03-2d0da0085787
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233853017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.233853017
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1899364586
Short name T703
Test name
Test status
Simulation time 60816104 ps
CPU time 0.62 seconds
Started Jun 28 04:48:02 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 194916 kb
Host smart-b954b005-45cf-4a7e-8b8a-7ed6cfc917da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899364586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1899364586
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.218477130
Short name T226
Test name
Test status
Simulation time 99422086 ps
CPU time 1.53 seconds
Started Jun 28 04:47:56 PM PDT 24
Finished Jun 28 04:48:01 PM PDT 24
Peak memory 197720 kb
Host smart-fceb74e4-bf03-494f-8b53-b3b288c60752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218477130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.218477130
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.910226884
Short name T545
Test name
Test status
Simulation time 121716676 ps
CPU time 0.99 seconds
Started Jun 28 04:47:59 PM PDT 24
Finished Jun 28 04:48:01 PM PDT 24
Peak memory 196228 kb
Host smart-0a4b0fc5-c632-40ce-b0bf-fd0e0c0c50a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910226884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
910226884
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2894050803
Short name T171
Test name
Test status
Simulation time 122540740 ps
CPU time 1.2 seconds
Started Jun 28 04:47:59 PM PDT 24
Finished Jun 28 04:48:01 PM PDT 24
Peak memory 197608 kb
Host smart-84d8f9fc-a4d2-48f5-9449-b4eced37b36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894050803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2894050803
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2377329468
Short name T228
Test name
Test status
Simulation time 16648023 ps
CPU time 0.76 seconds
Started Jun 28 04:48:04 PM PDT 24
Finished Jun 28 04:48:06 PM PDT 24
Peak memory 196804 kb
Host smart-67c944c9-ebcc-48e2-b9cf-79dd1672e701
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377329468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2377329468
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3124614970
Short name T603
Test name
Test status
Simulation time 127785912 ps
CPU time 1.64 seconds
Started Jun 28 04:48:06 PM PDT 24
Finished Jun 28 04:48:08 PM PDT 24
Peak memory 198636 kb
Host smart-dc825042-23a0-4c1a-b477-2ad212266012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124614970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3124614970
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3406040311
Short name T274
Test name
Test status
Simulation time 42210293 ps
CPU time 1.11 seconds
Started Jun 28 04:48:01 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 196528 kb
Host smart-193e54df-dd78-4976-bf0e-00dcd2b36fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406040311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3406040311
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3543336108
Short name T403
Test name
Test status
Simulation time 66302383 ps
CPU time 1.21 seconds
Started Jun 28 04:47:56 PM PDT 24
Finished Jun 28 04:48:00 PM PDT 24
Peak memory 197208 kb
Host smart-c8944ca9-24f0-4e19-83d8-cb802cf27561
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543336108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3543336108
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3555256501
Short name T7
Test name
Test status
Simulation time 24446393228 ps
CPU time 137 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:50:38 PM PDT 24
Peak memory 198704 kb
Host smart-7ceb4993-f96a-4ccb-ac4d-052acf2aadc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555256501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3555256501
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3051591449
Short name T322
Test name
Test status
Simulation time 29642533 ps
CPU time 0.55 seconds
Started Jun 28 04:47:52 PM PDT 24
Finished Jun 28 04:47:57 PM PDT 24
Peak memory 194200 kb
Host smart-19eafa6c-19ed-4192-9474-98e69b29c795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051591449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3051591449
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3472650893
Short name T506
Test name
Test status
Simulation time 26190911 ps
CPU time 0.77 seconds
Started Jun 28 04:48:09 PM PDT 24
Finished Jun 28 04:48:10 PM PDT 24
Peak memory 194832 kb
Host smart-663290d2-2306-4773-b5cc-ee372daa776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472650893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3472650893
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1364862553
Short name T178
Test name
Test status
Simulation time 1865840381 ps
CPU time 14.11 seconds
Started Jun 28 04:48:01 PM PDT 24
Finished Jun 28 04:48:17 PM PDT 24
Peak memory 197684 kb
Host smart-ed70b66d-7209-4976-b149-990e4ca5f695
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364862553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1364862553
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3582878531
Short name T232
Test name
Test status
Simulation time 849428555 ps
CPU time 0.81 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 196692 kb
Host smart-a7d6710e-0496-4e5b-9ff7-69840cb7d73b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582878531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3582878531
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.424782375
Short name T425
Test name
Test status
Simulation time 36445679 ps
CPU time 1.05 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:03 PM PDT 24
Peak memory 197220 kb
Host smart-9c53ef79-777d-41c5-b7e7-e06f4ac264d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424782375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.424782375
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3736511855
Short name T205
Test name
Test status
Simulation time 103431831 ps
CPU time 1.23 seconds
Started Jun 28 04:47:59 PM PDT 24
Finished Jun 28 04:48:01 PM PDT 24
Peak memory 197444 kb
Host smart-8c4b3863-2b0f-42dc-acf2-a15d2b42466a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736511855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3736511855
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2493009395
Short name T339
Test name
Test status
Simulation time 180299528 ps
CPU time 3.33 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:05 PM PDT 24
Peak memory 198740 kb
Host smart-961f8ab1-3164-4646-864a-0136c071b711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493009395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2493009395
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3719314855
Short name T529
Test name
Test status
Simulation time 789807710 ps
CPU time 1.39 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:03 PM PDT 24
Peak memory 197256 kb
Host smart-ae8c4193-ccf8-4fe1-a97c-d0664f87c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719314855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3719314855
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2847365274
Short name T648
Test name
Test status
Simulation time 134412828 ps
CPU time 1.21 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 197680 kb
Host smart-8d9f2d06-aee5-4bcb-9d99-9c67db87a3eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847365274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2847365274
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.202890451
Short name T344
Test name
Test status
Simulation time 559356812 ps
CPU time 2.62 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:11 PM PDT 24
Peak memory 198428 kb
Host smart-da64edff-4454-4d19-8347-ada38dcf915d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202890451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.202890451
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3716754651
Short name T160
Test name
Test status
Simulation time 59692267 ps
CPU time 0.88 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 195900 kb
Host smart-a104c64a-92d5-4916-aeb4-fa4fc2e22135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716754651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3716754651
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1512901861
Short name T318
Test name
Test status
Simulation time 715924455 ps
CPU time 1.37 seconds
Started Jun 28 04:48:06 PM PDT 24
Finished Jun 28 04:48:08 PM PDT 24
Peak memory 197384 kb
Host smart-956b34bc-aaaa-4cb0-b920-2725ffb29cc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512901861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1512901861
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.828871956
Short name T710
Test name
Test status
Simulation time 7773640797 ps
CPU time 79.54 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:49:31 PM PDT 24
Peak memory 198808 kb
Host smart-564f0802-a57f-4c63-b492-dd31401c9110
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828871956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.828871956
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1627186424
Short name T413
Test name
Test status
Simulation time 15346336822 ps
CPU time 342.78 seconds
Started Jun 28 04:48:04 PM PDT 24
Finished Jun 28 04:53:48 PM PDT 24
Peak memory 198944 kb
Host smart-e1265a23-899d-432b-bd3d-52a11686be23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1627186424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1627186424
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3320247962
Short name T125
Test name
Test status
Simulation time 54128450 ps
CPU time 0.56 seconds
Started Jun 28 04:48:14 PM PDT 24
Finished Jun 28 04:48:15 PM PDT 24
Peak memory 194680 kb
Host smart-fec917e2-1705-43ee-b0f1-4db180733892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320247962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3320247962
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1349606012
Short name T182
Test name
Test status
Simulation time 72500785 ps
CPU time 0.84 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:48:09 PM PDT 24
Peak memory 196668 kb
Host smart-374858f7-596b-4cb2-8bbf-63fc4626a5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349606012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1349606012
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3790543257
Short name T335
Test name
Test status
Simulation time 1367030752 ps
CPU time 22.55 seconds
Started Jun 28 04:48:06 PM PDT 24
Finished Jun 28 04:48:29 PM PDT 24
Peak memory 196228 kb
Host smart-cac28d82-df92-4200-89d2-ac4fb46522f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790543257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3790543257
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3145481989
Short name T345
Test name
Test status
Simulation time 70306353 ps
CPU time 0.93 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:10 PM PDT 24
Peak memory 197864 kb
Host smart-cce8aafd-5f12-4eeb-a8e3-ba1774a7f956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145481989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3145481989
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.232687743
Short name T460
Test name
Test status
Simulation time 116339302 ps
CPU time 0.84 seconds
Started Jun 28 04:48:05 PM PDT 24
Finished Jun 28 04:48:06 PM PDT 24
Peak memory 196228 kb
Host smart-ce472289-34dc-4d07-bbee-bc2d261a3aeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232687743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.232687743
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.687119660
Short name T638
Test name
Test status
Simulation time 215230363 ps
CPU time 1.32 seconds
Started Jun 28 04:47:59 PM PDT 24
Finished Jun 28 04:48:02 PM PDT 24
Peak memory 197456 kb
Host smart-c67dbe86-7a29-43d8-910c-73a0053029b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687119660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.687119660
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.4010145385
Short name T212
Test name
Test status
Simulation time 589522409 ps
CPU time 1.73 seconds
Started Jun 28 04:48:09 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 197420 kb
Host smart-b5b45fd5-ac57-4a4b-82b8-6e5ca48af205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010145385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.4010145385
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.312054381
Short name T420
Test name
Test status
Simulation time 24307756 ps
CPU time 0.9 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:48:09 PM PDT 24
Peak memory 196752 kb
Host smart-e09dae72-6c90-4b99-8768-e4734c953a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312054381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.312054381
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.82320485
Short name T657
Test name
Test status
Simulation time 274917879 ps
CPU time 0.78 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:10 PM PDT 24
Peak memory 196144 kb
Host smart-64a4fb87-9c3d-41e4-be6f-0a80cdf8df1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82320485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup_
pulldown.82320485
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_smoke.2919189455
Short name T397
Test name
Test status
Simulation time 285062669 ps
CPU time 1.22 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:03 PM PDT 24
Peak memory 198580 kb
Host smart-c92e06d5-c7ab-4979-ad84-af17f222c795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919189455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2919189455
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2084395226
Short name T348
Test name
Test status
Simulation time 72051438 ps
CPU time 1.38 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:48:17 PM PDT 24
Peak memory 197416 kb
Host smart-f8a848d6-3dd2-42dc-8b0b-376fcea8ad97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084395226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2084395226
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2245044080
Short name T531
Test name
Test status
Simulation time 2364083794 ps
CPU time 59.42 seconds
Started Jun 28 04:48:36 PM PDT 24
Finished Jun 28 04:49:35 PM PDT 24
Peak memory 198804 kb
Host smart-e25306a2-affc-4d5c-b3ed-6ec543124667
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245044080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2245044080
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.532609708
Short name T315
Test name
Test status
Simulation time 17715097 ps
CPU time 0.6 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:48:09 PM PDT 24
Peak memory 195352 kb
Host smart-2ae57711-83ec-463b-84fb-fe3f94087c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532609708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.532609708
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3042070912
Short name T568
Test name
Test status
Simulation time 174655666 ps
CPU time 0.86 seconds
Started Jun 28 04:48:05 PM PDT 24
Finished Jun 28 04:48:07 PM PDT 24
Peak memory 196980 kb
Host smart-cb0f4b26-e65f-4fd8-bccd-883fba145de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042070912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3042070912
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2088635843
Short name T115
Test name
Test status
Simulation time 1001063202 ps
CPU time 19.94 seconds
Started Jun 28 04:48:19 PM PDT 24
Finished Jun 28 04:48:40 PM PDT 24
Peak memory 198724 kb
Host smart-c19aa306-ef05-43b6-bbd5-7b35e7e0ba00
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088635843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2088635843
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3453182709
Short name T572
Test name
Test status
Simulation time 433016880 ps
CPU time 1.08 seconds
Started Jun 28 04:48:16 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 197324 kb
Host smart-af89b9cb-579b-4ba6-a62f-303959ffb13f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453182709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3453182709
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3503705980
Short name T533
Test name
Test status
Simulation time 452909961 ps
CPU time 1.31 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 197732 kb
Host smart-bcd0de80-327b-435c-83d3-bb6412ad764f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503705980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3503705980
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.501628706
Short name T667
Test name
Test status
Simulation time 108473448 ps
CPU time 2.94 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:16 PM PDT 24
Peak memory 198604 kb
Host smart-3489ce64-fdcf-45b6-905e-fd464a8f9ac1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501628706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.501628706
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.454051700
Short name T509
Test name
Test status
Simulation time 250742596 ps
CPU time 1.43 seconds
Started Jun 28 04:48:00 PM PDT 24
Finished Jun 28 04:48:04 PM PDT 24
Peak memory 196824 kb
Host smart-1b4985ac-c713-400a-9f25-817eb32b9215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454051700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
454051700
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3278499476
Short name T259
Test name
Test status
Simulation time 87870185 ps
CPU time 0.67 seconds
Started Jun 28 04:48:14 PM PDT 24
Finished Jun 28 04:48:16 PM PDT 24
Peak memory 195044 kb
Host smart-af362a66-6842-4953-865e-d7a9a053a743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278499476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3278499476
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3495929539
Short name T173
Test name
Test status
Simulation time 91224031 ps
CPU time 0.95 seconds
Started Jun 28 04:48:13 PM PDT 24
Finished Jun 28 04:48:15 PM PDT 24
Peak memory 196524 kb
Host smart-21baf856-cc7d-41b3-9890-b866f50bb2af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495929539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3495929539
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1196277164
Short name T363
Test name
Test status
Simulation time 369745528 ps
CPU time 4.42 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 198536 kb
Host smart-83203e7a-5bb6-4256-b0d4-af53cce7d589
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196277164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1196277164
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2939439556
Short name T311
Test name
Test status
Simulation time 58323242 ps
CPU time 1.1 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:34 PM PDT 24
Peak memory 196260 kb
Host smart-909b01f2-8430-4df4-9fe5-81fcd22623e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939439556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2939439556
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1084551559
Short name T497
Test name
Test status
Simulation time 80963397 ps
CPU time 1.22 seconds
Started Jun 28 04:48:03 PM PDT 24
Finished Jun 28 04:48:05 PM PDT 24
Peak memory 197400 kb
Host smart-e0811d68-dafb-435c-b678-4cee6e9f1156
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084551559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1084551559
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3334041838
Short name T279
Test name
Test status
Simulation time 92876235739 ps
CPU time 194.62 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:51:31 PM PDT 24
Peak memory 198876 kb
Host smart-83eba825-a61b-4a2b-992b-ecef38245d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334041838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3334041838
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3738629283
Short name T351
Test name
Test status
Simulation time 37933994 ps
CPU time 0.61 seconds
Started Jun 28 04:48:03 PM PDT 24
Finished Jun 28 04:48:05 PM PDT 24
Peak memory 195720 kb
Host smart-148898f4-7278-4f9c-8935-2d78bbb489e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738629283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3738629283
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.508448425
Short name T114
Test name
Test status
Simulation time 82375309 ps
CPU time 0.72 seconds
Started Jun 28 04:48:23 PM PDT 24
Finished Jun 28 04:48:25 PM PDT 24
Peak memory 195868 kb
Host smart-f24a5eac-66ca-46c2-ac1e-e0f9a629f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508448425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.508448425
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3236314291
Short name T689
Test name
Test status
Simulation time 2220222752 ps
CPU time 17.8 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:31 PM PDT 24
Peak memory 198752 kb
Host smart-8ab5c034-0f08-4acc-b845-16f9f4bc04f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236314291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3236314291
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.98108569
Short name T150
Test name
Test status
Simulation time 321794229 ps
CPU time 0.88 seconds
Started Jun 28 04:49:34 PM PDT 24
Finished Jun 28 04:49:37 PM PDT 24
Peak memory 198112 kb
Host smart-0d9131b1-2ec4-469b-9d6c-68b42b41846d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98108569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.98108569
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1045982057
Short name T470
Test name
Test status
Simulation time 57162564 ps
CPU time 0.81 seconds
Started Jun 28 04:48:14 PM PDT 24
Finished Jun 28 04:48:16 PM PDT 24
Peak memory 196200 kb
Host smart-f36dbf66-5902-470f-8381-43ef0491d5dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045982057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1045982057
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1346398479
Short name T386
Test name
Test status
Simulation time 1180484191 ps
CPU time 3.42 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:48:15 PM PDT 24
Peak memory 198760 kb
Host smart-79ac9267-c415-4d70-954e-648087e665ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346398479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1346398479
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3588729996
Short name T169
Test name
Test status
Simulation time 38291543 ps
CPU time 1.17 seconds
Started Jun 28 04:48:22 PM PDT 24
Finished Jun 28 04:48:24 PM PDT 24
Peak memory 196780 kb
Host smart-e194b274-aced-4ece-a26e-0150f3b3195b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588729996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3588729996
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1381054326
Short name T679
Test name
Test status
Simulation time 31093604 ps
CPU time 1.03 seconds
Started Jun 28 04:48:18 PM PDT 24
Finished Jun 28 04:48:20 PM PDT 24
Peak memory 196788 kb
Host smart-28766fb7-737b-4303-aeb5-099c2b7c650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381054326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1381054326
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.775916136
Short name T321
Test name
Test status
Simulation time 32710572 ps
CPU time 1.22 seconds
Started Jun 28 04:48:05 PM PDT 24
Finished Jun 28 04:48:08 PM PDT 24
Peak memory 197496 kb
Host smart-ba4e5962-b941-449c-b08e-6204579fcedf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775916136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.775916136
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3960223908
Short name T276
Test name
Test status
Simulation time 50705316 ps
CPU time 1.3 seconds
Started Jun 28 04:48:33 PM PDT 24
Finished Jun 28 04:48:35 PM PDT 24
Peak memory 198716 kb
Host smart-61d561ce-0f23-4db8-b9ed-4f6bed6f423c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960223908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3960223908
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2842863645
Short name T162
Test name
Test status
Simulation time 35662099 ps
CPU time 0.93 seconds
Started Jun 28 04:48:03 PM PDT 24
Finished Jun 28 04:48:05 PM PDT 24
Peak memory 197708 kb
Host smart-b3422cb5-049a-48f7-8952-e2947b7a9fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842863645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2842863645
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2991919392
Short name T299
Test name
Test status
Simulation time 35358196 ps
CPU time 1.01 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:10 PM PDT 24
Peak memory 196404 kb
Host smart-75684f81-ef62-4918-a2f7-764058f2426e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991919392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2991919392
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2719766199
Short name T331
Test name
Test status
Simulation time 8163784181 ps
CPU time 100.17 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:49:51 PM PDT 24
Peak memory 198824 kb
Host smart-d892a2ce-86c7-4d72-bd55-2d0f0d59a711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719766199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2719766199
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1126112887
Short name T644
Test name
Test status
Simulation time 14663340 ps
CPU time 0.6 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:48:09 PM PDT 24
Peak memory 194780 kb
Host smart-2a74dd3a-b745-4c09-94c7-30b05548fc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126112887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1126112887
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.4223361423
Short name T250
Test name
Test status
Simulation time 102217484 ps
CPU time 0.91 seconds
Started Jun 28 04:48:09 PM PDT 24
Finished Jun 28 04:48:11 PM PDT 24
Peak memory 197236 kb
Host smart-1967811d-cc2f-4899-be05-27184407a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223361423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.4223361423
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1345824390
Short name T615
Test name
Test status
Simulation time 672707416 ps
CPU time 22.77 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:36 PM PDT 24
Peak memory 197552 kb
Host smart-d06f94d4-7024-4e00-8741-cfeee5194d2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345824390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1345824390
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1452423417
Short name T599
Test name
Test status
Simulation time 83534704 ps
CPU time 0.62 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:48:16 PM PDT 24
Peak memory 195224 kb
Host smart-fa1dcc6b-c989-4ce2-8943-18b4a32d386a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452423417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1452423417
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3831328457
Short name T288
Test name
Test status
Simulation time 272998673 ps
CPU time 1.21 seconds
Started Jun 28 04:48:28 PM PDT 24
Finished Jun 28 04:48:29 PM PDT 24
Peak memory 196480 kb
Host smart-73085974-4c24-42a6-9a32-a7323215a399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831328457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3831328457
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2766031227
Short name T625
Test name
Test status
Simulation time 31736769 ps
CPU time 0.92 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 196872 kb
Host smart-f29335a2-f6c9-4532-bcff-a3f69e2f983f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766031227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2766031227
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1361522449
Short name T452
Test name
Test status
Simulation time 508155545 ps
CPU time 3.49 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:48:15 PM PDT 24
Peak memory 196472 kb
Host smart-f2d2a420-5b5e-427a-ae9f-0705e3280288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361522449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1361522449
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2034397385
Short name T518
Test name
Test status
Simulation time 79984125 ps
CPU time 1.01 seconds
Started Jun 28 04:48:26 PM PDT 24
Finished Jun 28 04:48:28 PM PDT 24
Peak memory 197248 kb
Host smart-ce7c8c63-e552-46c9-8115-32d4729d3cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034397385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2034397385
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.232497908
Short name T253
Test name
Test status
Simulation time 61537793 ps
CPU time 0.8 seconds
Started Jun 28 04:48:16 PM PDT 24
Finished Jun 28 04:48:18 PM PDT 24
Peak memory 196148 kb
Host smart-48d28853-44c9-4a8a-ad01-d73dcdf42bc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232497908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.232497908
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1495308684
Short name T70
Test name
Test status
Simulation time 194745077 ps
CPU time 4.35 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:49:42 PM PDT 24
Peak memory 198396 kb
Host smart-ba4eaa72-7902-4efe-acda-ef44f6b19bf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495308684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1495308684
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.160137249
Short name T154
Test name
Test status
Simulation time 236768130 ps
CPU time 1.24 seconds
Started Jun 28 04:48:09 PM PDT 24
Finished Jun 28 04:48:11 PM PDT 24
Peak memory 196248 kb
Host smart-a80b8265-8801-4768-91b9-df8d1f8c3531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160137249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.160137249
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.4075427531
Short name T421
Test name
Test status
Simulation time 32030609 ps
CPU time 0.87 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:10 PM PDT 24
Peak memory 195748 kb
Host smart-7444aa5d-b870-465d-8a27-d083c28f4281
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075427531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.4075427531
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2692875169
Short name T189
Test name
Test status
Simulation time 98414564327 ps
CPU time 66.89 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:49:20 PM PDT 24
Peak memory 198716 kb
Host smart-3eba1440-7fdf-4a9e-93ca-5a5839b5da9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692875169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2692875169
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2045780137
Short name T538
Test name
Test status
Simulation time 88409490092 ps
CPU time 1803.53 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 05:18:25 PM PDT 24
Peak memory 199116 kb
Host smart-69271a97-5f38-4db2-9cb9-cb7e22256eae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2045780137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2045780137
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.445205642
Short name T560
Test name
Test status
Simulation time 16553838 ps
CPU time 0.64 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 194896 kb
Host smart-35c6b3a8-0459-4b7a-93dd-54b1c166302b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445205642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.445205642
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.105050673
Short name T349
Test name
Test status
Simulation time 50277489 ps
CPU time 0.85 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:56 PM PDT 24
Peak memory 196068 kb
Host smart-e8a6a25f-768c-4919-abf0-1e0935a959ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105050673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.105050673
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4084537914
Short name T658
Test name
Test status
Simulation time 965528408 ps
CPU time 17.75 seconds
Started Jun 28 04:46:50 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 198664 kb
Host smart-406c7f80-8eb4-4ed0-9e2f-0cd83c5e4bf2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084537914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4084537914
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3812897597
Short name T628
Test name
Test status
Simulation time 157769212 ps
CPU time 0.76 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 195052 kb
Host smart-80282864-0713-4095-b69d-03c787c50760
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812897597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3812897597
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1135013313
Short name T637
Test name
Test status
Simulation time 276358971 ps
CPU time 1.04 seconds
Started Jun 28 04:46:56 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 196512 kb
Host smart-f3aa0c33-e9aa-44f3-9676-a3fdaa9608bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135013313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1135013313
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1892881275
Short name T537
Test name
Test status
Simulation time 859972759 ps
CPU time 3.27 seconds
Started Jun 28 04:46:47 PM PDT 24
Finished Jun 28 04:46:51 PM PDT 24
Peak memory 197748 kb
Host smart-ac3295c5-84ea-4842-8dc6-65a17f1c510f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892881275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1892881275
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1206132368
Short name T573
Test name
Test status
Simulation time 64533750 ps
CPU time 2.08 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 196512 kb
Host smart-c4b3ea6d-5aca-40bc-b287-afb23b5ac5d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206132368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1206132368
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3919621490
Short name T707
Test name
Test status
Simulation time 24291055 ps
CPU time 0.75 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:46:52 PM PDT 24
Peak memory 194960 kb
Host smart-fc3e8cf2-228d-4aca-bdc2-c66170057e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919621490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3919621490
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2921277021
Short name T594
Test name
Test status
Simulation time 200075867 ps
CPU time 1.04 seconds
Started Jun 28 04:47:01 PM PDT 24
Finished Jun 28 04:47:04 PM PDT 24
Peak memory 197200 kb
Host smart-1d8979e3-6d9e-4bc4-ad73-dcafe66d6967
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921277021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2921277021
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.194485350
Short name T194
Test name
Test status
Simulation time 208931244 ps
CPU time 3.62 seconds
Started Jun 28 04:46:46 PM PDT 24
Finished Jun 28 04:46:51 PM PDT 24
Peak memory 198628 kb
Host smart-9deca797-8909-4b7b-b95e-3040e124ec3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194485350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.194485350
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3867593781
Short name T39
Test name
Test status
Simulation time 809659631 ps
CPU time 0.98 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:57 PM PDT 24
Peak memory 214160 kb
Host smart-afea54b8-8e85-40d5-a1dd-9b351902da0a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867593781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3867593781
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3464310491
Short name T534
Test name
Test status
Simulation time 49503658 ps
CPU time 0.94 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 196244 kb
Host smart-27949883-5abf-4b22-abee-98736d9163a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464310491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3464310491
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.784215825
Short name T597
Test name
Test status
Simulation time 263179624 ps
CPU time 1 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 196308 kb
Host smart-146b0305-9b64-4a03-a5ef-f41d78527e98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784215825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.784215825
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.432132537
Short name T428
Test name
Test status
Simulation time 3699211528 ps
CPU time 48.81 seconds
Started Jun 28 04:46:51 PM PDT 24
Finished Jun 28 04:47:41 PM PDT 24
Peak memory 198848 kb
Host smart-02faacde-94df-4391-9b8e-ef7265a54459
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432132537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.432132537
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.4068360374
Short name T256
Test name
Test status
Simulation time 27676525 ps
CPU time 0.55 seconds
Started Jun 28 04:48:19 PM PDT 24
Finished Jun 28 04:48:20 PM PDT 24
Peak memory 193480 kb
Host smart-adb9697a-efd8-4e5e-8a20-ca32355f321b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068360374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.4068360374
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.4074647768
Short name T563
Test name
Test status
Simulation time 101347506 ps
CPU time 0.62 seconds
Started Jun 28 04:48:14 PM PDT 24
Finished Jun 28 04:48:15 PM PDT 24
Peak memory 194688 kb
Host smart-dc4fc44d-d643-4404-864a-958e871ca9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074647768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.4074647768
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.186526073
Short name T530
Test name
Test status
Simulation time 601470453 ps
CPU time 7.42 seconds
Started Jun 28 04:48:14 PM PDT 24
Finished Jun 28 04:48:22 PM PDT 24
Peak memory 197100 kb
Host smart-83737def-5221-4a6e-a654-2101f69c4e5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186526073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.186526073
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.731323544
Short name T472
Test name
Test status
Simulation time 355274765 ps
CPU time 1.09 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 198588 kb
Host smart-349354d4-77eb-43a3-a9ee-2931473b944f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731323544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.731323544
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3441675906
Short name T111
Test name
Test status
Simulation time 94861745 ps
CPU time 0.99 seconds
Started Jun 28 04:48:27 PM PDT 24
Finished Jun 28 04:48:28 PM PDT 24
Peak memory 196644 kb
Host smart-74f68887-86d7-40f2-87ae-8b226e7226dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441675906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3441675906
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2290950244
Short name T607
Test name
Test status
Simulation time 38789888 ps
CPU time 1.58 seconds
Started Jun 28 04:48:16 PM PDT 24
Finished Jun 28 04:48:18 PM PDT 24
Peak memory 198640 kb
Host smart-1c83d044-32b5-43c5-b073-0541d1e16638
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290950244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2290950244
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.989184176
Short name T207
Test name
Test status
Simulation time 734979530 ps
CPU time 2.93 seconds
Started Jun 28 04:49:34 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 197532 kb
Host smart-4c358a31-5384-41f0-88c9-0eaf0ad7d628
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989184176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
989184176
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3518782914
Short name T163
Test name
Test status
Simulation time 234256853 ps
CPU time 1.32 seconds
Started Jun 28 04:48:24 PM PDT 24
Finished Jun 28 04:48:26 PM PDT 24
Peak memory 197744 kb
Host smart-f061fb79-f31a-4451-80d0-86e4fba6b13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518782914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3518782914
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.436696055
Short name T622
Test name
Test status
Simulation time 28736620 ps
CPU time 0.97 seconds
Started Jun 28 04:48:05 PM PDT 24
Finished Jun 28 04:48:07 PM PDT 24
Peak memory 196584 kb
Host smart-c2d37074-ba99-4516-8f6e-edc6b736875c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436696055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.436696055
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1289816756
Short name T396
Test name
Test status
Simulation time 51715894 ps
CPU time 2.65 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 198624 kb
Host smart-66682a39-8036-4a04-87d7-f8e5231f559b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289816756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1289816756
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3336584871
Short name T503
Test name
Test status
Simulation time 710365942 ps
CPU time 1.23 seconds
Started Jun 28 04:48:07 PM PDT 24
Finished Jun 28 04:48:10 PM PDT 24
Peak memory 197220 kb
Host smart-93c8fcb2-ddc9-4c09-968f-11ebb88f91db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336584871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3336584871
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2421788923
Short name T457
Test name
Test status
Simulation time 21465961 ps
CPU time 0.73 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 196448 kb
Host smart-cf95da6d-1ec3-4b11-8396-c418747662c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421788923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2421788923
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1903115420
Short name T541
Test name
Test status
Simulation time 6607793552 ps
CPU time 46.37 seconds
Started Jun 28 04:49:34 PM PDT 24
Finished Jun 28 04:50:22 PM PDT 24
Peak memory 198544 kb
Host smart-5ed884fa-d55a-4277-aae8-5cc56ba1f14c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903115420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1903115420
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.4040405869
Short name T65
Test name
Test status
Simulation time 49533001142 ps
CPU time 945.01 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 05:03:54 PM PDT 24
Peak memory 198916 kb
Host smart-e3991fd6-d966-4cd5-bbaf-5f211cc6175c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4040405869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.4040405869
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1165460660
Short name T55
Test name
Test status
Simulation time 35247472 ps
CPU time 0.62 seconds
Started Jun 28 04:48:19 PM PDT 24
Finished Jun 28 04:48:20 PM PDT 24
Peak memory 195208 kb
Host smart-42d577b2-50bd-4e0e-a212-662f42e3bcba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165460660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1165460660
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2000334409
Short name T619
Test name
Test status
Simulation time 35949751 ps
CPU time 0.66 seconds
Started Jun 28 04:48:11 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 194844 kb
Host smart-51d27835-4c91-4d94-b957-16c546227854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000334409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2000334409
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1516253855
Short name T381
Test name
Test status
Simulation time 1139840640 ps
CPU time 14.99 seconds
Started Jun 28 04:48:34 PM PDT 24
Finished Jun 28 04:48:50 PM PDT 24
Peak memory 197260 kb
Host smart-c6e71f4b-7b39-4575-806d-3ed6801e9a39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516253855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1516253855
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1331432977
Short name T663
Test name
Test status
Simulation time 38620778 ps
CPU time 0.68 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 194944 kb
Host smart-8768da33-0282-4c88-a2a8-ab8f72554d7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331432977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1331432977
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2194602150
Short name T265
Test name
Test status
Simulation time 71051092 ps
CPU time 1.22 seconds
Started Jun 28 04:48:14 PM PDT 24
Finished Jun 28 04:48:16 PM PDT 24
Peak memory 197372 kb
Host smart-a4d4465f-bcb6-4947-8d41-379f26fdff17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194602150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2194602150
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3417787976
Short name T682
Test name
Test status
Simulation time 47473776 ps
CPU time 1.95 seconds
Started Jun 28 04:48:08 PM PDT 24
Finished Jun 28 04:48:11 PM PDT 24
Peak memory 198604 kb
Host smart-c045daed-7d2c-48f3-9be8-bb4e1bcbb9a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417787976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3417787976
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.198109926
Short name T140
Test name
Test status
Simulation time 80632991 ps
CPU time 1.73 seconds
Started Jun 28 04:48:11 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 197244 kb
Host smart-db18f8a1-d44c-4dc2-bdf6-9ce15a124d93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198109926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
198109926
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2567731362
Short name T302
Test name
Test status
Simulation time 42280715 ps
CPU time 0.95 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 196644 kb
Host smart-803f348a-2213-4df7-91d4-e5feb39c7aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567731362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2567731362
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.319174429
Short name T382
Test name
Test status
Simulation time 65506813 ps
CPU time 1.2 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:48:17 PM PDT 24
Peak memory 197324 kb
Host smart-5f47e73a-400f-4d34-8583-c7f5fe8be5b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319174429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.319174429
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1069958134
Short name T258
Test name
Test status
Simulation time 462103388 ps
CPU time 5.16 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 196900 kb
Host smart-abd64fc5-434f-4ead-b12a-19f712d3f281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069958134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1069958134
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2072403309
Short name T687
Test name
Test status
Simulation time 90644309 ps
CPU time 1.3 seconds
Started Jun 28 04:48:11 PM PDT 24
Finished Jun 28 04:48:14 PM PDT 24
Peak memory 198648 kb
Host smart-d669ddfc-a998-4528-a219-3b3967a9985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072403309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2072403309
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2644258555
Short name T567
Test name
Test status
Simulation time 40526181 ps
CPU time 1.2 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:48:17 PM PDT 24
Peak memory 197292 kb
Host smart-045b9843-3a10-4aae-9534-66768bf3e869
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644258555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2644258555
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1975320951
Short name T598
Test name
Test status
Simulation time 10322208553 ps
CPU time 85.75 seconds
Started Jun 28 04:48:16 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 198704 kb
Host smart-67a24c00-b975-4c85-9a3b-06f6aae04dc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975320951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1975320951
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2297301288
Short name T294
Test name
Test status
Simulation time 12493858 ps
CPU time 0.57 seconds
Started Jun 28 04:48:26 PM PDT 24
Finished Jun 28 04:48:26 PM PDT 24
Peak memory 195252 kb
Host smart-c99da8ba-c386-49fa-ae75-6fc563d7753b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297301288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2297301288
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.804199421
Short name T656
Test name
Test status
Simulation time 50150719 ps
CPU time 0.78 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 196656 kb
Host smart-6a8e1c71-c67e-4f85-abd1-8df370b22cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804199421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.804199421
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1521828649
Short name T26
Test name
Test status
Simulation time 5031083873 ps
CPU time 15.74 seconds
Started Jun 28 04:48:11 PM PDT 24
Finished Jun 28 04:48:28 PM PDT 24
Peak memory 197756 kb
Host smart-e27e2703-f814-4c4d-b82c-2705b50cfa2d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521828649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1521828649
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2811319924
Short name T490
Test name
Test status
Simulation time 29723285 ps
CPU time 0.75 seconds
Started Jun 28 04:48:33 PM PDT 24
Finished Jun 28 04:48:34 PM PDT 24
Peak memory 196184 kb
Host smart-3cf41984-885d-49d4-8d4c-d83d0b437a0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811319924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2811319924
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1303910781
Short name T546
Test name
Test status
Simulation time 95853177 ps
CPU time 1.27 seconds
Started Jun 28 04:48:23 PM PDT 24
Finished Jun 28 04:48:25 PM PDT 24
Peak memory 197704 kb
Host smart-bbb6dea2-d87e-47c1-8327-70ea85233817
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303910781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1303910781
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2490777879
Short name T692
Test name
Test status
Simulation time 64388805 ps
CPU time 2.65 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 196884 kb
Host smart-391000f1-308c-4ef4-a140-2cade9b7fcb5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490777879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2490777879
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.556406327
Short name T608
Test name
Test status
Simulation time 107866194 ps
CPU time 2.5 seconds
Started Jun 28 04:48:18 PM PDT 24
Finished Jun 28 04:48:22 PM PDT 24
Peak memory 197664 kb
Host smart-453205d1-7546-414e-8918-34f53e921074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556406327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
556406327
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.10270176
Short name T499
Test name
Test status
Simulation time 55705177 ps
CPU time 0.79 seconds
Started Jun 28 04:48:18 PM PDT 24
Finished Jun 28 04:48:20 PM PDT 24
Peak memory 196676 kb
Host smart-07cf3dc7-e11f-47f9-aca5-9526111bc202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10270176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.10270176
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3554874271
Short name T393
Test name
Test status
Simulation time 179791960 ps
CPU time 1.03 seconds
Started Jun 28 04:48:14 PM PDT 24
Finished Jun 28 04:48:16 PM PDT 24
Peak memory 196520 kb
Host smart-8af2e354-d751-42d6-b38d-0d5fc86f2a04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554874271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3554874271
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2260313480
Short name T591
Test name
Test status
Simulation time 340372142 ps
CPU time 3.77 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:22 PM PDT 24
Peak memory 198640 kb
Host smart-455f8ff9-2d45-417e-863a-6f6c749463bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260313480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2260313480
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.216311993
Short name T270
Test name
Test status
Simulation time 61779366 ps
CPU time 1.13 seconds
Started Jun 28 04:48:18 PM PDT 24
Finished Jun 28 04:48:20 PM PDT 24
Peak memory 197160 kb
Host smart-5b14a043-3bea-4d21-b515-4b3143ed6f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216311993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.216311993
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.211524464
Short name T677
Test name
Test status
Simulation time 46308415 ps
CPU time 0.75 seconds
Started Jun 28 04:48:33 PM PDT 24
Finished Jun 28 04:48:34 PM PDT 24
Peak memory 195920 kb
Host smart-34ae2f9f-dbd9-4785-96c0-a2c83dba9e03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211524464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.211524464
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.708702791
Short name T406
Test name
Test status
Simulation time 10201362046 ps
CPU time 110.38 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:50:09 PM PDT 24
Peak memory 198748 kb
Host smart-8f5d87a0-0515-4e10-95c4-4dbe5d5cf800
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708702791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.708702791
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3929953651
Short name T695
Test name
Test status
Simulation time 25257342 ps
CPU time 0.58 seconds
Started Jun 28 04:48:16 PM PDT 24
Finished Jun 28 04:48:17 PM PDT 24
Peak memory 194572 kb
Host smart-760012a9-0aed-4579-b14e-12593c08151c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929953651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3929953651
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4005284755
Short name T134
Test name
Test status
Simulation time 36753463 ps
CPU time 0.64 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:48:17 PM PDT 24
Peak memory 194540 kb
Host smart-ca4ca68f-9504-4220-948b-e3c9b055494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005284755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4005284755
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.878811959
Short name T285
Test name
Test status
Simulation time 1239404086 ps
CPU time 16.14 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 04:48:38 PM PDT 24
Peak memory 196196 kb
Host smart-a4913177-599d-43c6-9b1b-39afcbc7c0da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878811959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.878811959
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3267413708
Short name T323
Test name
Test status
Simulation time 35631464 ps
CPU time 0.71 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 195492 kb
Host smart-108ba8bb-6042-45d6-9d2d-349495aa36e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267413708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3267413708
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2052956046
Short name T217
Test name
Test status
Simulation time 341435660 ps
CPU time 1.25 seconds
Started Jun 28 04:48:19 PM PDT 24
Finished Jun 28 04:48:21 PM PDT 24
Peak memory 196388 kb
Host smart-c08a97f6-e398-41e1-a4da-42829c92fc4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052956046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2052956046
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3612933482
Short name T504
Test name
Test status
Simulation time 154152975 ps
CPU time 1.69 seconds
Started Jun 28 04:48:33 PM PDT 24
Finished Jun 28 04:48:35 PM PDT 24
Peak memory 197472 kb
Host smart-28632f38-12cd-4727-9b7c-024019e5b1cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612933482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3612933482
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3729601962
Short name T206
Test name
Test status
Simulation time 127737145 ps
CPU time 2.86 seconds
Started Jun 28 04:48:25 PM PDT 24
Finished Jun 28 04:48:28 PM PDT 24
Peak memory 198768 kb
Host smart-6bc8214a-4e2e-41cd-8d01-99623528e068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729601962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3729601962
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1328869540
Short name T308
Test name
Test status
Simulation time 97589854 ps
CPU time 1.17 seconds
Started Jun 28 04:48:11 PM PDT 24
Finished Jun 28 04:48:13 PM PDT 24
Peak memory 196544 kb
Host smart-dcaf0206-04dc-48f4-b746-6c161b790a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328869540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1328869540
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2739048655
Short name T455
Test name
Test status
Simulation time 45366766 ps
CPU time 0.89 seconds
Started Jun 28 04:48:23 PM PDT 24
Finished Jun 28 04:48:25 PM PDT 24
Peak memory 196412 kb
Host smart-e80766e0-45ec-43cd-a68d-31a7db3226d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739048655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2739048655
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1723468914
Short name T649
Test name
Test status
Simulation time 110153950 ps
CPU time 5.06 seconds
Started Jun 28 04:48:23 PM PDT 24
Finished Jun 28 04:48:29 PM PDT 24
Peak memory 198388 kb
Host smart-55fd53f5-d045-4f65-a4e2-26956aede290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723468914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1723468914
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.795710909
Short name T456
Test name
Test status
Simulation time 135935737 ps
CPU time 1.12 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 04:48:23 PM PDT 24
Peak memory 196112 kb
Host smart-9242b91c-9862-4bbb-abc3-9085e2d272f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795710909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.795710909
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1392288620
Short name T152
Test name
Test status
Simulation time 147791153 ps
CPU time 0.85 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 195832 kb
Host smart-4aad0abc-78aa-4149-b7ca-014e02526072
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392288620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1392288620
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1645169926
Short name T220
Test name
Test status
Simulation time 11695924206 ps
CPU time 80.58 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:49:38 PM PDT 24
Peak memory 198768 kb
Host smart-22b015ae-bbce-4ff0-bafc-da2fdbd0080e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645169926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1645169926
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.806933810
Short name T372
Test name
Test status
Simulation time 15622013 ps
CPU time 0.62 seconds
Started Jun 28 04:48:18 PM PDT 24
Finished Jun 28 04:48:20 PM PDT 24
Peak memory 194756 kb
Host smart-12d71a18-23a5-4a99-9a77-1303a8f18b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806933810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.806933810
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.323131752
Short name T478
Test name
Test status
Simulation time 75085673 ps
CPU time 0.88 seconds
Started Jun 28 04:48:23 PM PDT 24
Finished Jun 28 04:48:25 PM PDT 24
Peak memory 195984 kb
Host smart-c1f98d1f-6b66-4a51-8538-58f386e97e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323131752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.323131752
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3241068175
Short name T574
Test name
Test status
Simulation time 844039354 ps
CPU time 21.87 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 04:48:43 PM PDT 24
Peak memory 197672 kb
Host smart-22aef56c-f26f-4caf-8c9a-b2701e9540f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241068175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3241068175
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.969687185
Short name T523
Test name
Test status
Simulation time 109100125 ps
CPU time 0.7 seconds
Started Jun 28 04:48:16 PM PDT 24
Finished Jun 28 04:48:18 PM PDT 24
Peak memory 195208 kb
Host smart-885ac688-4b1c-49d3-94c6-551ef031cfce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969687185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.969687185
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2795974908
Short name T700
Test name
Test status
Simulation time 91888207 ps
CPU time 1.26 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 04:48:23 PM PDT 24
Peak memory 197048 kb
Host smart-f926dea4-8445-4f68-b1cd-7f5fde020cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795974908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2795974908
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.88925981
Short name T327
Test name
Test status
Simulation time 143616585 ps
CPU time 1.7 seconds
Started Jun 28 04:48:12 PM PDT 24
Finished Jun 28 04:48:15 PM PDT 24
Peak memory 196896 kb
Host smart-98760057-b3ce-43c7-af49-01d9760001ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88925981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.gpio_intr_with_filter_rand_intr_event.88925981
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3624879284
Short name T30
Test name
Test status
Simulation time 117563241 ps
CPU time 2.79 seconds
Started Jun 28 04:48:19 PM PDT 24
Finished Jun 28 04:48:23 PM PDT 24
Peak memory 198620 kb
Host smart-d322bf3d-1711-45ac-a335-532d38d73965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624879284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3624879284
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3949632312
Short name T119
Test name
Test status
Simulation time 49959625 ps
CPU time 1.01 seconds
Started Jun 28 04:48:15 PM PDT 24
Finished Jun 28 04:48:18 PM PDT 24
Peak memory 197572 kb
Host smart-8941f9e4-d8b8-4eb9-acfb-c08c81afe7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949632312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3949632312
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4185126806
Short name T666
Test name
Test status
Simulation time 67500418 ps
CPU time 0.63 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 194836 kb
Host smart-dcd4c5c2-b1f4-466a-8056-11618d6d2a58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185126806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4185126806
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1677396692
Short name T12
Test name
Test status
Simulation time 253701116 ps
CPU time 2.74 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:21 PM PDT 24
Peak memory 198636 kb
Host smart-72cf79ee-b9b9-40b1-a677-ddad21d912ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677396692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1677396692
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3545828962
Short name T587
Test name
Test status
Simulation time 405422137 ps
CPU time 1.21 seconds
Started Jun 28 04:48:18 PM PDT 24
Finished Jun 28 04:48:20 PM PDT 24
Peak memory 197476 kb
Host smart-a8a16938-fba6-4344-9feb-94d037171c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545828962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3545828962
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.728539077
Short name T642
Test name
Test status
Simulation time 42625219 ps
CPU time 0.94 seconds
Started Jun 28 04:48:10 PM PDT 24
Finished Jun 28 04:48:12 PM PDT 24
Peak memory 196156 kb
Host smart-b90cf665-e8e5-4dec-92e0-9f5989b3b87e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728539077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.728539077
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.576088229
Short name T221
Test name
Test status
Simulation time 7946988743 ps
CPU time 193.98 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 04:51:36 PM PDT 24
Peak memory 199028 kb
Host smart-46d48c74-7c2c-4f4c-b996-5e25acb3fc09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576088229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.576088229
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2583615083
Short name T418
Test name
Test status
Simulation time 80289694807 ps
CPU time 473.86 seconds
Started Jun 28 04:48:41 PM PDT 24
Finished Jun 28 04:56:37 PM PDT 24
Peak memory 207004 kb
Host smart-773c44c2-2967-4851-aa03-adfdc57d7b73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2583615083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2583615083
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1202497338
Short name T167
Test name
Test status
Simulation time 13022004 ps
CPU time 0.59 seconds
Started Jun 28 04:48:28 PM PDT 24
Finished Jun 28 04:48:30 PM PDT 24
Peak memory 194580 kb
Host smart-589a110e-c4db-4d30-b3cc-0df16466ca09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202497338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1202497338
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3397923833
Short name T539
Test name
Test status
Simulation time 19233021 ps
CPU time 0.64 seconds
Started Jun 28 04:48:38 PM PDT 24
Finished Jun 28 04:48:39 PM PDT 24
Peak memory 194724 kb
Host smart-a6d4c437-6a06-473f-b3d1-39b4e75e270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397923833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3397923833
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.594642362
Short name T239
Test name
Test status
Simulation time 233886466 ps
CPU time 6.82 seconds
Started Jun 28 04:48:23 PM PDT 24
Finished Jun 28 04:48:31 PM PDT 24
Peak memory 197152 kb
Host smart-1383ac7c-6b2c-46a1-93c2-e457e566d5f7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594642362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.594642362
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3430497732
Short name T593
Test name
Test status
Simulation time 85713859 ps
CPU time 1.06 seconds
Started Jun 28 04:48:20 PM PDT 24
Finished Jun 28 04:48:21 PM PDT 24
Peak memory 198324 kb
Host smart-d719e5e1-7e4f-4fb3-afd0-f3ffe7ef5926
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430497732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3430497732
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4018003400
Short name T693
Test name
Test status
Simulation time 245565625 ps
CPU time 1.24 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 197848 kb
Host smart-6bad1821-b0a6-4133-a988-ae61d0a4ff8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018003400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4018003400
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3325321539
Short name T417
Test name
Test status
Simulation time 300000086 ps
CPU time 0.99 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:34 PM PDT 24
Peak memory 196644 kb
Host smart-a02fbdcf-35f1-4a04-86e5-d5172cb3c153
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325321539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3325321539
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3193711619
Short name T433
Test name
Test status
Simulation time 102625539 ps
CPU time 3.09 seconds
Started Jun 28 04:48:20 PM PDT 24
Finished Jun 28 04:48:24 PM PDT 24
Peak memory 197512 kb
Host smart-03e1e22c-0c12-4850-80ac-2bd1142af7a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193711619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3193711619
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1351872155
Short name T650
Test name
Test status
Simulation time 376288301 ps
CPU time 1.27 seconds
Started Jun 28 04:48:39 PM PDT 24
Finished Jun 28 04:48:41 PM PDT 24
Peak memory 197716 kb
Host smart-7d3bf307-f7f1-4dd1-910d-473689d77fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351872155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1351872155
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1876809178
Short name T60
Test name
Test status
Simulation time 32018864 ps
CPU time 0.79 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:20 PM PDT 24
Peak memory 196880 kb
Host smart-e8f592af-5b6d-44d3-90d4-9c41c1b885c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876809178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1876809178
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4232924252
Short name T227
Test name
Test status
Simulation time 699855279 ps
CPU time 5.57 seconds
Started Jun 28 04:48:43 PM PDT 24
Finished Jun 28 04:48:50 PM PDT 24
Peak memory 198280 kb
Host smart-6b9ff58e-8a3b-471d-8bbf-9bc349854937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232924252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4232924252
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3077765230
Short name T450
Test name
Test status
Simulation time 208899594 ps
CPU time 1.15 seconds
Started Jun 28 04:48:17 PM PDT 24
Finished Jun 28 04:48:19 PM PDT 24
Peak memory 196264 kb
Host smart-8b1a615a-6ce9-46f5-8c0c-e8f1fd7b122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077765230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3077765230
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3603069349
Short name T28
Test name
Test status
Simulation time 46520299 ps
CPU time 0.97 seconds
Started Jun 28 04:49:15 PM PDT 24
Finished Jun 28 04:49:17 PM PDT 24
Peak memory 195608 kb
Host smart-33aa8e07-3808-41c8-a1ea-64d052c526dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603069349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3603069349
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2648282020
Short name T419
Test name
Test status
Simulation time 25808594475 ps
CPU time 161.41 seconds
Started Jun 28 04:48:18 PM PDT 24
Finished Jun 28 04:51:01 PM PDT 24
Peak memory 198752 kb
Host smart-791b94c7-b1fe-478c-8c13-10c11190fb6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648282020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2648282020
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2409333160
Short name T177
Test name
Test status
Simulation time 29434910 ps
CPU time 0.56 seconds
Started Jun 28 04:48:35 PM PDT 24
Finished Jun 28 04:48:36 PM PDT 24
Peak memory 195360 kb
Host smart-922ca2ad-6426-485a-8a6f-a062b18c1a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409333160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2409333160
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2353491119
Short name T578
Test name
Test status
Simulation time 117135375 ps
CPU time 0.91 seconds
Started Jun 28 04:48:22 PM PDT 24
Finished Jun 28 04:48:23 PM PDT 24
Peak memory 197376 kb
Host smart-d3498dee-4fed-4e2f-8605-91d91afe8711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353491119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2353491119
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3862151766
Short name T708
Test name
Test status
Simulation time 381245805 ps
CPU time 20.18 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:53 PM PDT 24
Peak memory 198688 kb
Host smart-af808df7-9ab9-4668-8095-183c9bc15350
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862151766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3862151766
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1627033097
Short name T716
Test name
Test status
Simulation time 58383964 ps
CPU time 0.63 seconds
Started Jun 28 04:48:36 PM PDT 24
Finished Jun 28 04:48:38 PM PDT 24
Peak memory 195800 kb
Host smart-1537ab55-7922-446c-b922-a3aecce0a338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627033097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1627033097
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.657664996
Short name T405
Test name
Test status
Simulation time 25523911 ps
CPU time 0.85 seconds
Started Jun 28 04:48:30 PM PDT 24
Finished Jun 28 04:48:31 PM PDT 24
Peak memory 196228 kb
Host smart-69fbfaac-cc12-4c4d-aa18-424658e3c983
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657664996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.657664996
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1134304732
Short name T130
Test name
Test status
Simulation time 127677760 ps
CPU time 2.33 seconds
Started Jun 28 04:48:43 PM PDT 24
Finished Jun 28 04:48:47 PM PDT 24
Peak memory 198760 kb
Host smart-49962e27-2acc-4f65-bf33-441f8cad0973
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134304732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1134304732
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.670883113
Short name T442
Test name
Test status
Simulation time 433412142 ps
CPU time 1 seconds
Started Jun 28 04:48:25 PM PDT 24
Finished Jun 28 04:48:26 PM PDT 24
Peak memory 196240 kb
Host smart-aac1c0a8-46db-4b9b-aa20-bb3a67875dfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670883113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
670883113
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1323305336
Short name T718
Test name
Test status
Simulation time 70651945 ps
CPU time 0.81 seconds
Started Jun 28 04:48:30 PM PDT 24
Finished Jun 28 04:48:32 PM PDT 24
Peak memory 196944 kb
Host smart-9e24b573-7eb3-424a-92a6-f4cfddebba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323305336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1323305336
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1944790686
Short name T562
Test name
Test status
Simulation time 64319079 ps
CPU time 1.35 seconds
Started Jun 28 04:48:42 PM PDT 24
Finished Jun 28 04:48:45 PM PDT 24
Peak memory 198716 kb
Host smart-f224f719-6c6c-42c9-9da6-d0ab34f54223
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944790686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1944790686
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1310744831
Short name T1
Test name
Test status
Simulation time 381673559 ps
CPU time 1.49 seconds
Started Jun 28 04:48:40 PM PDT 24
Finished Jun 28 04:48:43 PM PDT 24
Peak memory 198444 kb
Host smart-5ff3e7d1-e0f6-4928-a350-656382fc46a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310744831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1310744831
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.745758544
Short name T676
Test name
Test status
Simulation time 210115478 ps
CPU time 1.12 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 04:48:23 PM PDT 24
Peak memory 196468 kb
Host smart-bbaff562-7185-4537-a56a-3f7dcdba8c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745758544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.745758544
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2045889791
Short name T249
Test name
Test status
Simulation time 70760390 ps
CPU time 1.11 seconds
Started Jun 28 04:48:27 PM PDT 24
Finished Jun 28 04:48:29 PM PDT 24
Peak memory 196664 kb
Host smart-23a707f4-ce51-4e67-a2d9-d3f031d208e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045889791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2045889791
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.4188948571
Short name T623
Test name
Test status
Simulation time 13218669162 ps
CPU time 83.29 seconds
Started Jun 28 04:48:20 PM PDT 24
Finished Jun 28 04:49:44 PM PDT 24
Peak memory 198816 kb
Host smart-cee410c6-1c32-4204-b344-e2173f4a6b2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188948571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.4188948571
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3159419380
Short name T626
Test name
Test status
Simulation time 22217785 ps
CPU time 0.6 seconds
Started Jun 28 04:48:37 PM PDT 24
Finished Jun 28 04:48:39 PM PDT 24
Peak memory 195472 kb
Host smart-f0a090c6-5d52-45b1-bc1e-e92c8002e567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159419380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3159419380
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3535649836
Short name T444
Test name
Test status
Simulation time 24728944 ps
CPU time 0.68 seconds
Started Jun 28 04:48:43 PM PDT 24
Finished Jun 28 04:48:45 PM PDT 24
Peak memory 196612 kb
Host smart-e1810422-fa83-40c3-8641-973149c1000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535649836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3535649836
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1754470023
Short name T174
Test name
Test status
Simulation time 942516541 ps
CPU time 28.65 seconds
Started Jun 28 04:48:40 PM PDT 24
Finished Jun 28 04:49:10 PM PDT 24
Peak memory 198664 kb
Host smart-e8c8d5f5-76b2-4286-b0c6-df2e7619df99
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754470023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1754470023
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.4262061383
Short name T616
Test name
Test status
Simulation time 352423978 ps
CPU time 0.72 seconds
Started Jun 28 04:48:37 PM PDT 24
Finished Jun 28 04:48:39 PM PDT 24
Peak memory 195444 kb
Host smart-91832efa-4965-48a7-9f6d-119cc1308047
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262061383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.4262061383
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3606367211
Short name T262
Test name
Test status
Simulation time 37904087 ps
CPU time 0.63 seconds
Started Jun 28 04:48:40 PM PDT 24
Finished Jun 28 04:48:42 PM PDT 24
Peak memory 194980 kb
Host smart-c33816b7-a5c3-403e-acfe-31910ff59bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606367211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3606367211
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1576937839
Short name T229
Test name
Test status
Simulation time 390286848 ps
CPU time 3.51 seconds
Started Jun 28 04:48:41 PM PDT 24
Finished Jun 28 04:48:46 PM PDT 24
Peak memory 198764 kb
Host smart-d0bf5f25-13a2-40bd-ba5c-fe71958bd3b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576937839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1576937839
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3787007632
Short name T18
Test name
Test status
Simulation time 370690336 ps
CPU time 2.18 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:35 PM PDT 24
Peak memory 198008 kb
Host smart-676ad97d-a249-42aa-936e-2fa0af71f075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787007632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3787007632
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.513913527
Short name T198
Test name
Test status
Simulation time 784716560 ps
CPU time 1.23 seconds
Started Jun 28 04:48:21 PM PDT 24
Finished Jun 28 04:48:23 PM PDT 24
Peak memory 198612 kb
Host smart-019407df-13a3-47ac-afdf-34467fe15413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513913527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.513913527
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.641652100
Short name T471
Test name
Test status
Simulation time 65741645 ps
CPU time 0.74 seconds
Started Jun 28 04:48:42 PM PDT 24
Finished Jun 28 04:48:45 PM PDT 24
Peak memory 194992 kb
Host smart-c0f09a0e-60e9-453d-9761-c1709cf903da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641652100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.641652100
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2143856368
Short name T4
Test name
Test status
Simulation time 3102456846 ps
CPU time 4.1 seconds
Started Jun 28 04:48:34 PM PDT 24
Finished Jun 28 04:48:39 PM PDT 24
Peak memory 198644 kb
Host smart-2b816d4e-9d26-4322-bbf2-2041e88cc7e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143856368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2143856368
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.846154861
Short name T257
Test name
Test status
Simulation time 83034801 ps
CPU time 1.19 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:49:38 PM PDT 24
Peak memory 196312 kb
Host smart-daa3c6b1-883b-4201-897e-616aad2e28cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846154861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.846154861
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3627142612
Short name T343
Test name
Test status
Simulation time 25223125 ps
CPU time 0.8 seconds
Started Jun 28 04:48:19 PM PDT 24
Finished Jun 28 04:48:21 PM PDT 24
Peak memory 195792 kb
Host smart-b2c556ce-6bb9-434d-8fad-2da748ba2f41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627142612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3627142612
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1955397765
Short name T5
Test name
Test status
Simulation time 28746700664 ps
CPU time 160.7 seconds
Started Jun 28 04:48:26 PM PDT 24
Finished Jun 28 04:51:07 PM PDT 24
Peak memory 198836 kb
Host smart-e838cff6-aa9d-4938-80ae-9ce4e739202c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955397765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1955397765
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4070613449
Short name T438
Test name
Test status
Simulation time 131139270 ps
CPU time 0.55 seconds
Started Jun 28 04:48:40 PM PDT 24
Finished Jun 28 04:48:41 PM PDT 24
Peak memory 194664 kb
Host smart-886830f2-48cd-4bf6-a4b5-2166a18e2d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070613449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4070613449
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3679967877
Short name T610
Test name
Test status
Simulation time 23390664 ps
CPU time 0.69 seconds
Started Jun 28 04:48:26 PM PDT 24
Finished Jun 28 04:48:28 PM PDT 24
Peak memory 194868 kb
Host smart-c13447a5-2106-4f4f-b64c-b66f055c606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679967877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3679967877
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3254970433
Short name T255
Test name
Test status
Simulation time 732471370 ps
CPU time 23.9 seconds
Started Jun 28 04:48:40 PM PDT 24
Finished Jun 28 04:49:05 PM PDT 24
Peak memory 196232 kb
Host smart-52ad2c9b-def8-483d-81ab-438b0204e8fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254970433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3254970433
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3736002579
Short name T465
Test name
Test status
Simulation time 90352165 ps
CPU time 1.04 seconds
Started Jun 28 04:48:40 PM PDT 24
Finished Jun 28 04:48:42 PM PDT 24
Peak memory 198608 kb
Host smart-be23cf5f-ceb1-4d74-8ed5-e8d2a1e78135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736002579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3736002579
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2619799593
Short name T515
Test name
Test status
Simulation time 138467294 ps
CPU time 1.02 seconds
Started Jun 28 04:48:39 PM PDT 24
Finished Jun 28 04:48:40 PM PDT 24
Peak memory 196488 kb
Host smart-487da5ac-ff4e-4d14-a265-4c3d59498b5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619799593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2619799593
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1064874823
Short name T247
Test name
Test status
Simulation time 254074686 ps
CPU time 2.61 seconds
Started Jun 28 04:48:38 PM PDT 24
Finished Jun 28 04:48:41 PM PDT 24
Peak memory 198740 kb
Host smart-f745a390-0612-4458-b7a9-daada8a5add7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064874823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1064874823
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2417326589
Short name T200
Test name
Test status
Simulation time 142555926 ps
CPU time 1.12 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:34 PM PDT 24
Peak memory 196816 kb
Host smart-428ab9a8-4d87-4494-a4f4-a110c31d3dd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417326589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2417326589
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2652128008
Short name T680
Test name
Test status
Simulation time 108824051 ps
CPU time 1.43 seconds
Started Jun 28 04:48:28 PM PDT 24
Finished Jun 28 04:48:30 PM PDT 24
Peak memory 198652 kb
Host smart-e8276912-6fb7-4a64-a1a5-cec7785c2920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652128008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2652128008
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1047089679
Short name T193
Test name
Test status
Simulation time 80445811 ps
CPU time 1.09 seconds
Started Jun 28 04:48:37 PM PDT 24
Finished Jun 28 04:48:39 PM PDT 24
Peak memory 196508 kb
Host smart-2d23e77e-29fb-417f-b796-51861df6a041
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047089679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1047089679
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.52203550
Short name T6
Test name
Test status
Simulation time 424061353 ps
CPU time 3.26 seconds
Started Jun 28 04:48:41 PM PDT 24
Finished Jun 28 04:48:46 PM PDT 24
Peak memory 198688 kb
Host smart-4260944a-b4fb-4a32-98b1-6c0b6a144e27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52203550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand
om_long_reg_writes_reg_reads.52203550
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2289143165
Short name T132
Test name
Test status
Simulation time 386519651 ps
CPU time 1.1 seconds
Started Jun 28 04:48:43 PM PDT 24
Finished Jun 28 04:48:45 PM PDT 24
Peak memory 196224 kb
Host smart-5ce05aa6-cc4d-47d1-a032-9c74739cc7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289143165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2289143165
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2268140480
Short name T436
Test name
Test status
Simulation time 352238236 ps
CPU time 0.99 seconds
Started Jun 28 04:48:24 PM PDT 24
Finished Jun 28 04:48:25 PM PDT 24
Peak memory 196424 kb
Host smart-da040e21-1624-4c68-8f1b-72fc8d795ac3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268140480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2268140480
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3010481858
Short name T234
Test name
Test status
Simulation time 16913997764 ps
CPU time 75.4 seconds
Started Jun 28 04:48:41 PM PDT 24
Finished Jun 28 04:49:57 PM PDT 24
Peak memory 198700 kb
Host smart-08cd5a55-ceef-4adf-8ef0-89679eb9062e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010481858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3010481858
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2058968246
Short name T564
Test name
Test status
Simulation time 27916568 ps
CPU time 0.56 seconds
Started Jun 28 04:48:24 PM PDT 24
Finished Jun 28 04:48:25 PM PDT 24
Peak memory 195428 kb
Host smart-802d6c54-9df5-4b23-95c9-85aeaab2a48f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058968246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2058968246
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3941519726
Short name T536
Test name
Test status
Simulation time 33853505 ps
CPU time 0.67 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:49:37 PM PDT 24
Peak memory 195652 kb
Host smart-7d2e5cd2-1725-4d79-a694-d9cb4529b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941519726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3941519726
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.229273294
Short name T148
Test name
Test status
Simulation time 540565708 ps
CPU time 12.99 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:46 PM PDT 24
Peak memory 197264 kb
Host smart-c111869f-5760-45ae-8748-22e465508af4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229273294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.229273294
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1643687479
Short name T401
Test name
Test status
Simulation time 323765965 ps
CPU time 0.86 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:34 PM PDT 24
Peak memory 196344 kb
Host smart-ee2e63cc-c0e3-4fbe-b4fa-3afc39937b23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643687479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1643687479
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1287646590
Short name T488
Test name
Test status
Simulation time 70144142 ps
CPU time 0.68 seconds
Started Jun 28 04:48:24 PM PDT 24
Finished Jun 28 04:48:25 PM PDT 24
Peak memory 194796 kb
Host smart-ca47a424-ac4b-4746-a10b-0f2dc1fd480e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287646590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1287646590
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3637505339
Short name T176
Test name
Test status
Simulation time 27413321 ps
CPU time 1.19 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 196900 kb
Host smart-f8dd44af-d4e0-4efc-8b15-74f455b81195
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637505339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3637505339
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4028308966
Short name T375
Test name
Test status
Simulation time 1576044004 ps
CPU time 3.28 seconds
Started Jun 28 04:49:34 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 198460 kb
Host smart-bcb65eb4-68e0-411d-8c04-6c1f09031994
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028308966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4028308966
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3163807909
Short name T379
Test name
Test status
Simulation time 871878405 ps
CPU time 1.29 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:34 PM PDT 24
Peak memory 196340 kb
Host smart-28f9e315-1217-4dcf-9292-92add366750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163807909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3163807909
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2240936895
Short name T407
Test name
Test status
Simulation time 304149781 ps
CPU time 1.14 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:34 PM PDT 24
Peak memory 196700 kb
Host smart-6b3828c9-eec0-4e03-94b1-81fc4d9a23c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240936895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2240936895
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.30095291
Short name T121
Test name
Test status
Simulation time 96704231 ps
CPU time 4.36 seconds
Started Jun 28 04:48:32 PM PDT 24
Finished Jun 28 04:48:37 PM PDT 24
Peak memory 198552 kb
Host smart-991666bc-c416-4b43-b1c1-5ef0d80b7d96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30095291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand
om_long_reg_writes_reg_reads.30095291
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1689735788
Short name T618
Test name
Test status
Simulation time 357070789 ps
CPU time 1.27 seconds
Started Jun 28 04:48:26 PM PDT 24
Finished Jun 28 04:48:28 PM PDT 24
Peak memory 198736 kb
Host smart-9aa6f400-ae35-4f75-a9b7-f16ae9ee7d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689735788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1689735788
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.813657655
Short name T688
Test name
Test status
Simulation time 131389660 ps
CPU time 1.19 seconds
Started Jun 28 04:49:46 PM PDT 24
Finished Jun 28 04:49:48 PM PDT 24
Peak memory 196352 kb
Host smart-d23d9cb0-033f-4385-af25-1033214cb4d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813657655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.813657655
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3636405662
Short name T172
Test name
Test status
Simulation time 2213741054 ps
CPU time 56.63 seconds
Started Jun 28 04:48:27 PM PDT 24
Finished Jun 28 04:49:24 PM PDT 24
Peak memory 198716 kb
Host smart-89e291d4-b691-4a98-ba1d-bbb001e7c832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636405662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3636405662
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.506234227
Short name T632
Test name
Test status
Simulation time 125256340 ps
CPU time 0.64 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:10 PM PDT 24
Peak memory 194904 kb
Host smart-3239b9a8-3e2e-4a37-8d92-e7da5e861da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506234227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.506234227
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1868992644
Short name T422
Test name
Test status
Simulation time 46097289 ps
CPU time 0.9 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 197840 kb
Host smart-2a96c9b1-2bc8-496e-9aef-5343586a6e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868992644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1868992644
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4044616452
Short name T332
Test name
Test status
Simulation time 196127725 ps
CPU time 6.95 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 196892 kb
Host smart-edb2c756-4d10-4247-b58e-0325fbf5cfb5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044616452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4044616452
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2319187013
Short name T489
Test name
Test status
Simulation time 64714305 ps
CPU time 0.93 seconds
Started Jun 28 04:46:59 PM PDT 24
Finished Jun 28 04:47:04 PM PDT 24
Peak memory 198404 kb
Host smart-301aac2f-7217-485d-aa3f-03c8fe524f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319187013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2319187013
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3867480338
Short name T145
Test name
Test status
Simulation time 166196053 ps
CPU time 1.18 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 197004 kb
Host smart-5642c3b9-f338-44d1-928f-d304ef61cf1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867480338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3867480338
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1703417978
Short name T127
Test name
Test status
Simulation time 57761906 ps
CPU time 2.26 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 198696 kb
Host smart-51199912-82d5-454d-8962-2f73f0eeabea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703417978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1703417978
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4264944231
Short name T68
Test name
Test status
Simulation time 110815393 ps
CPU time 2.42 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 197076 kb
Host smart-6917e16f-6e48-4f5c-a9f3-8031670e4444
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264944231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4264944231
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.962588661
Short name T709
Test name
Test status
Simulation time 107958617 ps
CPU time 0.84 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 197228 kb
Host smart-1143ef39-75cd-4456-aeac-c474c8e7bfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962588661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.962588661
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3692867299
Short name T305
Test name
Test status
Simulation time 72811406 ps
CPU time 1.39 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:57 PM PDT 24
Peak memory 197916 kb
Host smart-9ff46f66-61bc-4a4f-8b62-12941dba6a85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692867299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3692867299
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2831209025
Short name T669
Test name
Test status
Simulation time 1451526704 ps
CPU time 4.31 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 198564 kb
Host smart-8b67bc91-9d9c-4849-821b-f5c2b44f9831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831209025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2831209025
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2622274868
Short name T283
Test name
Test status
Simulation time 399167158 ps
CPU time 1.07 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:46:51 PM PDT 24
Peak memory 197196 kb
Host smart-becca711-78ae-4243-9bf8-4cdf766eb35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622274868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2622274868
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2049482134
Short name T25
Test name
Test status
Simulation time 344571586 ps
CPU time 1.54 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 197404 kb
Host smart-0d7b0356-982a-4896-b232-898c5c1109de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049482134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2049482134
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3428456671
Short name T468
Test name
Test status
Simulation time 25884760606 ps
CPU time 178.47 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:50:00 PM PDT 24
Peak memory 198752 kb
Host smart-b73f74fc-6859-4ac8-b137-0bf4ddbbdcd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428456671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3428456671
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1025626909
Short name T556
Test name
Test status
Simulation time 216850317440 ps
CPU time 2291.57 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 05:25:08 PM PDT 24
Peak memory 199116 kb
Host smart-ca79f1c7-253d-4ca5-bcbc-113b14884ac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1025626909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1025626909
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2179355013
Short name T296
Test name
Test status
Simulation time 24477583 ps
CPU time 0.6 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:22 PM PDT 24
Peak memory 194888 kb
Host smart-f3e9202c-46f9-448c-8e62-3e9680ba6c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179355013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2179355013
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2491526216
Short name T664
Test name
Test status
Simulation time 166277996 ps
CPU time 0.85 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 197684 kb
Host smart-a999d950-4dd8-4da2-beb5-8509464f5493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491526216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2491526216
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.500706424
Short name T184
Test name
Test status
Simulation time 1454487827 ps
CPU time 27.42 seconds
Started Jun 28 04:47:06 PM PDT 24
Finished Jun 28 04:47:34 PM PDT 24
Peak memory 198688 kb
Host smart-dd94c321-db75-49e3-8430-c8d9a547c25f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500706424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.500706424
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3806177952
Short name T583
Test name
Test status
Simulation time 160465816 ps
CPU time 0.76 seconds
Started Jun 28 04:47:03 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 196056 kb
Host smart-866b3a51-69a9-4d69-ab96-6d2bdf4090eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806177952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3806177952
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2931969352
Short name T366
Test name
Test status
Simulation time 30739398 ps
CPU time 0.96 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 196804 kb
Host smart-0b212f3f-38ab-4b3d-9a52-be83e948ade5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931969352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2931969352
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1019309614
Short name T143
Test name
Test status
Simulation time 53961007 ps
CPU time 1.27 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:21 PM PDT 24
Peak memory 197040 kb
Host smart-fab1a8e4-979f-4f40-a3db-c13c5bed9908
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019309614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1019309614
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.805826524
Short name T11
Test name
Test status
Simulation time 668865570 ps
CPU time 2.78 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 197188 kb
Host smart-9d0e6056-602f-4b7c-9bfd-21fab22d6e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805826524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.805826524
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.77911365
Short name T261
Test name
Test status
Simulation time 53986777 ps
CPU time 1.12 seconds
Started Jun 28 04:47:05 PM PDT 24
Finished Jun 28 04:47:07 PM PDT 24
Peak memory 196544 kb
Host smart-e8fe5005-5282-4d86-88c8-16380cfc8583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77911365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.77911365
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1317296556
Short name T16
Test name
Test status
Simulation time 363332027 ps
CPU time 0.92 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:15 PM PDT 24
Peak memory 196588 kb
Host smart-7f27cd1c-06b7-4657-bc16-ad8fc9da5177
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317296556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1317296556
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1334433437
Short name T271
Test name
Test status
Simulation time 45494055 ps
CPU time 1.09 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 196912 kb
Host smart-6aeeb390-bf83-453d-9fd0-bd2656a628df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334433437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1334433437
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3626803908
Short name T415
Test name
Test status
Simulation time 104131219 ps
CPU time 1.57 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:12 PM PDT 24
Peak memory 197388 kb
Host smart-7459f49b-9d64-42b3-88a8-bb1a7715c0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626803908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3626803908
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3701402994
Short name T238
Test name
Test status
Simulation time 146628241 ps
CPU time 1.35 seconds
Started Jun 28 04:47:04 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 197520 kb
Host smart-09611c7f-d225-4730-9037-89aa74cbf2b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701402994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3701402994
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3208179928
Short name T681
Test name
Test status
Simulation time 4823228510 ps
CPU time 56.2 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:57 PM PDT 24
Peak memory 198840 kb
Host smart-be77cccf-8776-4285-91a9-733b1aaade8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208179928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3208179928
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2417023442
Short name T267
Test name
Test status
Simulation time 19382078 ps
CPU time 0.58 seconds
Started Jun 28 04:47:19 PM PDT 24
Finished Jun 28 04:47:20 PM PDT 24
Peak memory 195272 kb
Host smart-4039c2ea-966b-4d6a-a358-ec310bda0ccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417023442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2417023442
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3819052348
Short name T341
Test name
Test status
Simulation time 107785616 ps
CPU time 0.8 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 195884 kb
Host smart-4e399365-0416-48ac-8dc0-b0e682a27ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819052348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3819052348
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.624794797
Short name T712
Test name
Test status
Simulation time 91795335 ps
CPU time 4.4 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 196428 kb
Host smart-f24eb0b2-c8a7-4d70-82d9-88c7813baf01
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624794797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.624794797
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.11767290
Short name T113
Test name
Test status
Simulation time 56643636 ps
CPU time 0.92 seconds
Started Jun 28 04:47:08 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 197272 kb
Host smart-cfc02291-ae50-4217-b265-27184433f553
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11767290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.11767290
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1858663103
Short name T641
Test name
Test status
Simulation time 275997617 ps
CPU time 1.27 seconds
Started Jun 28 04:47:13 PM PDT 24
Finished Jun 28 04:47:15 PM PDT 24
Peak memory 197432 kb
Host smart-005d13ac-525e-4fe8-91c5-e6cb6f5f1ca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858663103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1858663103
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.4119429489
Short name T581
Test name
Test status
Simulation time 51762065 ps
CPU time 2.12 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:04 PM PDT 24
Peak memory 196916 kb
Host smart-7fe1df51-96b3-42b8-869e-b17dd0f4ae9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119429489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.4119429489
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.664663376
Short name T435
Test name
Test status
Simulation time 171791861 ps
CPU time 1.36 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 196844 kb
Host smart-d305d963-4724-433e-9b60-3eb79221cd2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664663376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.664663376
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.763485528
Short name T368
Test name
Test status
Simulation time 120943550 ps
CPU time 1.17 seconds
Started Jun 28 04:47:05 PM PDT 24
Finished Jun 28 04:47:07 PM PDT 24
Peak memory 196748 kb
Host smart-8b4b686a-96b5-4478-8f1e-032101bf2009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763485528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.763485528
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2445144422
Short name T118
Test name
Test status
Simulation time 122601711 ps
CPU time 0.92 seconds
Started Jun 28 04:46:59 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 196448 kb
Host smart-73ad9874-5563-406f-8c1d-6c72fd5b49aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445144422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2445144422
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.409162873
Short name T309
Test name
Test status
Simulation time 839269283 ps
CPU time 5.75 seconds
Started Jun 28 04:47:00 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 198572 kb
Host smart-4202f540-ef9e-4608-96cb-61d8b1fb865f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409162873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.409162873
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1646402238
Short name T520
Test name
Test status
Simulation time 197481709 ps
CPU time 1.22 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 196516 kb
Host smart-ffaddb57-0ce8-4ac6-977d-b2ed7a5997c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646402238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1646402238
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2417511954
Short name T303
Test name
Test status
Simulation time 109507852 ps
CPU time 1.13 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 197164 kb
Host smart-5bdf17f4-24dc-46cf-bac6-1805ca708707
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417511954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2417511954
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2249691383
Short name T342
Test name
Test status
Simulation time 51366509563 ps
CPU time 146.21 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:49:34 PM PDT 24
Peak memory 198812 kb
Host smart-fa189cd8-03c6-45a4-9e21-646a5bfba633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249691383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2249691383
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3987835529
Short name T674
Test name
Test status
Simulation time 279092146106 ps
CPU time 1352.37 seconds
Started Jun 28 04:46:59 PM PDT 24
Finished Jun 28 05:09:35 PM PDT 24
Peak memory 198824 kb
Host smart-54319aab-936d-4a15-be48-201d6f88eeb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3987835529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.3987835529
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2162844425
Short name T73
Test name
Test status
Simulation time 22864752 ps
CPU time 0.58 seconds
Started Jun 28 04:47:04 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 195240 kb
Host smart-94de5e2f-af86-4dde-ad84-78da53e69f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162844425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2162844425
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.22295360
Short name T575
Test name
Test status
Simulation time 31843914 ps
CPU time 0.88 seconds
Started Jun 28 04:47:06 PM PDT 24
Finished Jun 28 04:47:08 PM PDT 24
Peak memory 197252 kb
Host smart-b2631bf6-ada5-4e26-835f-95bfa4a9e3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22295360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.22295360
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3830808314
Short name T268
Test name
Test status
Simulation time 374669316 ps
CPU time 10.76 seconds
Started Jun 28 04:46:59 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 198740 kb
Host smart-ba2beb72-bbc7-4a3d-9ace-cab7719f7417
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830808314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3830808314
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3502123999
Short name T201
Test name
Test status
Simulation time 53989351 ps
CPU time 1.44 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 198940 kb
Host smart-593fd5bf-7b4e-4088-90dd-14255c5cc646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502123999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3502123999
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1291781430
Short name T297
Test name
Test status
Simulation time 97861439 ps
CPU time 1.2 seconds
Started Jun 28 04:47:06 PM PDT 24
Finished Jun 28 04:47:07 PM PDT 24
Peak memory 197736 kb
Host smart-84e0fb28-466a-4346-a62e-eb52c725c1db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291781430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1291781430
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3214242778
Short name T647
Test name
Test status
Simulation time 414989417 ps
CPU time 3.51 seconds
Started Jun 28 04:46:58 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 197876 kb
Host smart-06ce1254-2222-49fb-a16b-b7ea8735b53b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214242778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3214242778
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1432175220
Short name T576
Test name
Test status
Simulation time 112695525 ps
CPU time 1.08 seconds
Started Jun 28 04:47:02 PM PDT 24
Finished Jun 28 04:47:04 PM PDT 24
Peak memory 197448 kb
Host smart-8e2efa84-14b5-43b4-9c90-920e7a59475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432175220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1432175220
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1779182607
Short name T347
Test name
Test status
Simulation time 46879349 ps
CPU time 1.1 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 196580 kb
Host smart-9aa7bef4-92a1-4cc4-a5c5-34aa07e18d2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779182607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1779182607
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3343575044
Short name T704
Test name
Test status
Simulation time 463710778 ps
CPU time 2.37 seconds
Started Jun 28 04:47:10 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 198660 kb
Host smart-6142d4b8-806f-4fa2-a2de-bb0ecfc316bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343575044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3343575044
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2358033765
Short name T532
Test name
Test status
Simulation time 138098756 ps
CPU time 0.9 seconds
Started Jun 28 04:47:03 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 195976 kb
Host smart-67c58ed2-f9db-4e0f-909b-499553a04ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358033765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2358033765
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3887350425
Short name T715
Test name
Test status
Simulation time 21888851 ps
CPU time 0.71 seconds
Started Jun 28 04:47:11 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 195800 kb
Host smart-c11099ae-53da-41d1-884f-27eec04e6b6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887350425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3887350425
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2934238481
Short name T409
Test name
Test status
Simulation time 19004298531 ps
CPU time 132.32 seconds
Started Jun 28 04:47:00 PM PDT 24
Finished Jun 28 04:49:15 PM PDT 24
Peak memory 198712 kb
Host smart-9725d260-7550-4fc3-b6dd-b0ad203d1c59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934238481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2934238481
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3599283460
Short name T129
Test name
Test status
Simulation time 10771847 ps
CPU time 0.57 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 194532 kb
Host smart-81a8a743-d4fd-4614-95ca-bda28a24d544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599283460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3599283460
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1208670675
Short name T544
Test name
Test status
Simulation time 63763457 ps
CPU time 0.76 seconds
Started Jun 28 04:47:08 PM PDT 24
Finished Jun 28 04:47:10 PM PDT 24
Peak memory 195908 kb
Host smart-88720df9-5fc0-4c3d-b620-46a374f6b98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208670675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1208670675
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1739081722
Short name T112
Test name
Test status
Simulation time 3272355013 ps
CPU time 27.5 seconds
Started Jun 28 04:47:10 PM PDT 24
Finished Jun 28 04:47:38 PM PDT 24
Peak memory 197528 kb
Host smart-07829c58-8705-4652-a5bc-4eaaf5aebbf6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739081722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1739081722
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.287624681
Short name T458
Test name
Test status
Simulation time 67366823 ps
CPU time 0.71 seconds
Started Jun 28 04:47:12 PM PDT 24
Finished Jun 28 04:47:14 PM PDT 24
Peak memory 195264 kb
Host smart-958e6892-7b25-4bc3-b056-4249ebdd1b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287624681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.287624681
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2988995176
Short name T188
Test name
Test status
Simulation time 96920790 ps
CPU time 1.41 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 198512 kb
Host smart-6c2147f3-d310-4801-83f9-948561e6b651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988995176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2988995176
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1702547226
Short name T402
Test name
Test status
Simulation time 37566560 ps
CPU time 1.44 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:12 PM PDT 24
Peak memory 197388 kb
Host smart-a9f85750-07e7-4335-b373-c41db0ec098c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702547226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1702547226
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.583769342
Short name T579
Test name
Test status
Simulation time 80082182 ps
CPU time 2.42 seconds
Started Jun 28 04:47:07 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 198764 kb
Host smart-d73b11fe-3183-48de-a7c9-17d349cd0f43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583769342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.583769342
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.4159784333
Short name T519
Test name
Test status
Simulation time 50064001 ps
CPU time 1.12 seconds
Started Jun 28 04:47:08 PM PDT 24
Finished Jun 28 04:47:10 PM PDT 24
Peak memory 196696 kb
Host smart-30e44d9d-36c1-4bd6-8506-3c0b16859a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159784333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.4159784333
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.381721297
Short name T281
Test name
Test status
Simulation time 40673736 ps
CPU time 0.76 seconds
Started Jun 28 04:47:03 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 194884 kb
Host smart-2e8e7868-6ce1-47d2-a5d7-c750d9f20250
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381721297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.381721297
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.711986962
Short name T181
Test name
Test status
Simulation time 85054677 ps
CPU time 1.69 seconds
Started Jun 28 04:47:04 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 198520 kb
Host smart-00a04f03-c986-4058-b80c-62bdb26f1b01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711986962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.711986962
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.330079263
Short name T486
Test name
Test status
Simulation time 256578101 ps
CPU time 1.14 seconds
Started Jun 28 04:47:09 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 196392 kb
Host smart-5dc1fd97-af97-47f2-8238-0aa98824f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330079263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.330079263
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2244728696
Short name T699
Test name
Test status
Simulation time 61984160 ps
CPU time 1 seconds
Started Jun 28 04:47:11 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 196152 kb
Host smart-e1446013-ca44-4c96-b11d-29c422023f0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244728696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2244728696
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2034051343
Short name T10
Test name
Test status
Simulation time 51113506154 ps
CPU time 88.27 seconds
Started Jun 28 04:47:12 PM PDT 24
Finished Jun 28 04:48:42 PM PDT 24
Peak memory 198796 kb
Host smart-74c1ef5e-05e3-4539-869b-194f2761a958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034051343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2034051343
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.30478971
Short name T843
Test name
Test status
Simulation time 67408921 ps
CPU time 1.14 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 196920 kb
Host smart-4a4f5ddc-792c-43c1-908c-c81cd6519ecc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=30478971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.30478971
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1491474591
Short name T906
Test name
Test status
Simulation time 269054664 ps
CPU time 1.45 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 198432 kb
Host smart-19bf58e1-285e-4309-a90f-4a14320a8f24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491474591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1491474591
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4047618551
Short name T845
Test name
Test status
Simulation time 28668977 ps
CPU time 0.74 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 195624 kb
Host smart-68d69d7c-50a8-45dd-a2bc-8034cffd0538
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4047618551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4047618551
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.571228465
Short name T907
Test name
Test status
Simulation time 52281518 ps
CPU time 1.14 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 196884 kb
Host smart-9aa80ce5-399a-4a0f-b983-aafb16a5a237
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571228465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.571228465
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1513367413
Short name T915
Test name
Test status
Simulation time 322976545 ps
CPU time 1.35 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 197248 kb
Host smart-c53e772a-0533-4796-835f-0e3e3043ce4a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1513367413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1513367413
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1952117404
Short name T929
Test name
Test status
Simulation time 348679394 ps
CPU time 1.35 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 197300 kb
Host smart-abf45cbf-a7d9-4bfc-8ab4-677b4feb29f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952117404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1952117404
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.847807355
Short name T876
Test name
Test status
Simulation time 59636145 ps
CPU time 1.16 seconds
Started Jun 28 04:44:02 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 196236 kb
Host smart-d622b8c6-13aa-4e35-8f80-6d8d3f65fdc5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=847807355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.847807355
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.624409657
Short name T855
Test name
Test status
Simulation time 127822806 ps
CPU time 1.3 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 197308 kb
Host smart-973b9fb1-1d7e-4595-83c0-fdabdb6f0a78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624409657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.624409657
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2463874088
Short name T914
Test name
Test status
Simulation time 113195350 ps
CPU time 1.01 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 196292 kb
Host smart-b78dd3c2-bfe9-4333-be5d-e99170168a7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2463874088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2463874088
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3375528136
Short name T910
Test name
Test status
Simulation time 45907506 ps
CPU time 1.22 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:02 PM PDT 24
Peak memory 196836 kb
Host smart-f8125728-5952-4071-b4ff-ca1ac090b89e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375528136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3375528136
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.58921203
Short name T937
Test name
Test status
Simulation time 176801967 ps
CPU time 0.82 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:16 PM PDT 24
Peak memory 196536 kb
Host smart-36cd72ab-b130-40a8-bb4e-23d09e21f83c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=58921203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.58921203
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1978319855
Short name T903
Test name
Test status
Simulation time 54912871 ps
CPU time 0.96 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:14 PM PDT 24
Peak memory 197076 kb
Host smart-563f6cd7-9de5-4543-b19e-5a67ffed6e5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978319855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1978319855
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1274757859
Short name T917
Test name
Test status
Simulation time 89271228 ps
CPU time 1.14 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:12 PM PDT 24
Peak memory 196832 kb
Host smart-749ee1e6-6dac-4fac-82a9-8a0b5b080a66
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1274757859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1274757859
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1814586221
Short name T872
Test name
Test status
Simulation time 55909610 ps
CPU time 1.11 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:15 PM PDT 24
Peak memory 196216 kb
Host smart-3078462f-e628-41dc-8345-a14a9f271701
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814586221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1814586221
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1428645111
Short name T866
Test name
Test status
Simulation time 110652669 ps
CPU time 0.76 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:14 PM PDT 24
Peak memory 195800 kb
Host smart-8356d188-7b7f-4f24-b35a-04ab9714bb32
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1428645111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1428645111
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3215742942
Short name T890
Test name
Test status
Simulation time 35740828 ps
CPU time 1.04 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:12 PM PDT 24
Peak memory 196220 kb
Host smart-65649aa7-3e6e-45f3-b574-846fa95d5e41
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215742942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3215742942
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.793392121
Short name T852
Test name
Test status
Simulation time 147160471 ps
CPU time 1.29 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:14 PM PDT 24
Peak memory 197168 kb
Host smart-43a1e8e2-7c08-4458-b78f-a7123edec63d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=793392121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.793392121
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4144225085
Short name T904
Test name
Test status
Simulation time 208009421 ps
CPU time 1.47 seconds
Started Jun 28 04:44:06 PM PDT 24
Finished Jun 28 04:44:08 PM PDT 24
Peak memory 197280 kb
Host smart-f5fc9b58-fa3c-439b-a2eb-48ab63d23396
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144225085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4144225085
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1412918159
Short name T928
Test name
Test status
Simulation time 43764219 ps
CPU time 1.21 seconds
Started Jun 28 04:44:07 PM PDT 24
Finished Jun 28 04:44:10 PM PDT 24
Peak memory 197204 kb
Host smart-33325768-8a1c-44a6-ae44-e9b83a2d7083
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1412918159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1412918159
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1471382239
Short name T901
Test name
Test status
Simulation time 137715139 ps
CPU time 1.25 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 196912 kb
Host smart-4054fdc6-20e5-4331-93d2-27774d33bf89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471382239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1471382239
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3889688738
Short name T850
Test name
Test status
Simulation time 84577240 ps
CPU time 0.94 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 196236 kb
Host smart-b4dde2e2-c4eb-428e-9e6c-39acf50b0345
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3889688738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3889688738
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.139661288
Short name T897
Test name
Test status
Simulation time 112241781 ps
CPU time 0.9 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 196352 kb
Host smart-e60e5459-f6d3-4b44-8480-18387ed1076d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139661288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.139661288
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3791634660
Short name T913
Test name
Test status
Simulation time 108527195 ps
CPU time 1.02 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 196536 kb
Host smart-16a42aa6-71c0-439b-920f-164b5e9a9343
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3791634660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3791634660
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.872507793
Short name T851
Test name
Test status
Simulation time 39822452 ps
CPU time 1.08 seconds
Started Jun 28 04:44:07 PM PDT 24
Finished Jun 28 04:44:09 PM PDT 24
Peak memory 198332 kb
Host smart-b958a432-5946-4359-8139-2eb70be55f4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872507793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.872507793
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2892609367
Short name T895
Test name
Test status
Simulation time 84229009 ps
CPU time 0.94 seconds
Started Jun 28 04:43:56 PM PDT 24
Finished Jun 28 04:43:57 PM PDT 24
Peak memory 195764 kb
Host smart-89cdb8b7-5077-4136-9c89-d1d441efc606
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2892609367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2892609367
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.445040718
Short name T909
Test name
Test status
Simulation time 44085822 ps
CPU time 0.99 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 196944 kb
Host smart-62f0595e-2030-4330-8479-4ce2c52366c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445040718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.445040718
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2909285934
Short name T921
Test name
Test status
Simulation time 80724194 ps
CPU time 0.94 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 195956 kb
Host smart-0c426351-1b34-4d6d-af9a-f0f4fac48b8b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2909285934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2909285934
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3873378725
Short name T883
Test name
Test status
Simulation time 123014501 ps
CPU time 1.32 seconds
Started Jun 28 04:44:07 PM PDT 24
Finished Jun 28 04:44:10 PM PDT 24
Peak memory 196912 kb
Host smart-703bb94d-cc90-4e4c-bfbd-bdaf870cc930
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873378725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3873378725
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2455482763
Short name T938
Test name
Test status
Simulation time 335675242 ps
CPU time 1.49 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:14 PM PDT 24
Peak memory 197232 kb
Host smart-aa348640-3156-489c-8648-06ba3d840a62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2455482763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2455482763
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2551820583
Short name T860
Test name
Test status
Simulation time 204595515 ps
CPU time 1.05 seconds
Started Jun 28 04:44:08 PM PDT 24
Finished Jun 28 04:44:10 PM PDT 24
Peak memory 196896 kb
Host smart-95714e2d-5fa8-45ef-82b4-50f8545c5a96
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551820583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2551820583
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2308244385
Short name T933
Test name
Test status
Simulation time 70329061 ps
CPU time 0.75 seconds
Started Jun 28 04:44:07 PM PDT 24
Finished Jun 28 04:44:09 PM PDT 24
Peak memory 196324 kb
Host smart-882336c0-acea-446e-9230-72ab7ffdcf5a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2308244385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2308244385
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.676543187
Short name T864
Test name
Test status
Simulation time 46396373 ps
CPU time 1.27 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 197196 kb
Host smart-7022803a-5690-492e-bb5a-fee05658bc65
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676543187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.676543187
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1375291304
Short name T863
Test name
Test status
Simulation time 159353638 ps
CPU time 0.83 seconds
Started Jun 28 04:44:08 PM PDT 24
Finished Jun 28 04:44:10 PM PDT 24
Peak memory 195736 kb
Host smart-f8f2dca3-0e94-4976-b89b-84c056356129
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1375291304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1375291304
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3520876940
Short name T849
Test name
Test status
Simulation time 33613745 ps
CPU time 0.85 seconds
Started Jun 28 04:44:06 PM PDT 24
Finished Jun 28 04:44:08 PM PDT 24
Peak memory 196960 kb
Host smart-939f18b8-cc1d-483a-b0f7-b2276eec4b40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520876940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3520876940
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3974519970
Short name T931
Test name
Test status
Simulation time 55824853 ps
CPU time 1.19 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:11 PM PDT 24
Peak memory 196892 kb
Host smart-40fb0577-d0d1-4672-a8ee-f1b2b81e910d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3974519970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3974519970
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1013761983
Short name T853
Test name
Test status
Simulation time 33829079 ps
CPU time 0.93 seconds
Started Jun 28 04:44:07 PM PDT 24
Finished Jun 28 04:44:08 PM PDT 24
Peak memory 196836 kb
Host smart-b5c9821f-af67-432b-a8a6-29261f514efd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013761983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1013761983
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1747078294
Short name T919
Test name
Test status
Simulation time 84779309 ps
CPU time 1.43 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:16 PM PDT 24
Peak memory 197104 kb
Host smart-f9e3253a-cb76-4000-b809-9fa2e09d9ea4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1747078294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1747078294
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3711585756
Short name T880
Test name
Test status
Simulation time 316092390 ps
CPU time 1.54 seconds
Started Jun 28 04:44:08 PM PDT 24
Finished Jun 28 04:44:11 PM PDT 24
Peak memory 197712 kb
Host smart-2cb50811-695a-4ee7-833d-489fe668516b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711585756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3711585756
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.248435550
Short name T922
Test name
Test status
Simulation time 184394013 ps
CPU time 1.21 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 197212 kb
Host smart-8c3f5d9a-9c43-4c2d-a69d-a6786a2b1f0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=248435550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.248435550
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1078281850
Short name T891
Test name
Test status
Simulation time 49939651 ps
CPU time 1.02 seconds
Started Jun 28 04:44:08 PM PDT 24
Finished Jun 28 04:44:10 PM PDT 24
Peak memory 197016 kb
Host smart-50ac9c32-17c2-4975-9a34-bd6b55d7b7f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078281850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1078281850
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.80509415
Short name T871
Test name
Test status
Simulation time 140875203 ps
CPU time 0.89 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:17 PM PDT 24
Peak memory 195660 kb
Host smart-7811a26c-34e9-49cb-b818-a29bb67b8fb4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=80509415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.80509415
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4182837851
Short name T899
Test name
Test status
Simulation time 104458924 ps
CPU time 0.97 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 196880 kb
Host smart-116e7b47-119e-45f2-bf9a-2dd6bd49e0da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182837851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4182837851
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.21938493
Short name T882
Test name
Test status
Simulation time 386974639 ps
CPU time 1.5 seconds
Started Jun 28 04:44:14 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 197188 kb
Host smart-e051a4a2-00d5-4ee3-bbe2-9b40775194ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=21938493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.21938493
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1502667588
Short name T889
Test name
Test status
Simulation time 32341235 ps
CPU time 0.94 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:16 PM PDT 24
Peak memory 196276 kb
Host smart-9101af5a-84a2-40e0-aa76-8def510258b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502667588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1502667588
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1621668375
Short name T902
Test name
Test status
Simulation time 31453541 ps
CPU time 1.02 seconds
Started Jun 28 04:44:08 PM PDT 24
Finished Jun 28 04:44:11 PM PDT 24
Peak memory 196928 kb
Host smart-23d53118-068f-4595-8482-f95e26898818
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1621668375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1621668375
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2044172695
Short name T847
Test name
Test status
Simulation time 29869056 ps
CPU time 0.85 seconds
Started Jun 28 04:44:08 PM PDT 24
Finished Jun 28 04:44:10 PM PDT 24
Peak memory 195740 kb
Host smart-4c81fc85-858d-4b81-afe9-075822c044dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044172695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2044172695
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3701764480
Short name T885
Test name
Test status
Simulation time 659639850 ps
CPU time 1.33 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 192060 kb
Host smart-4686ce25-3759-455e-b0fa-d82be8ab4d8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3701764480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3701764480
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.858947607
Short name T856
Test name
Test status
Simulation time 178478509 ps
CPU time 1.06 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 197780 kb
Host smart-e28d5be5-f824-4b3c-857d-36f12cdbc308
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858947607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.858947607
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2640788788
Short name T869
Test name
Test status
Simulation time 103090376 ps
CPU time 1.1 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 196916 kb
Host smart-903c3f2f-3b56-4dd1-ae23-d93d73bc1227
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2640788788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2640788788
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.642191987
Short name T873
Test name
Test status
Simulation time 39119230 ps
CPU time 0.9 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:16 PM PDT 24
Peak memory 198148 kb
Host smart-6b07f9b3-cb3c-4f91-b788-c1ca96ffb865
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642191987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.642191987
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.372234926
Short name T927
Test name
Test status
Simulation time 177135462 ps
CPU time 1.36 seconds
Started Jun 28 04:44:08 PM PDT 24
Finished Jun 28 04:44:10 PM PDT 24
Peak memory 198436 kb
Host smart-012c8d31-f81d-4b32-bcc9-5dd567a837b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=372234926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.372234926
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1840595614
Short name T854
Test name
Test status
Simulation time 104868923 ps
CPU time 1.09 seconds
Started Jun 28 04:44:07 PM PDT 24
Finished Jun 28 04:44:09 PM PDT 24
Peak memory 196932 kb
Host smart-dbf6b62e-9801-4545-aa4f-540dabed5602
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840595614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1840595614
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.110973426
Short name T886
Test name
Test status
Simulation time 53455815 ps
CPU time 1.02 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:14 PM PDT 24
Peak memory 196908 kb
Host smart-e1460e98-2329-46d2-a5ee-4245fb7f33af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=110973426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.110973426
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1756429340
Short name T844
Test name
Test status
Simulation time 320801679 ps
CPU time 1.43 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 197140 kb
Host smart-c98acc1f-eef3-49f3-85ee-9861136c34d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756429340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1756429340
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2628316816
Short name T858
Test name
Test status
Simulation time 176407235 ps
CPU time 0.92 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:15 PM PDT 24
Peak memory 195484 kb
Host smart-ce4d5d42-8995-43f5-9b83-d1e3a21a0d1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2628316816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2628316816
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1330014482
Short name T842
Test name
Test status
Simulation time 470372235 ps
CPU time 1 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:15 PM PDT 24
Peak memory 196068 kb
Host smart-29bfc6fa-69ee-4f55-a922-581c6e63925a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330014482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1330014482
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1411505078
Short name T920
Test name
Test status
Simulation time 149866072 ps
CPU time 1.33 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 198404 kb
Host smart-ca6b3bda-d23f-49cf-99a7-43b6539bc64c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1411505078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1411505078
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.852375245
Short name T870
Test name
Test status
Simulation time 202575980 ps
CPU time 1.26 seconds
Started Jun 28 04:44:06 PM PDT 24
Finished Jun 28 04:44:08 PM PDT 24
Peak memory 197112 kb
Host smart-fb2dbe0f-a13f-40e6-9c5a-bc1864d5bfee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852375245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.852375245
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.118903374
Short name T881
Test name
Test status
Simulation time 57364502 ps
CPU time 1.07 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 196196 kb
Host smart-72eacead-68ea-4e38-98f7-3f1862238ee1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=118903374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.118903374
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.351902943
Short name T841
Test name
Test status
Simulation time 78081761 ps
CPU time 1.15 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 198328 kb
Host smart-52334261-6c0f-4f29-8859-6d144a83c59c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351902943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.351902943
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3409314800
Short name T875
Test name
Test status
Simulation time 148483507 ps
CPU time 1.17 seconds
Started Jun 28 04:44:14 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 198348 kb
Host smart-df21512f-af60-4285-9e37-23de744c97fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3409314800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3409314800
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3328979141
Short name T867
Test name
Test status
Simulation time 27591286 ps
CPU time 0.85 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:15 PM PDT 24
Peak memory 196904 kb
Host smart-7dfab192-e59e-4e86-b885-6daa9129546d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328979141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3328979141
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.332008542
Short name T888
Test name
Test status
Simulation time 127677549 ps
CPU time 0.82 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 196488 kb
Host smart-a69a53e2-f398-4b7c-b3b9-63eb84d58ecb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=332008542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.332008542
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1633413326
Short name T932
Test name
Test status
Simulation time 69889806 ps
CPU time 1.17 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 196976 kb
Host smart-dc48897d-fb89-4430-8953-f6f580c8db7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633413326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1633413326
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.662899079
Short name T887
Test name
Test status
Simulation time 80894649 ps
CPU time 1.01 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 196804 kb
Host smart-aefdda89-7958-41d8-83c7-c46fd68ac8f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=662899079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.662899079
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.699529747
Short name T865
Test name
Test status
Simulation time 35609594 ps
CPU time 1.15 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 196884 kb
Host smart-8403ad1e-33b7-4814-8378-842e52c6d9db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699529747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.699529747
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.780032837
Short name T859
Test name
Test status
Simulation time 96409848 ps
CPU time 1.07 seconds
Started Jun 28 04:44:08 PM PDT 24
Finished Jun 28 04:44:11 PM PDT 24
Peak memory 197128 kb
Host smart-8bd41817-925d-4f2f-a34a-0958775ac632
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=780032837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.780032837
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1471884621
Short name T893
Test name
Test status
Simulation time 83176089 ps
CPU time 1.3 seconds
Started Jun 28 04:44:14 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 197360 kb
Host smart-bca83cd4-db3e-4c7c-8c50-6c01e5688dce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471884621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1471884621
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1042608922
Short name T916
Test name
Test status
Simulation time 38372876 ps
CPU time 1.21 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 196180 kb
Host smart-2414bf38-3eac-4d56-8901-076e37f3cd0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1042608922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1042608922
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2608615439
Short name T905
Test name
Test status
Simulation time 57424535 ps
CPU time 0.95 seconds
Started Jun 28 04:43:58 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 196964 kb
Host smart-db60ff20-eab4-4f86-a112-edf3ac85e488
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608615439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2608615439
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2991802109
Short name T868
Test name
Test status
Simulation time 57078394 ps
CPU time 1.07 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:17 PM PDT 24
Peak memory 198376 kb
Host smart-4a0cbe14-0fff-45a2-80eb-04d51e24c5b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2991802109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2991802109
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1301446979
Short name T918
Test name
Test status
Simulation time 243985472 ps
CPU time 1.01 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 196892 kb
Host smart-50a6b437-8daf-4799-a851-5d4c778e40f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301446979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1301446979
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4041552314
Short name T925
Test name
Test status
Simulation time 52127491 ps
CPU time 1.48 seconds
Started Jun 28 04:44:14 PM PDT 24
Finished Jun 28 04:44:20 PM PDT 24
Peak memory 198388 kb
Host smart-1877bddb-358f-4294-989d-2503206fc601
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4041552314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4041552314
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.6631798
Short name T936
Test name
Test status
Simulation time 43907742 ps
CPU time 0.91 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 196500 kb
Host smart-3ae94b4f-79d6-4617-af2f-0e1233a22595
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6631798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.6631798
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4047372858
Short name T839
Test name
Test status
Simulation time 83153319 ps
CPU time 1.38 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:16 PM PDT 24
Peak memory 197120 kb
Host smart-4b9afe40-543a-4c42-a63d-f5bad0173513
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4047372858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4047372858
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2925306188
Short name T840
Test name
Test status
Simulation time 177053094 ps
CPU time 1.09 seconds
Started Jun 28 04:44:09 PM PDT 24
Finished Jun 28 04:44:13 PM PDT 24
Peak memory 196892 kb
Host smart-dbff457b-572b-4034-b6e8-83c3301a5f29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925306188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2925306188
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1134087144
Short name T894
Test name
Test status
Simulation time 54853658 ps
CPU time 1.32 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 196884 kb
Host smart-843d580b-9c68-4e82-81ba-67731b327a1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1134087144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1134087144
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623168438
Short name T861
Test name
Test status
Simulation time 57759429 ps
CPU time 1.11 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 196776 kb
Host smart-0a000037-0a3f-4f9f-9895-c596d821abb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623168438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.623168438
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3953406831
Short name T878
Test name
Test status
Simulation time 181326483 ps
CPU time 1.05 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:17 PM PDT 24
Peak memory 196964 kb
Host smart-6f4c3814-5519-4322-88f2-bd685e550284
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3953406831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3953406831
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4273514079
Short name T884
Test name
Test status
Simulation time 274470433 ps
CPU time 1.36 seconds
Started Jun 28 04:44:14 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 197252 kb
Host smart-d182db12-ef54-4aaa-a3d9-f21eada877e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273514079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4273514079
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3810589729
Short name T892
Test name
Test status
Simulation time 30127064 ps
CPU time 0.74 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:14 PM PDT 24
Peak memory 194632 kb
Host smart-89ef63f5-36ba-4c48-8c37-195a1dcf0e3e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3810589729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3810589729
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.637717057
Short name T874
Test name
Test status
Simulation time 42215833 ps
CPU time 1.15 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:16 PM PDT 24
Peak memory 197032 kb
Host smart-5a5f0c44-a272-45a6-9f7c-557cd89465a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637717057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.637717057
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.119015167
Short name T848
Test name
Test status
Simulation time 80259527 ps
CPU time 0.97 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:14 PM PDT 24
Peak memory 197200 kb
Host smart-823d93e7-ca3b-4750-8ea5-ee21cf26662e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=119015167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.119015167
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2377580769
Short name T846
Test name
Test status
Simulation time 45026784 ps
CPU time 1.12 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:14 PM PDT 24
Peak memory 197184 kb
Host smart-d0a413d9-ca8a-4313-a6b7-9aafefb20a25
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377580769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2377580769
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4238071409
Short name T898
Test name
Test status
Simulation time 155648720 ps
CPU time 1.32 seconds
Started Jun 28 04:44:14 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 197280 kb
Host smart-7e1f9341-b5c2-4abf-8be5-5d2542dbf785
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4238071409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4238071409
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3761755149
Short name T923
Test name
Test status
Simulation time 254328136 ps
CPU time 1.25 seconds
Started Jun 28 04:44:14 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 196868 kb
Host smart-27b541ae-9788-4e15-94ae-4b6a93646a77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761755149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3761755149
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3968990731
Short name T877
Test name
Test status
Simulation time 137818863 ps
CPU time 1.4 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 198684 kb
Host smart-0d11b97e-a067-4a5a-a36b-c6fa782fa503
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3968990731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3968990731
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1975095330
Short name T908
Test name
Test status
Simulation time 185220582 ps
CPU time 1.34 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:16 PM PDT 24
Peak memory 197292 kb
Host smart-02b56a72-3505-40fc-8681-4d135c6b7f59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975095330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1975095330
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.274596907
Short name T857
Test name
Test status
Simulation time 130710052 ps
CPU time 1.11 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 196496 kb
Host smart-f8dbc310-c206-4565-9b90-4bb837f52fa0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=274596907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.274596907
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1076303833
Short name T912
Test name
Test status
Simulation time 123268205 ps
CPU time 1.45 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 197680 kb
Host smart-a10050fc-a205-4b8a-ab52-6a7d74a621be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076303833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1076303833
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.408079110
Short name T911
Test name
Test status
Simulation time 37536117 ps
CPU time 1.03 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 197012 kb
Host smart-74ec307a-d415-4558-b4c1-9399bdf778e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=408079110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.408079110
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2738770270
Short name T900
Test name
Test status
Simulation time 118930767 ps
CPU time 0.83 seconds
Started Jun 28 04:44:02 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 195732 kb
Host smart-3c7e0c08-7828-445a-b8bc-2ee9654effec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738770270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2738770270
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3317389320
Short name T879
Test name
Test status
Simulation time 187771725 ps
CPU time 1.39 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 198444 kb
Host smart-c3b3da93-a5f2-4139-85d1-c4a574f53cc9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3317389320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3317389320
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.402114667
Short name T926
Test name
Test status
Simulation time 65213582 ps
CPU time 1.11 seconds
Started Jun 28 04:43:59 PM PDT 24
Finished Jun 28 04:44:02 PM PDT 24
Peak memory 197080 kb
Host smart-9818722d-f677-4431-afcd-fa46489ff63c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402114667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.402114667
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2601208578
Short name T896
Test name
Test status
Simulation time 111230874 ps
CPU time 1.27 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 197088 kb
Host smart-6756a317-0c05-45da-bf46-9f7ed77273d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2601208578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2601208578
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.235406625
Short name T935
Test name
Test status
Simulation time 145028785 ps
CPU time 1.25 seconds
Started Jun 28 04:44:05 PM PDT 24
Finished Jun 28 04:44:07 PM PDT 24
Peak memory 197188 kb
Host smart-a1d9e15c-132d-444f-a459-6d760e7622d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235406625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.235406625
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.780279748
Short name T862
Test name
Test status
Simulation time 50816658 ps
CPU time 0.98 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 196892 kb
Host smart-c37d2f4b-12cc-415e-8618-ab7f5ac04088
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=780279748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.780279748
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1822919931
Short name T934
Test name
Test status
Simulation time 248055581 ps
CPU time 1.16 seconds
Started Jun 28 04:44:01 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 198404 kb
Host smart-4391fb7c-c90a-4325-94e7-2da2ab5e51d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822919931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1822919931
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3764778756
Short name T924
Test name
Test status
Simulation time 36696696 ps
CPU time 1.2 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 197992 kb
Host smart-dadc68f8-627e-4ec0-956c-f9312fbcd7a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3764778756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3764778756
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.273406135
Short name T930
Test name
Test status
Simulation time 84835448 ps
CPU time 1.31 seconds
Started Jun 28 04:44:00 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 196932 kb
Host smart-c797ca97-82b5-465a-9d8c-f86da38d9346
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273406135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.273406135
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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