Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3641475	1			T35	190		T36	1		T37	1
all_pins[1]	3641475	1			T35	190		T36	1		T37	1
all_pins[2]	3641475	1			T35	190		T36	1		T37	1
all_pins[3]	3641475	1			T35	190		T36	1		T37	1
all_pins[4]	3641475	1			T35	190		T36	1		T37	1
all_pins[5]	3641475	1			T35	190		T36	1		T37	1
all_pins[6]	3641475	1			T35	190		T36	1		T37	1
all_pins[7]	3641475	1			T35	190		T36	1		T37	1
all_pins[8]	3641475	1			T35	190		T36	1		T37	1
all_pins[9]	3641475	1			T35	190		T36	1		T37	1
all_pins[10]	3641475	1			T35	190		T36	1		T37	1
all_pins[11]	3641475	1			T35	190		T36	1		T37	1
all_pins[12]	3641475	1			T35	190		T36	1		T37	1
all_pins[13]	3641475	1			T35	190		T36	1		T37	1
all_pins[14]	3641475	1			T35	190		T36	1		T37	1
all_pins[15]	3641475	1			T35	190		T36	1		T37	1
all_pins[16]	3641475	1			T35	190		T36	1		T37	1
all_pins[17]	3641475	1			T35	190		T36	1		T37	1
all_pins[18]	3641475	1			T35	190		T36	1		T37	1
all_pins[19]	3641475	1			T35	190		T36	1		T37	1
all_pins[20]	3641475	1			T35	190		T36	1		T37	1
all_pins[21]	3641475	1			T35	190		T36	1		T37	1
all_pins[22]	3641475	1			T35	190		T36	1		T37	1
all_pins[23]	3641475	1			T35	190		T36	1		T37	1
all_pins[24]	3641475	1			T35	190		T36	1		T37	1
all_pins[25]	3641475	1			T35	190		T36	1		T37	1
all_pins[26]	3641475	1			T35	190		T36	1		T37	1
all_pins[27]	3641475	1			T35	190		T36	1		T37	1
all_pins[28]	3641475	1			T35	190		T36	1		T37	1
all_pins[29]	3641475	1			T35	190		T36	1		T37	1
all_pins[30]	3641475	1			T35	190		T36	1		T37	1
all_pins[31]	3641475	1			T35	190		T36	1		T37	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	72391078	1			T35	3867		T36	32		T37	32
values[0x1]	44136122	1			T35	2213		T38	9301		T39	859838
transitions[0x0=>0x1]	26452833	1			T35	1371		T38	5482		T39	516914
transitions[0x1=>0x0]	26452678	1			T35	1371		T38	5481		T39	516914

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2261705	1			T35	133		T36	1		T37	1
all_pins[0]	values[0x1]	1379770	1			T35	57		T38	295		T39	27108
all_pins[0]	transitions[0x0=>0x1]	856735	1			T35	26		T38	195		T39	17133
all_pins[0]	transitions[0x1=>0x0]	852815	1			T35	66		T38	167		T39	16614
all_pins[1]	values[0x0]	2262453	1			T35	132		T36	1		T37	1
all_pins[1]	values[0x1]	1379022	1			T35	58		T38	355		T39	26618
all_pins[1]	transitions[0x0=>0x1]	826776	1			T35	51		T38	223		T39	15857
all_pins[1]	transitions[0x1=>0x0]	827524	1			T35	50		T38	163		T39	16347
all_pins[2]	values[0x0]	2262755	1			T35	142		T36	1		T37	1
all_pins[2]	values[0x1]	1378720	1			T35	48		T38	346		T39	27034
all_pins[2]	transitions[0x0=>0x1]	825898	1			T35	34		T38	169		T39	16427
all_pins[2]	transitions[0x1=>0x0]	826200	1			T35	44		T38	178		T39	16011
all_pins[3]	values[0x0]	2259728	1			T35	140		T36	1		T37	1
all_pins[3]	values[0x1]	1381747	1			T35	50		T38	313		T39	26211
all_pins[3]	transitions[0x0=>0x1]	827499	1			T35	29		T38	145		T39	15543
all_pins[3]	transitions[0x1=>0x0]	824472	1			T35	27		T38	178		T39	16366
all_pins[4]	values[0x0]	2261706	1			T35	115		T36	1		T37	1
all_pins[4]	values[0x1]	1379769	1			T35	75		T38	269		T39	27167
all_pins[4]	transitions[0x0=>0x1]	825336	1			T35	50		T38	164		T39	16888
all_pins[4]	transitions[0x1=>0x0]	827314	1			T35	25		T38	208		T39	15932
all_pins[5]	values[0x0]	2255118	1			T35	122		T36	1		T37	1
all_pins[5]	values[0x1]	1386357	1			T35	68		T38	271		T39	27547
all_pins[5]	transitions[0x0=>0x1]	828772	1			T35	42		T38	195		T39	16601
all_pins[5]	transitions[0x1=>0x0]	822184	1			T35	49		T38	193		T39	16221
all_pins[6]	values[0x0]	2262007	1			T35	101		T36	1		T37	1
all_pins[6]	values[0x1]	1379468	1			T35	89		T38	311		T39	26306
all_pins[6]	transitions[0x0=>0x1]	824208	1			T35	67		T38	194		T39	15578
all_pins[6]	transitions[0x1=>0x0]	831097	1			T35	46		T38	154		T39	16819
all_pins[7]	values[0x0]	2264782	1			T35	144		T36	1		T37	1
all_pins[7]	values[0x1]	1376693	1			T35	46		T38	209		T39	27482
all_pins[7]	transitions[0x0=>0x1]	824107	1			T35	17		T38	127		T39	16954
all_pins[7]	transitions[0x1=>0x0]	826882	1			T35	60		T38	229		T39	15778
all_pins[8]	values[0x0]	2265834	1			T35	106		T36	1		T37	1
all_pins[8]	values[0x1]	1375641	1			T35	84		T38	267		T39	26994
all_pins[8]	transitions[0x0=>0x1]	826523	1			T35	67		T38	177		T39	15884
all_pins[8]	transitions[0x1=>0x0]	827575	1			T35	29		T38	119		T39	16372
all_pins[9]	values[0x0]	2256099	1			T35	115		T36	1		T37	1
all_pins[9]	values[0x1]	1385376	1			T35	75		T38	241		T39	27431
all_pins[9]	transitions[0x0=>0x1]	831035	1			T35	39		T38	135		T39	16486
all_pins[9]	transitions[0x1=>0x0]	821300	1			T35	48		T38	161		T39	16049
all_pins[10]	values[0x0]	2259729	1			T35	109		T36	1		T37	1
all_pins[10]	values[0x1]	1381746	1			T35	81		T38	319		T39	26672
all_pins[10]	transitions[0x0=>0x1]	823122	1			T35	55		T38	215		T39	15673
all_pins[10]	transitions[0x1=>0x0]	826752	1			T35	49		T38	137		T39	16432
all_pins[11]	values[0x0]	2266399	1			T35	101		T36	1		T37	1
all_pins[11]	values[0x1]	1375076	1			T35	89		T38	294		T39	26413
all_pins[11]	transitions[0x0=>0x1]	819520	1			T35	57		T38	171		T39	16074
all_pins[11]	transitions[0x1=>0x0]	826190	1			T35	49		T38	196		T39	16333
all_pins[12]	values[0x0]	2260516	1			T35	116		T36	1		T37	1
all_pins[12]	values[0x1]	1380959	1			T35	74		T38	281		T39	27088
all_pins[12]	transitions[0x0=>0x1]	825986	1			T35	38		T38	148		T39	16558
all_pins[12]	transitions[0x1=>0x0]	820103	1			T35	53		T38	161		T39	15883
all_pins[13]	values[0x0]	2258865	1			T35	139		T36	1		T37	1
all_pins[13]	values[0x1]	1382610	1			T35	51		T38	277		T39	27662
all_pins[13]	transitions[0x0=>0x1]	824802	1			T35	27		T38	158		T39	16302
all_pins[13]	transitions[0x1=>0x0]	823151	1			T35	50		T38	162		T39	15728
all_pins[14]	values[0x0]	2260502	1			T35	120		T36	1		T37	1
all_pins[14]	values[0x1]	1380973	1			T35	70		T38	307		T39	26547
all_pins[14]	transitions[0x0=>0x1]	826298	1			T35	56		T38	220		T39	15421
all_pins[14]	transitions[0x1=>0x0]	827935	1			T35	37		T38	190		T39	16536
all_pins[15]	values[0x0]	2261401	1			T35	122		T36	1		T37	1
all_pins[15]	values[0x1]	1380074	1			T35	68		T38	313		T39	26924
all_pins[15]	transitions[0x0=>0x1]	824478	1			T35	48		T38	199		T39	16308
all_pins[15]	transitions[0x1=>0x0]	825377	1			T35	50		T38	193		T39	15931
all_pins[16]	values[0x0]	2259672	1			T35	95		T36	1		T37	1
all_pins[16]	values[0x1]	1381803	1			T35	95		T38	328		T39	26676
all_pins[16]	transitions[0x0=>0x1]	829942	1			T35	53		T38	184		T39	15802
all_pins[16]	transitions[0x1=>0x0]	828213	1			T35	26		T38	169		T39	16050
all_pins[17]	values[0x0]	2261460	1			T35	159		T36	1		T37	1
all_pins[17]	values[0x1]	1380015	1			T35	31		T38	293		T39	27291
all_pins[17]	transitions[0x0=>0x1]	826785	1			T35	9		T38	151		T39	16150
all_pins[17]	transitions[0x1=>0x0]	828573	1			T35	73		T38	186		T39	15535
all_pins[18]	values[0x0]	2265448	1			T35	122		T36	1		T37	1
all_pins[18]	values[0x1]	1376027	1			T35	68		T38	222		T39	27176
all_pins[18]	transitions[0x0=>0x1]	825857	1			T35	62		T38	115		T39	16321
all_pins[18]	transitions[0x1=>0x0]	829845	1			T35	25		T38	186		T39	16436
all_pins[19]	values[0x0]	2261304	1			T35	131		T36	1		T37	1
all_pins[19]	values[0x1]	1380171	1			T35	59		T38	253		T39	26577
all_pins[19]	transitions[0x0=>0x1]	828152	1			T35	40		T38	193		T39	15844
all_pins[19]	transitions[0x1=>0x0]	824008	1			T35	49		T38	162		T39	16443
all_pins[20]	values[0x0]	2263822	1			T35	138		T36	1		T37	1
all_pins[20]	values[0x1]	1377653	1			T35	52		T38	282		T39	26611
all_pins[20]	transitions[0x0=>0x1]	825171	1			T35	37		T38	169		T39	16406
all_pins[20]	transitions[0x1=>0x0]	827689	1			T35	44		T38	140		T39	16372
all_pins[21]	values[0x0]	2264233	1			T35	118		T36	1		T37	1
all_pins[21]	values[0x1]	1377242	1			T35	72		T38	234		T39	26670
all_pins[21]	transitions[0x0=>0x1]	825618	1			T35	51		T38	122		T39	16135
all_pins[21]	transitions[0x1=>0x0]	826029	1			T35	31		T38	170		T39	16076
all_pins[22]	values[0x0]	2260841	1			T35	98		T36	1		T37	1
all_pins[22]	values[0x1]	1380634	1			T35	92		T38	258		T39	26610
all_pins[22]	transitions[0x0=>0x1]	826761	1			T35	52		T38	167		T39	16011
all_pins[22]	transitions[0x1=>0x0]	823369	1			T35	32		T38	143		T39	16071
all_pins[23]	values[0x0]	2266164	1			T35	139		T36	1		T37	1
all_pins[23]	values[0x1]	1375311	1			T35	51		T38	324		T39	27434
all_pins[23]	transitions[0x0=>0x1]	821961	1			T35	24		T38	198		T39	16263
all_pins[23]	transitions[0x1=>0x0]	827284	1			T35	65		T38	132		T39	15439
all_pins[24]	values[0x0]	2263875	1			T35	129		T36	1		T37	1
all_pins[24]	values[0x1]	1377600	1			T35	61		T38	327		T39	26836
all_pins[24]	transitions[0x0=>0x1]	824474	1			T35	38		T38	173		T39	15595
all_pins[24]	transitions[0x1=>0x0]	822185	1			T35	28		T38	170		T39	16193
all_pins[25]	values[0x0]	2263264	1			T35	106		T36	1		T37	1
all_pins[25]	values[0x1]	1378211	1			T35	84		T38	289		T39	26379
all_pins[25]	transitions[0x0=>0x1]	825307	1			T35	59		T38	166		T39	15566
all_pins[25]	transitions[0x1=>0x0]	824696	1			T35	36		T38	204		T39	16023
all_pins[26]	values[0x0]	2265711	1			T35	117		T36	1		T37	1
all_pins[26]	values[0x1]	1375764	1			T35	73		T38	287		T39	26988
all_pins[26]	transitions[0x0=>0x1]	823629	1			T35	39		T38	170		T39	16603
all_pins[26]	transitions[0x1=>0x0]	826076	1			T35	50		T38	172		T39	15994
all_pins[27]	values[0x0]	2261353	1			T35	121		T36	1		T37	1
all_pins[27]	values[0x1]	1380122	1			T35	69		T38	252		T39	26471
all_pins[27]	transitions[0x0=>0x1]	827013	1			T35	37		T38	139		T39	15844
all_pins[27]	transitions[0x1=>0x0]	822655	1			T35	41		T38	174		T39	16361
all_pins[28]	values[0x0]	2260897	1			T35	124		T36	1		T37	1
all_pins[28]	values[0x1]	1380578	1			T35	66		T38	376		T39	26960
all_pins[28]	transitions[0x0=>0x1]	823969	1			T35	30		T38	257		T39	16534
all_pins[28]	transitions[0x1=>0x0]	823513	1			T35	33		T38	133		T39	16045
all_pins[29]	values[0x0]	2264004	1			T35	106		T36	1		T37	1
all_pins[29]	values[0x1]	1377471	1			T35	84		T38	315		T39	26866
all_pins[29]	transitions[0x0=>0x1]	823722	1			T35	42		T38	162		T39	16132
all_pins[29]	transitions[0x1=>0x0]	826829	1			T35	24		T38	223		T39	16226
all_pins[30]	values[0x0]	2263961	1			T35	114		T36	1		T37	1
all_pins[30]	values[0x1]	1377514	1			T35	76		T38	325		T39	26500
all_pins[30]	transitions[0x0=>0x1]	827171	1			T35	43		T38	154		T39	15927
all_pins[30]	transitions[0x1=>0x0]	827128	1			T35	51		T38	144		T39	16293
all_pins[31]	values[0x0]	2265470	1			T35	93		T36	1		T37	1
all_pins[31]	values[0x1]	1376005	1			T35	97		T38	268		T39	26589
all_pins[31]	transitions[0x0=>0x1]	826206	1			T35	52		T38	127		T39	16094
all_pins[31]	transitions[0x1=>0x0]	827715	1			T35	31		T38	184		T39	16005