Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[1]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[2]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[3]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[4]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[5]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[6]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[7]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[8]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[9]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[10]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[11]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[12]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[13]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[14]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[15]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[16]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[17]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[18]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[19]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[20]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[21]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[22]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[23]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[24]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[25]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[26]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[27]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[28]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[29]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[30]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[31]	12167742	1			T35	161		T36	570		T37	360

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230583947

1

T35

2641

T36

12954

T37

9083

auto[1]

158783797

1

T35

2511

T36

5286

T37

2437

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313073255

1

T35

5152

T36

10276

T37

8950

auto[1]

76294489

1

T36

7964

T37

2570

T38

25647

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

291064519

1

T35

5152

T36

10580

T37

5942

auto[1]

98303225

1

T36

7660

T37

5578

T38

29649

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4510726	1			T35	96		T36	159		T37	172
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3386397	1			T35	65		T36	34		T37	23
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1199255	1			T36	142		T37	60		T38	290
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1488759	1			T36	100		T37	63		T38	16
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	394656	1			T37	6		T38	518		T39	2237
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1187949	1			T36	135		T37	36		T38	445
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4512945	1			T35	97		T36	158		T37	130
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3378023	1			T35	64		T36	42		T37	12
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1194141	1			T36	138		T37	43		T38	428
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1494299	1			T36	78		T37	137		T38	14
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	393174	1			T37	16		T38	533		T39	2174
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1195160	1			T36	154		T37	22		T38	362
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4517328	1			T35	96		T36	155		T37	122
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3376061	1			T35	65		T36	39		T37	19
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1199523	1			T36	112		T37	42		T38	384
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1496115	1			T36	120		T37	112		T38	16
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	391266	1			T37	21		T38	574		T39	2213
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1187449	1			T36	144		T37	44		T38	352
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4506934	1			T35	86		T36	142		T37	112
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3384187	1			T35	75		T36	39		T37	21
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1198474	1			T36	134		T37	20		T38	411
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1493441	1			T36	112		T37	119		T38	21
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	391729	1			T37	18		T38	450		T39	2426
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1192977	1			T36	143		T37	70		T38	353
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4506609	1			T35	79		T36	161		T37	168
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3382777	1			T35	82		T36	38		T37	27
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1199736	1			T36	108		T37	36		T38	387
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1492460	1			T36	138		T37	78		T38	19
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	394757	1			T37	11		T38	534		T39	2157
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1191403	1			T36	125		T37	40		T38	388
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4519930	1			T35	99		T36	153		T37	137
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3376021	1			T35	62		T36	34		T37	24
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1200933	1			T36	116		T37	33		T38	417
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1490373	1			T36	123		T37	110		T38	15
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	394210	1			T37	9		T38	495		T39	2225
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1186275	1			T36	144		T37	47		T38	345
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4512213	1			T35	87		T36	193		T37	125
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3381700	1			T35	74		T36	42		T37	11
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1200671	1			T36	147		T37	35		T38	408
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1490491	1			T36	94		T37	120		T38	11
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	392886	1			T37	23		T38	480		T39	2382
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1189781	1			T36	94		T37	46		T38	480
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4524369	1			T35	75		T36	168		T37	101
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3376198	1			T35	86		T36	47		T37	13
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1203014	1			T36	148		T37	21		T38	515
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1483492	1			T36	71		T37	157		T38	17
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	392065	1			T37	21		T38	470		T39	2251
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1188604	1			T36	136		T37	47		T38	300
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4523731	1			T35	73		T36	181		T37	127
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3379214	1			T35	88		T36	38		T37	23
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1202824	1			T36	91		T37	44		T38	464
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1485509	1			T36	130		T37	115		T38	22
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	391480	1			T37	11		T38	550		T39	2080
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1184984	1			T36	130		T37	40		T38	417
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4507763	1			T35	89		T36	130		T37	103
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3386628	1			T35	72		T36	47		T37	10
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1195579	1			T36	118		T37	30		T38	310
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1492196	1			T36	160		T37	154		T38	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	392763	1			T37	21		T38	520		T39	2166
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1192813	1			T36	115		T37	42		T38	403
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4517631	1			T35	68		T36	148		T37	138
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3378520	1			T35	93		T36	35		T37	18
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1192574	1			T36	127		T37	41		T38	339
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1496019	1			T36	122		T37	108		T38	13
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	391718	1			T37	14		T38	455		T39	2219
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1191280	1			T36	138		T37	41		T38	468
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4513751	1			T35	76		T36	165		T37	64
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3379761	1			T35	85		T36	40		T37	11
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1198387	1			T36	117		T37	49		T38	348
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1492770	1			T36	148		T37	140		T38	26
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	392868	1			T37	19		T38	516		T39	2135
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1190205	1			T36	100		T37	77		T38	340
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4512458	1			T35	77		T36	205		T37	139
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3382678	1			T35	84		T36	35		T37	23
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1201733	1			T36	86		T37	34		T38	383
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1488923	1			T36	122		T37	123		T38	18
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	389909	1			T37	8		T38	533		T39	2274
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1192041	1			T36	122		T37	33		T38	409
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4512157	1			T35	87		T36	180		T37	135
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3384952	1			T35	74		T36	47		T37	20
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1196509	1			T36	112		T37	42		T38	396
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1493339	1			T36	123		T37	118		T38	22
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	390759	1			T37	11		T38	456		T39	2230
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1190026	1			T36	108		T37	34		T38	403
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4521665	1			T35	80		T36	124		T37	125
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3375919	1			T35	81		T36	43		T37	19
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1200606	1			T36	112		T37	52		T38	387
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1485727	1			T36	115		T37	94		T38	33
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	392884	1			T37	19		T38	524		T39	2283
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1190941	1			T36	176		T37	51		T38	440
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4518455	1			T35	83		T36	149		T37	135
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3381188	1			T35	78		T36	41		T37	10
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1202700	1			T36	108		T37	47		T38	347
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1490792	1			T36	144		T37	123		T38	15
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	391551	1			T37	21		T38	510		T39	2341
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1183056	1			T36	128		T37	24		T38	567
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4520148	1			T35	58		T36	179		T37	79
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3384380	1			T35	103		T36	42		T37	21
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1195731	1			T36	146		T37	21		T38	385
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1492728	1			T36	97		T37	153		T38	20
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	394020	1			T37	21		T38	475		T39	2304
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1180735	1			T36	106		T37	65		T38	431
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4523883	1			T35	84		T36	162		T37	165
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3378880	1			T35	77		T36	35		T37	10
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1195257	1			T36	154		T37	31		T38	491
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1494207	1			T36	92		T37	105		T38	15
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	390506	1			T37	8		T38	466		T39	2063
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1185009	1			T36	127		T37	41		T38	345
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4522171	1			T35	86		T36	178		T37	100
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3379762	1			T35	75		T36	39		T37	9
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1193218	1			T36	113		T37	33		T38	363
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1496008	1			T36	128		T37	148		T38	18
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	392259	1			T37	19		T38	511		T39	2333
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1184324	1			T36	112		T37	51		T38	254
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4508564	1			T35	89		T36	165		T37	196
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3390080	1			T35	72		T36	46		T37	28
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1198833	1			T36	108		T37	32		T38	524
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1496454	1			T36	127		T37	69		T38	15
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	393102	1			T37	10		T38	477		T39	2292
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1180709	1			T36	124		T37	25		T38	363
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4507910	1			T35	89		T36	161		T37	158
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3389553	1			T35	72		T36	39		T37	20
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1197068	1			T36	126		T37	36		T38	362
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1495792	1			T36	126		T37	115		T38	23
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	391298	1			T37	7		T38	527		T39	2376
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1186121	1			T36	118		T37	24		T38	371
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4514468	1			T35	72		T36	172		T37	198
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3381225	1			T35	89		T36	39		T37	38
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1195188	1			T36	135		T37	46		T38	356
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1494722	1			T36	102		T37	56		T38	14
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	395274	1			T37	3		T38	560		T39	2283
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1186865	1			T36	122		T37	19		T38	394
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4515274	1			T35	77		T36	175		T37	130
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3384671	1			T35	84		T36	44		T37	16
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1195430	1			T36	120		T37	12		T38	451
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1494761	1			T36	98		T37	153		T38	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	392140	1			T37	16		T38	421		T39	2220
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1185466	1			T36	133		T37	33		T38	466
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4507681	1			T35	75		T36	177		T37	149
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3390931	1			T35	86		T36	36		T37	12
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1191451	1			T36	113		T37	37		T38	359
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1498330	1			T36	136		T37	105		T38	30
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	393390	1			T37	22		T38	518		T39	2122
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1185959	1			T36	108		T37	35		T38	334
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4524782	1			T35	86		T36	174		T37	96
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3378635	1			T35	75		T36	43		T37	18
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1196261	1			T36	174		T37	34		T38	406
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1493380	1			T36	97		T37	148		T38	28
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	393472	1			T37	6		T38	437		T39	2255
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1181212	1			T36	82		T37	58		T38	480
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4512164	1			T35	81		T36	147		T37	110
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3389026	1			T35	80		T36	48		T37	18
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1190533	1			T36	135		T37	23		T38	354
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1494714	1			T36	106		T37	154		T38	32
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	393227	1			T37	21		T38	606		T39	2283
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1188078	1			T36	134		T37	34		T38	396
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4517370	1			T35	80		T36	184		T37	135
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3384959	1			T35	81		T36	34		T37	26
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1198928	1			T36	116		T37	57		T38	443
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1487972	1			T36	124		T37	79		T38	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	392074	1			T37	11		T38	470		T39	2181
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1186439	1			T36	112		T37	52		T38	442
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4509142	1			T35	78		T36	151		T37	108
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3388895	1			T35	83		T36	49		T37	18
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1191986	1			T36	130		T37	33		T38	385
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1497161	1			T36	98		T37	123		T38	5
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	392454	1			T37	20		T38	451		T39	2302
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1188104	1			T36	142		T37	58		T38	440
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4522334	1			T35	71		T36	176		T37	112
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3385046	1			T35	90		T36	47		T37	17
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1194110	1			T36	92		T37	51		T38	407
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1493772	1			T36	131		T37	114		T38	29
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	392221	1			T37	18		T38	492		T39	2226
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1180259	1			T36	124		T37	48		T38	347
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4525914	1			T35	84		T36	163		T37	127
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3374238	1			T35	77		T36	44		T37	16
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1199219	1			T36	132		T37	31		T38	392
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1489851	1			T36	110		T37	104		T38	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	391598	1			T37	16		T38	526		T39	2148
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1186922	1			T36	121		T37	66		T38	498
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4520443	1			T35	92		T36	180		T37	139
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3389512	1			T35	69		T36	39		T37	17
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1194552	1			T36	136		T37	34		T38	407
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1489876	1			T36	94		T37	92		T38	28
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	392386	1			T37	10		T38	474		T39	2302
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1180973	1			T36	121		T37	68		T38	451
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4521933	1			T35	91		T36	171		T37	149
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3379659	1			T35	70		T36	43		T37	9
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1197573	1			T36	140		T37	41		T38	387
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1494671	1			T36	116		T37	129		T38	22
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	393533	1			T37	14		T38	529		T39	2134
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1180373	1			T36	100		T37	18		T38	477

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal