Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[1]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[2]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[3]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[4]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[5]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[6]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[7]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[8]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[9]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[10]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[11]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[12]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[13]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[14]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[15]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[16]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[17]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[18]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[19]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[20]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[21]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[22]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[23]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[24]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[25]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[26]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[27]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[28]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[29]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[30]	12167742	1			T35	161		T36	570		T37	360
bins_for_gpio_bits[31]	12167742	1			T35	161		T36	570		T37	360

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230583947

1

T35

2641

T36

12954

T37

9083

auto[1]

158783797

1

T35

2511

T36

5286

T37

2437

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230575814

1

T35

2641

T36

12946

T37

9083

auto[1]

158791930

1

T35

2511

T36

5294

T37

2437

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6986253	1			T35	96		T36	366		T37	289
bins_for_gpio_bits[0]	auto[0]	auto[1]	212226	1			T36	34		T37	6		T38	47
bins_for_gpio_bits[0]	auto[1]	auto[0]	212487	1			T36	35		T37	6		T38	47
bins_for_gpio_bits[0]	auto[1]	auto[1]	4756776	1			T35	65		T36	135		T37	59
bins_for_gpio_bits[1]	auto[0]	auto[0]	6987899	1			T35	97		T36	343		T37	305
bins_for_gpio_bits[1]	auto[0]	auto[1]	213210	1			T36	31		T37	5		T38	55
bins_for_gpio_bits[1]	auto[1]	auto[0]	213486	1			T36	31		T37	5		T38	55
bins_for_gpio_bits[1]	auto[1]	auto[1]	4753147	1			T35	64		T36	165		T37	45
bins_for_gpio_bits[2]	auto[0]	auto[0]	6999851	1			T35	96		T36	350		T37	270
bins_for_gpio_bits[2]	auto[0]	auto[1]	212859	1			T36	37		T37	6		T38	50
bins_for_gpio_bits[2]	auto[1]	auto[0]	213115	1			T36	37		T37	6		T38	50
bins_for_gpio_bits[2]	auto[1]	auto[1]	4741917	1			T35	65		T36	146		T37	78
bins_for_gpio_bits[3]	auto[0]	auto[0]	6985360	1			T35	86		T36	353		T37	238
bins_for_gpio_bits[3]	auto[0]	auto[1]	213231	1			T36	34		T37	13		T38	60
bins_for_gpio_bits[3]	auto[1]	auto[0]	213489	1			T36	35		T37	13		T38	60
bins_for_gpio_bits[3]	auto[1]	auto[1]	4755662	1			T35	75		T36	148		T37	96
bins_for_gpio_bits[4]	auto[0]	auto[0]	6985239	1			T35	79		T36	377		T37	274
bins_for_gpio_bits[4]	auto[0]	auto[1]	213273	1			T36	29		T37	8		T38	49
bins_for_gpio_bits[4]	auto[1]	auto[0]	213566	1			T36	30		T37	8		T38	49
bins_for_gpio_bits[4]	auto[1]	auto[1]	4755664	1			T35	82		T36	134		T37	70
bins_for_gpio_bits[5]	auto[0]	auto[0]	6998523	1			T35	99		T36	359		T37	270
bins_for_gpio_bits[5]	auto[0]	auto[1]	212453	1			T36	33		T37	10		T38	60
bins_for_gpio_bits[5]	auto[1]	auto[0]	212713	1			T36	33		T37	10		T38	60
bins_for_gpio_bits[5]	auto[1]	auto[1]	4744053	1			T35	62		T36	145		T37	70
bins_for_gpio_bits[6]	auto[0]	auto[0]	6990176	1			T35	87		T36	406		T37	273
bins_for_gpio_bits[6]	auto[0]	auto[1]	212941	1			T36	28		T37	7		T38	66
bins_for_gpio_bits[6]	auto[1]	auto[0]	213199	1			T36	28		T37	7		T38	66
bins_for_gpio_bits[6]	auto[1]	auto[1]	4751426	1			T35	74		T36	108		T37	73
bins_for_gpio_bits[7]	auto[0]	auto[0]	6998020	1			T35	75		T36	360		T37	268
bins_for_gpio_bits[7]	auto[0]	auto[1]	212563	1			T36	27		T37	11		T38	62
bins_for_gpio_bits[7]	auto[1]	auto[0]	212855	1			T36	27		T37	11		T38	62
bins_for_gpio_bits[7]	auto[1]	auto[1]	4744304	1			T35	86		T36	156		T37	70
bins_for_gpio_bits[8]	auto[0]	auto[0]	6999012	1			T35	73		T36	370		T37	278
bins_for_gpio_bits[8]	auto[0]	auto[1]	212795	1			T36	32		T37	8		T38	58
bins_for_gpio_bits[8]	auto[1]	auto[0]	213052	1			T36	32		T37	8		T38	58
bins_for_gpio_bits[8]	auto[1]	auto[1]	4742883	1			T35	88		T36	136		T37	66
bins_for_gpio_bits[9]	auto[0]	auto[0]	6982390	1			T35	89		T36	375		T37	279
bins_for_gpio_bits[9]	auto[0]	auto[1]	212934	1			T36	32		T37	8		T38	56
bins_for_gpio_bits[9]	auto[1]	auto[0]	213148	1			T36	33		T37	8		T38	56
bins_for_gpio_bits[9]	auto[1]	auto[1]	4759270	1			T35	72		T36	130		T37	65
bins_for_gpio_bits[10]	auto[0]	auto[0]	6993074	1			T35	68		T36	368		T37	280
bins_for_gpio_bits[10]	auto[0]	auto[1]	212945	1			T36	29		T37	7		T38	55
bins_for_gpio_bits[10]	auto[1]	auto[0]	213150	1			T36	29		T37	7		T38	55
bins_for_gpio_bits[10]	auto[1]	auto[1]	4748573	1			T35	93		T36	144		T37	66
bins_for_gpio_bits[11]	auto[0]	auto[0]	6992451	1			T35	76		T36	401		T37	243
bins_for_gpio_bits[11]	auto[0]	auto[1]	212216	1			T36	29		T37	10		T38	61
bins_for_gpio_bits[11]	auto[1]	auto[0]	212457	1			T36	29		T37	10		T38	61
bins_for_gpio_bits[11]	auto[1]	auto[1]	4750618	1			T35	85		T36	111		T37	97
bins_for_gpio_bits[12]	auto[0]	auto[0]	6989935	1			T35	77		T36	384		T37	287
bins_for_gpio_bits[12]	auto[0]	auto[1]	212890	1			T36	29		T37	9		T38	60
bins_for_gpio_bits[12]	auto[1]	auto[0]	213179	1			T36	29		T37	9		T38	60
bins_for_gpio_bits[12]	auto[1]	auto[1]	4751738	1			T35	84		T36	128		T37	55
bins_for_gpio_bits[13]	auto[0]	auto[0]	6989130	1			T35	87		T36	389		T37	287
bins_for_gpio_bits[13]	auto[0]	auto[1]	212646	1			T36	26		T37	8		T38	57
bins_for_gpio_bits[13]	auto[1]	auto[0]	212875	1			T36	26		T37	8		T38	57
bins_for_gpio_bits[13]	auto[1]	auto[1]	4753091	1			T35	74		T36	129		T37	57
bins_for_gpio_bits[14]	auto[0]	auto[0]	6994980	1			T35	80		T36	319		T37	260
bins_for_gpio_bits[14]	auto[0]	auto[1]	212770	1			T36	32		T37	11		T38	59
bins_for_gpio_bits[14]	auto[1]	auto[0]	213018	1			T36	32		T37	11		T38	59
bins_for_gpio_bits[14]	auto[1]	auto[1]	4746974	1			T35	81		T36	187		T37	78
bins_for_gpio_bits[15]	auto[0]	auto[0]	6999147	1			T35	83		T36	366		T37	299
bins_for_gpio_bits[15]	auto[0]	auto[1]	212523	1			T36	35		T37	6		T38	50
bins_for_gpio_bits[15]	auto[1]	auto[0]	212800	1			T36	35		T37	6		T38	50
bins_for_gpio_bits[15]	auto[1]	auto[1]	4743272	1			T35	78		T36	134		T37	49
bins_for_gpio_bits[16]	auto[0]	auto[0]	6995857	1			T35	58		T36	395		T37	241
bins_for_gpio_bits[16]	auto[0]	auto[1]	212469	1			T36	27		T37	12		T38	64
bins_for_gpio_bits[16]	auto[1]	auto[0]	212750	1			T36	27		T37	12		T38	64
bins_for_gpio_bits[16]	auto[1]	auto[1]	4746666	1			T35	103		T36	121		T37	95
bins_for_gpio_bits[17]	auto[0]	auto[0]	7000531	1			T35	84		T36	377		T37	294
bins_for_gpio_bits[17]	auto[0]	auto[1]	212585	1			T36	30		T37	7		T38	62
bins_for_gpio_bits[17]	auto[1]	auto[0]	212816	1			T36	31		T37	7		T38	62
bins_for_gpio_bits[17]	auto[1]	auto[1]	4741810	1			T35	77		T36	132		T37	52
bins_for_gpio_bits[18]	auto[0]	auto[0]	6998483	1			T35	86		T36	387		T37	271
bins_for_gpio_bits[18]	auto[0]	auto[1]	212687	1			T36	32		T37	10		T38	55
bins_for_gpio_bits[18]	auto[1]	auto[0]	212914	1			T36	32		T37	10		T38	55
bins_for_gpio_bits[18]	auto[1]	auto[1]	4743658	1			T35	75		T36	119		T37	69
bins_for_gpio_bits[19]	auto[0]	auto[0]	6990787	1			T35	89		T36	369		T37	292
bins_for_gpio_bits[19]	auto[0]	auto[1]	212776	1			T36	31		T37	5		T38	63
bins_for_gpio_bits[19]	auto[1]	auto[0]	213064	1			T36	31		T37	5		T38	63
bins_for_gpio_bits[19]	auto[1]	auto[1]	4751115	1			T35	72		T36	139		T37	58
bins_for_gpio_bits[20]	auto[0]	auto[0]	6987251	1			T35	89		T36	386		T37	303
bins_for_gpio_bits[20]	auto[0]	auto[1]	213244	1			T36	27		T37	6		T38	59
bins_for_gpio_bits[20]	auto[1]	auto[0]	213519	1			T36	27		T37	6		T38	59
bins_for_gpio_bits[20]	auto[1]	auto[1]	4753728	1			T35	72		T36	130		T37	45
bins_for_gpio_bits[21]	auto[0]	auto[0]	6991628	1			T35	72		T36	382		T37	295
bins_for_gpio_bits[21]	auto[0]	auto[1]	212505	1			T36	27		T37	5		T38	49
bins_for_gpio_bits[21]	auto[1]	auto[0]	212750	1			T36	27		T37	5		T38	49
bins_for_gpio_bits[21]	auto[1]	auto[1]	4750859	1			T35	89		T36	134		T37	55
bins_for_gpio_bits[22]	auto[0]	auto[0]	6992516	1			T35	77		T36	364		T37	288
bins_for_gpio_bits[22]	auto[0]	auto[1]	212719	1			T36	28		T37	7		T38	64
bins_for_gpio_bits[22]	auto[1]	auto[0]	212949	1			T36	29		T37	7		T38	64
bins_for_gpio_bits[22]	auto[1]	auto[1]	4749558	1			T35	84		T36	149		T37	58
bins_for_gpio_bits[23]	auto[0]	auto[0]	6984863	1			T35	75		T36	393		T37	285
bins_for_gpio_bits[23]	auto[0]	auto[1]	212327	1			T36	33		T37	6		T38	54
bins_for_gpio_bits[23]	auto[1]	auto[0]	212599	1			T36	33		T37	6		T38	54
bins_for_gpio_bits[23]	auto[1]	auto[1]	4757953	1			T35	86		T36	111		T37	63
bins_for_gpio_bits[24]	auto[0]	auto[0]	7001400	1			T35	86		T36	419		T37	271
bins_for_gpio_bits[24]	auto[0]	auto[1]	212772	1			T36	26		T37	7		T38	55
bins_for_gpio_bits[24]	auto[1]	auto[0]	213023	1			T36	26		T37	7		T38	55
bins_for_gpio_bits[24]	auto[1]	auto[1]	4740547	1			T35	75		T36	99		T37	75
bins_for_gpio_bits[25]	auto[0]	auto[0]	6984117	1			T35	81		T36	352		T37	279
bins_for_gpio_bits[25]	auto[0]	auto[1]	213017	1			T36	36		T37	8		T38	48
bins_for_gpio_bits[25]	auto[1]	auto[0]	213294	1			T36	36		T37	8		T38	48
bins_for_gpio_bits[25]	auto[1]	auto[1]	4757314	1			T35	80		T36	146		T37	65
bins_for_gpio_bits[26]	auto[0]	auto[0]	6990968	1			T35	80		T36	393		T37	260
bins_for_gpio_bits[26]	auto[0]	auto[1]	213011	1			T36	31		T37	11		T38	66
bins_for_gpio_bits[26]	auto[1]	auto[0]	213302	1			T36	31		T37	11		T38	66
bins_for_gpio_bits[26]	auto[1]	auto[1]	4750461	1			T35	81		T36	115		T37	78
bins_for_gpio_bits[27]	auto[0]	auto[0]	6984934	1			T35	78		T36	343		T37	255
bins_for_gpio_bits[27]	auto[0]	auto[1]	213135	1			T36	36		T37	9		T38	57
bins_for_gpio_bits[27]	auto[1]	auto[0]	213355	1			T36	36		T37	9		T38	57
bins_for_gpio_bits[27]	auto[1]	auto[1]	4756318	1			T35	83		T36	155		T37	87
bins_for_gpio_bits[28]	auto[0]	auto[0]	6997477	1			T35	71		T36	369		T37	267
bins_for_gpio_bits[28]	auto[0]	auto[1]	212504	1			T36	30		T37	10		T38	55
bins_for_gpio_bits[28]	auto[1]	auto[0]	212739	1			T36	30		T37	10		T38	55
bins_for_gpio_bits[28]	auto[1]	auto[1]	4745022	1			T35	90		T36	141		T37	73
bins_for_gpio_bits[29]	auto[0]	auto[0]	7001595	1			T35	84		T36	375		T37	251
bins_for_gpio_bits[29]	auto[0]	auto[1]	213178	1			T36	29		T37	11		T38	59
bins_for_gpio_bits[29]	auto[1]	auto[0]	213389	1			T36	30		T37	11		T38	59
bins_for_gpio_bits[29]	auto[1]	auto[1]	4739580	1			T35	77		T36	136		T37	87
bins_for_gpio_bits[30]	auto[0]	auto[0]	6992498	1			T35	92		T36	379		T37	254
bins_for_gpio_bits[30]	auto[0]	auto[1]	212160	1			T36	30		T37	11		T38	71
bins_for_gpio_bits[30]	auto[1]	auto[0]	212373	1			T36	31		T37	11		T38	71
bins_for_gpio_bits[30]	auto[1]	auto[1]	4750711	1			T35	69		T36	130		T37	84
bins_for_gpio_bits[31]	auto[0]	auto[0]	7001124	1			T35	91		T36	395		T37	314
bins_for_gpio_bits[31]	auto[0]	auto[1]	212781	1			T36	32		T37	5		T38	55
bins_for_gpio_bits[31]	auto[1]	auto[0]	213053	1			T36	32		T37	5		T38	55
bins_for_gpio_bits[31]	auto[1]	auto[1]	4740784	1			T35	70		T36	111		T37	36