Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7219058 |
1 |
|
|
T35 |
178 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5150189 |
1 |
|
|
T35 |
141 |
|
T38 |
1065 |
|
T39 |
102003 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11710231 |
1 |
|
|
T35 |
310 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
659016 |
1 |
|
|
T35 |
9 |
|
T38 |
26 |
|
T39 |
11631 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7197327 |
1 |
|
|
T35 |
176 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5171920 |
1 |
|
|
T35 |
143 |
|
T38 |
732 |
|
T39 |
95870 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2266781 |
1 |
|
|
T35 |
85 |
|
T38 |
276 |
|
T39 |
41464 |
| auto[1] |
auto[0] |
auto[1] |
330523 |
1 |
|
|
T35 |
6 |
|
T38 |
8 |
|
T39 |
5792 |
| auto[1] |
auto[1] |
auto[0] |
2246123 |
1 |
|
|
T35 |
49 |
|
T38 |
430 |
|
T39 |
42775 |
| auto[1] |
auto[1] |
auto[1] |
328493 |
1 |
|
|
T35 |
3 |
|
T38 |
18 |
|
T39 |
5839 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7217447 |
1 |
|
|
T35 |
181 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5151800 |
1 |
|
|
T35 |
138 |
|
T38 |
1265 |
|
T39 |
100147 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11710486 |
1 |
|
|
T35 |
313 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
658761 |
1 |
|
|
T35 |
6 |
|
T38 |
35 |
|
T39 |
12006 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7210187 |
1 |
|
|
T35 |
185 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5159060 |
1 |
|
|
T35 |
134 |
|
T38 |
938 |
|
T39 |
95297 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2255486 |
1 |
|
|
T35 |
74 |
|
T38 |
322 |
|
T39 |
41968 |
| auto[1] |
auto[0] |
auto[1] |
331062 |
1 |
|
|
T35 |
3 |
|
T38 |
9 |
|
T39 |
5997 |
| auto[1] |
auto[1] |
auto[0] |
2244813 |
1 |
|
|
T35 |
54 |
|
T38 |
581 |
|
T39 |
41323 |
| auto[1] |
auto[1] |
auto[1] |
327699 |
1 |
|
|
T35 |
3 |
|
T38 |
26 |
|
T39 |
6009 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7193362 |
1 |
|
|
T35 |
177 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5175885 |
1 |
|
|
T35 |
142 |
|
T38 |
1101 |
|
T39 |
98618 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11712111 |
1 |
|
|
T35 |
308 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
657136 |
1 |
|
|
T35 |
11 |
|
T38 |
36 |
|
T39 |
11883 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7226018 |
1 |
|
|
T35 |
194 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5143229 |
1 |
|
|
T35 |
125 |
|
T38 |
953 |
|
T39 |
96212 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2237676 |
1 |
|
|
T35 |
56 |
|
T38 |
438 |
|
T39 |
41529 |
| auto[1] |
auto[0] |
auto[1] |
327223 |
1 |
|
|
T35 |
4 |
|
T38 |
20 |
|
T39 |
5993 |
| auto[1] |
auto[1] |
auto[0] |
2248417 |
1 |
|
|
T35 |
58 |
|
T38 |
479 |
|
T39 |
42800 |
| auto[1] |
auto[1] |
auto[1] |
329913 |
1 |
|
|
T35 |
7 |
|
T38 |
16 |
|
T39 |
5890 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7212558 |
1 |
|
|
T35 |
116 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5156689 |
1 |
|
|
T35 |
203 |
|
T38 |
939 |
|
T39 |
103001 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11717386 |
1 |
|
|
T35 |
311 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
651861 |
1 |
|
|
T35 |
8 |
|
T38 |
50 |
|
T39 |
12048 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7249840 |
1 |
|
|
T35 |
186 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5119407 |
1 |
|
|
T35 |
133 |
|
T38 |
1059 |
|
T39 |
96594 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2240275 |
1 |
|
|
T35 |
45 |
|
T38 |
556 |
|
T39 |
40570 |
| auto[1] |
auto[0] |
auto[1] |
327730 |
1 |
|
|
T35 |
2 |
|
T38 |
31 |
|
T39 |
5696 |
| auto[1] |
auto[1] |
auto[0] |
2227271 |
1 |
|
|
T35 |
80 |
|
T38 |
453 |
|
T39 |
43976 |
| auto[1] |
auto[1] |
auto[1] |
324131 |
1 |
|
|
T35 |
6 |
|
T38 |
19 |
|
T39 |
6352 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7203605 |
1 |
|
|
T35 |
163 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5165642 |
1 |
|
|
T35 |
156 |
|
T38 |
1060 |
|
T39 |
104503 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11708174 |
1 |
|
|
T35 |
305 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
661073 |
1 |
|
|
T35 |
14 |
|
T38 |
37 |
|
T39 |
12216 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7198665 |
1 |
|
|
T35 |
107 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5170582 |
1 |
|
|
T35 |
212 |
|
T38 |
930 |
|
T39 |
97851 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2253728 |
1 |
|
|
T35 |
108 |
|
T38 |
470 |
|
T39 |
41818 |
| auto[1] |
auto[0] |
auto[1] |
329118 |
1 |
|
|
T35 |
8 |
|
T38 |
13 |
|
T39 |
5883 |
| auto[1] |
auto[1] |
auto[0] |
2255781 |
1 |
|
|
T35 |
90 |
|
T38 |
423 |
|
T39 |
43817 |
| auto[1] |
auto[1] |
auto[1] |
331955 |
1 |
|
|
T35 |
6 |
|
T38 |
24 |
|
T39 |
6333 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7181123 |
1 |
|
|
T35 |
167 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5188124 |
1 |
|
|
T35 |
152 |
|
T38 |
1014 |
|
T39 |
102263 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11712006 |
1 |
|
|
T35 |
314 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
657241 |
1 |
|
|
T35 |
5 |
|
T38 |
40 |
|
T39 |
12942 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7214715 |
1 |
|
|
T35 |
178 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5154532 |
1 |
|
|
T35 |
141 |
|
T38 |
933 |
|
T39 |
102620 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2230930 |
1 |
|
|
T35 |
68 |
|
T38 |
460 |
|
T39 |
42460 |
| auto[1] |
auto[0] |
auto[1] |
324701 |
1 |
|
|
T35 |
3 |
|
T38 |
21 |
|
T39 |
5983 |
| auto[1] |
auto[1] |
auto[0] |
2266361 |
1 |
|
|
T35 |
68 |
|
T38 |
433 |
|
T39 |
47218 |
| auto[1] |
auto[1] |
auto[1] |
332540 |
1 |
|
|
T35 |
2 |
|
T38 |
19 |
|
T39 |
6959 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7198762 |
1 |
|
|
T35 |
164 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5170485 |
1 |
|
|
T35 |
155 |
|
T38 |
1043 |
|
T39 |
96094 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11713977 |
1 |
|
|
T35 |
309 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
655270 |
1 |
|
|
T35 |
10 |
|
T38 |
50 |
|
T39 |
12275 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7231346 |
1 |
|
|
T35 |
143 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5137901 |
1 |
|
|
T35 |
176 |
|
T38 |
1129 |
|
T39 |
98433 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2243329 |
1 |
|
|
T35 |
79 |
|
T38 |
524 |
|
T39 |
44956 |
| auto[1] |
auto[0] |
auto[1] |
328139 |
1 |
|
|
T35 |
5 |
|
T38 |
25 |
|
T39 |
6564 |
| auto[1] |
auto[1] |
auto[0] |
2239302 |
1 |
|
|
T35 |
87 |
|
T38 |
555 |
|
T39 |
41202 |
| auto[1] |
auto[1] |
auto[1] |
327131 |
1 |
|
|
T35 |
5 |
|
T38 |
25 |
|
T39 |
5711 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7197731 |
1 |
|
|
T35 |
174 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5171516 |
1 |
|
|
T35 |
145 |
|
T38 |
1202 |
|
T39 |
103515 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11711405 |
1 |
|
|
T35 |
311 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
657842 |
1 |
|
|
T35 |
8 |
|
T38 |
36 |
|
T39 |
12128 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7212689 |
1 |
|
|
T35 |
168 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5156558 |
1 |
|
|
T35 |
151 |
|
T38 |
1118 |
|
T39 |
97375 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2239002 |
1 |
|
|
T35 |
82 |
|
T38 |
407 |
|
T39 |
41024 |
| auto[1] |
auto[0] |
auto[1] |
327257 |
1 |
|
|
T35 |
4 |
|
T38 |
17 |
|
T39 |
5752 |
| auto[1] |
auto[1] |
auto[0] |
2259714 |
1 |
|
|
T35 |
61 |
|
T38 |
675 |
|
T39 |
44223 |
| auto[1] |
auto[1] |
auto[1] |
330585 |
1 |
|
|
T35 |
4 |
|
T38 |
19 |
|
T39 |
6376 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7195506 |
1 |
|
|
T35 |
119 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5173741 |
1 |
|
|
T35 |
200 |
|
T38 |
898 |
|
T39 |
97855 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11717427 |
1 |
|
|
T35 |
309 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
651820 |
1 |
|
|
T35 |
10 |
|
T38 |
55 |
|
T39 |
12696 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7244487 |
1 |
|
|
T35 |
152 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5124760 |
1 |
|
|
T35 |
167 |
|
T38 |
1201 |
|
T39 |
101324 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2242656 |
1 |
|
|
T35 |
44 |
|
T38 |
568 |
|
T39 |
47175 |
| auto[1] |
auto[0] |
auto[1] |
327343 |
1 |
|
|
T35 |
5 |
|
T38 |
24 |
|
T39 |
6943 |
| auto[1] |
auto[1] |
auto[0] |
2230284 |
1 |
|
|
T35 |
113 |
|
T38 |
578 |
|
T39 |
41453 |
| auto[1] |
auto[1] |
auto[1] |
324477 |
1 |
|
|
T35 |
5 |
|
T38 |
31 |
|
T39 |
5753 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7230399 |
1 |
|
|
T35 |
206 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5138848 |
1 |
|
|
T35 |
113 |
|
T38 |
939 |
|
T39 |
94907 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11712217 |
1 |
|
|
T35 |
310 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
657030 |
1 |
|
|
T35 |
9 |
|
T38 |
39 |
|
T39 |
12272 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7219268 |
1 |
|
|
T35 |
150 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5149979 |
1 |
|
|
T35 |
169 |
|
T38 |
925 |
|
T39 |
97192 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2260555 |
1 |
|
|
T35 |
104 |
|
T38 |
375 |
|
T39 |
44159 |
| auto[1] |
auto[0] |
auto[1] |
331590 |
1 |
|
|
T35 |
6 |
|
T38 |
11 |
|
T39 |
6392 |
| auto[1] |
auto[1] |
auto[0] |
2232394 |
1 |
|
|
T35 |
56 |
|
T38 |
511 |
|
T39 |
40761 |
| auto[1] |
auto[1] |
auto[1] |
325440 |
1 |
|
|
T35 |
3 |
|
T38 |
28 |
|
T39 |
5880 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7238201 |
1 |
|
|
T35 |
190 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5131046 |
1 |
|
|
T35 |
129 |
|
T38 |
695 |
|
T39 |
99905 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11709767 |
1 |
|
|
T35 |
307 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
659480 |
1 |
|
|
T35 |
12 |
|
T38 |
42 |
|
T39 |
12290 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7197960 |
1 |
|
|
T35 |
159 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5171287 |
1 |
|
|
T35 |
160 |
|
T38 |
1068 |
|
T39 |
98309 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2266345 |
1 |
|
|
T35 |
94 |
|
T38 |
678 |
|
T39 |
43092 |
| auto[1] |
auto[0] |
auto[1] |
331336 |
1 |
|
|
T35 |
6 |
|
T38 |
33 |
|
T39 |
6156 |
| auto[1] |
auto[1] |
auto[0] |
2245462 |
1 |
|
|
T35 |
54 |
|
T38 |
348 |
|
T39 |
42927 |
| auto[1] |
auto[1] |
auto[1] |
328144 |
1 |
|
|
T35 |
6 |
|
T38 |
9 |
|
T39 |
6134 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7217822 |
1 |
|
|
T35 |
174 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5151425 |
1 |
|
|
T35 |
145 |
|
T38 |
854 |
|
T39 |
100684 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11711090 |
1 |
|
|
T35 |
309 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
658157 |
1 |
|
|
T35 |
10 |
|
T38 |
37 |
|
T39 |
12307 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7216344 |
1 |
|
|
T35 |
143 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5152903 |
1 |
|
|
T35 |
176 |
|
T38 |
904 |
|
T39 |
98603 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2253301 |
1 |
|
|
T35 |
89 |
|
T38 |
508 |
|
T39 |
43018 |
| auto[1] |
auto[0] |
auto[1] |
330410 |
1 |
|
|
T35 |
5 |
|
T38 |
13 |
|
T39 |
5995 |
| auto[1] |
auto[1] |
auto[0] |
2241445 |
1 |
|
|
T35 |
77 |
|
T38 |
359 |
|
T39 |
43278 |
| auto[1] |
auto[1] |
auto[1] |
327747 |
1 |
|
|
T35 |
5 |
|
T38 |
24 |
|
T39 |
6312 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7213209 |
1 |
|
|
T35 |
192 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5156038 |
1 |
|
|
T35 |
127 |
|
T38 |
1119 |
|
T39 |
96921 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11705373 |
1 |
|
|
T35 |
313 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
663874 |
1 |
|
|
T35 |
6 |
|
T38 |
31 |
|
T39 |
13186 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7181635 |
1 |
|
|
T35 |
164 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5187612 |
1 |
|
|
T35 |
155 |
|
T38 |
1026 |
|
T39 |
103682 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2257730 |
1 |
|
|
T35 |
97 |
|
T38 |
416 |
|
T39 |
47655 |
| auto[1] |
auto[0] |
auto[1] |
331172 |
1 |
|
|
T35 |
1 |
|
T38 |
15 |
|
T39 |
7124 |
| auto[1] |
auto[1] |
auto[0] |
2266008 |
1 |
|
|
T35 |
52 |
|
T38 |
579 |
|
T39 |
42841 |
| auto[1] |
auto[1] |
auto[1] |
332702 |
1 |
|
|
T35 |
5 |
|
T38 |
16 |
|
T39 |
6062 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7217055 |
1 |
|
|
T35 |
196 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5152192 |
1 |
|
|
T35 |
123 |
|
T38 |
999 |
|
T39 |
99801 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11710811 |
1 |
|
|
T35 |
310 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
658436 |
1 |
|
|
T35 |
9 |
|
T38 |
39 |
|
T39 |
12758 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7201824 |
1 |
|
|
T35 |
155 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5167423 |
1 |
|
|
T35 |
164 |
|
T38 |
979 |
|
T39 |
100853 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2262117 |
1 |
|
|
T35 |
96 |
|
T38 |
492 |
|
T39 |
43338 |
| auto[1] |
auto[0] |
auto[1] |
330256 |
1 |
|
|
T35 |
7 |
|
T38 |
24 |
|
T39 |
6244 |
| auto[1] |
auto[1] |
auto[0] |
2246870 |
1 |
|
|
T35 |
59 |
|
T38 |
448 |
|
T39 |
44757 |
| auto[1] |
auto[1] |
auto[1] |
328180 |
1 |
|
|
T35 |
2 |
|
T38 |
15 |
|
T39 |
6514 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7243196 |
1 |
|
|
T35 |
151 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5126051 |
1 |
|
|
T35 |
168 |
|
T38 |
960 |
|
T39 |
99356 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11714232 |
1 |
|
|
T35 |
312 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
655015 |
1 |
|
|
T35 |
7 |
|
T38 |
26 |
|
T39 |
12315 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7229127 |
1 |
|
|
T35 |
190 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5140120 |
1 |
|
|
T35 |
129 |
|
T38 |
944 |
|
T39 |
98897 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2271083 |
1 |
|
|
T35 |
61 |
|
T38 |
490 |
|
T39 |
44567 |
| auto[1] |
auto[0] |
auto[1] |
333065 |
1 |
|
|
T35 |
4 |
|
T38 |
12 |
|
T39 |
6326 |
| auto[1] |
auto[1] |
auto[0] |
2214022 |
1 |
|
|
T35 |
61 |
|
T38 |
428 |
|
T39 |
42015 |
| auto[1] |
auto[1] |
auto[1] |
321950 |
1 |
|
|
T35 |
3 |
|
T38 |
14 |
|
T39 |
5989 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7203932 |
1 |
|
|
T35 |
122 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5165315 |
1 |
|
|
T35 |
197 |
|
T38 |
888 |
|
T39 |
98417 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11710003 |
1 |
|
|
T35 |
305 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
659244 |
1 |
|
|
T35 |
14 |
|
T38 |
58 |
|
T39 |
12319 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7196803 |
1 |
|
|
T35 |
134 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5172444 |
1 |
|
|
T35 |
185 |
|
T38 |
1222 |
|
T39 |
97552 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2269929 |
1 |
|
|
T35 |
70 |
|
T38 |
667 |
|
T39 |
43670 |
| auto[1] |
auto[0] |
auto[1] |
331795 |
1 |
|
|
T35 |
4 |
|
T38 |
35 |
|
T39 |
6433 |
| auto[1] |
auto[1] |
auto[0] |
2243271 |
1 |
|
|
T35 |
101 |
|
T38 |
497 |
|
T39 |
41563 |
| auto[1] |
auto[1] |
auto[1] |
327449 |
1 |
|
|
T35 |
10 |
|
T38 |
23 |
|
T39 |
5886 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7200130 |
1 |
|
|
T35 |
199 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5169117 |
1 |
|
|
T35 |
120 |
|
T38 |
1074 |
|
T39 |
104495 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11710078 |
1 |
|
|
T35 |
301 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
659169 |
1 |
|
|
T35 |
18 |
|
T38 |
36 |
|
T39 |
12212 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7209635 |
1 |
|
|
T35 |
111 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5159612 |
1 |
|
|
T35 |
208 |
|
T38 |
1062 |
|
T39 |
96377 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2254199 |
1 |
|
|
T35 |
130 |
|
T38 |
419 |
|
T39 |
40510 |
| auto[1] |
auto[0] |
auto[1] |
330639 |
1 |
|
|
T35 |
10 |
|
T38 |
15 |
|
T39 |
5830 |
| auto[1] |
auto[1] |
auto[0] |
2246244 |
1 |
|
|
T35 |
60 |
|
T38 |
607 |
|
T39 |
43655 |
| auto[1] |
auto[1] |
auto[1] |
328530 |
1 |
|
|
T35 |
8 |
|
T38 |
21 |
|
T39 |
6382 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7206127 |
1 |
|
|
T35 |
182 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5163120 |
1 |
|
|
T35 |
137 |
|
T38 |
1047 |
|
T39 |
100874 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11713566 |
1 |
|
|
T35 |
310 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
655681 |
1 |
|
|
T35 |
9 |
|
T38 |
31 |
|
T39 |
11633 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7230434 |
1 |
|
|
T35 |
197 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5138813 |
1 |
|
|
T35 |
122 |
|
T38 |
952 |
|
T39 |
94294 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2236691 |
1 |
|
|
T35 |
55 |
|
T38 |
421 |
|
T39 |
40158 |
| auto[1] |
auto[0] |
auto[1] |
327416 |
1 |
|
|
T35 |
5 |
|
T38 |
13 |
|
T39 |
5596 |
| auto[1] |
auto[1] |
auto[0] |
2246441 |
1 |
|
|
T35 |
58 |
|
T38 |
500 |
|
T39 |
42503 |
| auto[1] |
auto[1] |
auto[1] |
328265 |
1 |
|
|
T35 |
4 |
|
T38 |
18 |
|
T39 |
6037 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7206621 |
1 |
|
|
T35 |
119 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5162626 |
1 |
|
|
T35 |
200 |
|
T38 |
994 |
|
T39 |
96602 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11711509 |
1 |
|
|
T35 |
308 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
657738 |
1 |
|
|
T35 |
11 |
|
T38 |
35 |
|
T39 |
12280 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7221639 |
1 |
|
|
T35 |
158 |
|
T36 |
326 |
|
T37 |
185 |
| auto[1] |
5147608 |
1 |
|
|
T35 |
161 |
|
T38 |
1042 |
|
T39 |
97864 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2240700 |
1 |
|
|
T35 |
38 |
|
T38 |
452 |
|
T39 |
43855 |
| auto[1] |
auto[0] |
auto[1] |
327480 |
1 |
|
|
T35 |
3 |
|
T38 |
18 |
|
T39 |
6238 |
| auto[1] |
auto[1] |
auto[0] |
2249170 |
1 |
|
|
T35 |
112 |
|
T38 |
555 |
|
T39 |
41729 |
| auto[1] |
auto[1] |
auto[1] |
330258 |
1 |
|
|
T35 |
8 |
|
T38 |
17 |
|
T39 |
6042 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |