Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html

T769 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1685833269 Jun 29 05:12:58 PM PDT 24 Jun 29 05:13:01 PM PDT 24 228741582 ps
T770 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3398686802 Jun 29 05:12:22 PM PDT 24 Jun 29 05:12:22 PM PDT 24 12651156 ps
T771 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3758033343 Jun 29 05:12:59 PM PDT 24 Jun 29 05:13:01 PM PDT 24 41300583 ps
T772 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4274204655 Jun 29 05:12:50 PM PDT 24 Jun 29 05:12:52 PM PDT 24 53230371 ps
T773 /workspace/coverage/cover_reg_top/36.gpio_intr_test.1294787500 Jun 29 05:13:21 PM PDT 24 Jun 29 05:13:21 PM PDT 24 42462715 ps
T94 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3092269964 Jun 29 05:13:07 PM PDT 24 Jun 29 05:13:08 PM PDT 24 35617795 ps
T774 /workspace/coverage/cover_reg_top/12.gpio_intr_test.197653127 Jun 29 05:13:00 PM PDT 24 Jun 29 05:13:01 PM PDT 24 14443961 ps
T775 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3453433596 Jun 29 05:13:01 PM PDT 24 Jun 29 05:13:02 PM PDT 24 19405822 ps
T776 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1725591089 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:51 PM PDT 24 18219166 ps
T777 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2918245151 Jun 29 05:12:32 PM PDT 24 Jun 29 05:12:33 PM PDT 24 31391978 ps
T778 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1343602875 Jun 29 05:13:08 PM PDT 24 Jun 29 05:13:10 PM PDT 24 27503353 ps
T779 /workspace/coverage/cover_reg_top/37.gpio_intr_test.728840228 Jun 29 05:13:16 PM PDT 24 Jun 29 05:13:17 PM PDT 24 15548389 ps
T780 /workspace/coverage/cover_reg_top/41.gpio_intr_test.4061542168 Jun 29 05:13:16 PM PDT 24 Jun 29 05:13:17 PM PDT 24 14950708 ps
T781 /workspace/coverage/cover_reg_top/17.gpio_intr_test.475307620 Jun 29 05:13:07 PM PDT 24 Jun 29 05:13:08 PM PDT 24 45808096 ps
T57 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1412714809 Jun 29 05:12:31 PM PDT 24 Jun 29 05:12:33 PM PDT 24 300466309 ps
T782 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3542851168 Jun 29 05:13:17 PM PDT 24 Jun 29 05:13:18 PM PDT 24 42920751 ps
T84 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1956365240 Jun 29 05:12:33 PM PDT 24 Jun 29 05:12:34 PM PDT 24 71151870 ps
T85 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1303842054 Jun 29 05:12:41 PM PDT 24 Jun 29 05:12:42 PM PDT 24 25348814 ps
T783 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2836856329 Jun 29 05:13:09 PM PDT 24 Jun 29 05:13:13 PM PDT 24 206556904 ps
T95 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2177952277 Jun 29 05:12:30 PM PDT 24 Jun 29 05:12:31 PM PDT 24 204720149 ps
T784 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2720659643 Jun 29 05:13:08 PM PDT 24 Jun 29 05:13:11 PM PDT 24 49878195 ps
T785 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2217615039 Jun 29 05:13:18 PM PDT 24 Jun 29 05:13:19 PM PDT 24 13991496 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1955746271 Jun 29 05:13:01 PM PDT 24 Jun 29 05:13:02 PM PDT 24 18745837 ps
T787 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1640463349 Jun 29 05:13:10 PM PDT 24 Jun 29 05:13:11 PM PDT 24 43879026 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.223647421 Jun 29 05:12:32 PM PDT 24 Jun 29 05:12:33 PM PDT 24 13797838 ps
T789 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2057165060 Jun 29 05:13:16 PM PDT 24 Jun 29 05:13:17 PM PDT 24 40990532 ps
T96 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2782631787 Jun 29 05:13:00 PM PDT 24 Jun 29 05:13:01 PM PDT 24 18369783 ps
T790 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1270857177 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:51 PM PDT 24 35620398 ps
T58 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2259187628 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:51 PM PDT 24 162843650 ps
T791 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3833231287 Jun 29 05:12:45 PM PDT 24 Jun 29 05:12:46 PM PDT 24 25299214 ps
T792 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3689671367 Jun 29 05:12:40 PM PDT 24 Jun 29 05:12:41 PM PDT 24 15584453 ps
T793 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3867961682 Jun 29 05:13:08 PM PDT 24 Jun 29 05:13:09 PM PDT 24 14884772 ps
T97 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.916449932 Jun 29 05:13:10 PM PDT 24 Jun 29 05:13:11 PM PDT 24 22121631 ps
T62 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3909300572 Jun 29 05:13:08 PM PDT 24 Jun 29 05:13:10 PM PDT 24 189619120 ps
T794 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1425683994 Jun 29 05:12:58 PM PDT 24 Jun 29 05:13:00 PM PDT 24 53617606 ps
T795 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2293694092 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:53 PM PDT 24 352191059 ps
T86 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.469990692 Jun 29 05:12:23 PM PDT 24 Jun 29 05:12:24 PM PDT 24 273276110 ps
T796 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1459943918 Jun 29 05:12:40 PM PDT 24 Jun 29 05:12:41 PM PDT 24 48373453 ps
T797 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2058305610 Jun 29 05:13:10 PM PDT 24 Jun 29 05:13:11 PM PDT 24 98801647 ps
T798 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2701924429 Jun 29 05:12:32 PM PDT 24 Jun 29 05:12:36 PM PDT 24 257401082 ps
T799 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1799598207 Jun 29 05:12:58 PM PDT 24 Jun 29 05:12:59 PM PDT 24 12281097 ps
T800 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1214227378 Jun 29 05:13:10 PM PDT 24 Jun 29 05:13:11 PM PDT 24 16100626 ps
T87 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1084433787 Jun 29 05:12:23 PM PDT 24 Jun 29 05:12:24 PM PDT 24 26039223 ps
T801 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2119375143 Jun 29 05:12:58 PM PDT 24 Jun 29 05:13:01 PM PDT 24 115030893 ps
T802 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3925962668 Jun 29 05:13:18 PM PDT 24 Jun 29 05:13:19 PM PDT 24 16026868 ps
T98 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4236102690 Jun 29 05:12:22 PM PDT 24 Jun 29 05:12:24 PM PDT 24 43119257 ps
T803 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.230270007 Jun 29 05:12:43 PM PDT 24 Jun 29 05:12:45 PM PDT 24 102103751 ps
T804 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1953762028 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:52 PM PDT 24 179157845 ps
T805 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2653815224 Jun 29 05:12:57 PM PDT 24 Jun 29 05:13:00 PM PDT 24 299861560 ps
T806 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3932076825 Jun 29 05:13:09 PM PDT 24 Jun 29 05:13:11 PM PDT 24 52008804 ps
T807 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3591861423 Jun 29 05:13:06 PM PDT 24 Jun 29 05:13:08 PM PDT 24 117767964 ps
T808 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.611475112 Jun 29 05:12:48 PM PDT 24 Jun 29 05:12:49 PM PDT 24 15142222 ps
T88 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3403682478 Jun 29 05:12:32 PM PDT 24 Jun 29 05:12:33 PM PDT 24 102508750 ps
T809 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2124046430 Jun 29 05:13:15 PM PDT 24 Jun 29 05:13:16 PM PDT 24 54007750 ps
T89 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1429159429 Jun 29 05:12:22 PM PDT 24 Jun 29 05:12:23 PM PDT 24 14605405 ps
T810 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3305465814 Jun 29 05:13:07 PM PDT 24 Jun 29 05:13:08 PM PDT 24 15922400 ps
T90 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2998478579 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:50 PM PDT 24 18456067 ps
T811 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2465571942 Jun 29 05:13:00 PM PDT 24 Jun 29 05:13:02 PM PDT 24 209978551 ps
T812 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2607287760 Jun 29 05:12:31 PM PDT 24 Jun 29 05:12:32 PM PDT 24 113567844 ps
T813 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1307645460 Jun 29 05:13:09 PM PDT 24 Jun 29 05:13:11 PM PDT 24 41429380 ps
T814 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2852815306 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:51 PM PDT 24 53580279 ps
T815 /workspace/coverage/cover_reg_top/30.gpio_intr_test.57884428 Jun 29 05:13:18 PM PDT 24 Jun 29 05:13:19 PM PDT 24 49500707 ps
T816 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2113365425 Jun 29 05:13:01 PM PDT 24 Jun 29 05:13:02 PM PDT 24 17204909 ps
T817 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1326890663 Jun 29 05:13:06 PM PDT 24 Jun 29 05:13:07 PM PDT 24 18189963 ps
T818 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3630690258 Jun 29 05:13:18 PM PDT 24 Jun 29 05:13:19 PM PDT 24 12597480 ps
T819 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1555451717 Jun 29 05:12:31 PM PDT 24 Jun 29 05:12:32 PM PDT 24 66034367 ps
T820 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.818144346 Jun 29 05:13:00 PM PDT 24 Jun 29 05:13:01 PM PDT 24 145705544 ps
T91 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2638956373 Jun 29 05:12:59 PM PDT 24 Jun 29 05:13:01 PM PDT 24 203462498 ps
T821 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2649247794 Jun 29 05:12:22 PM PDT 24 Jun 29 05:12:23 PM PDT 24 85221224 ps
T822 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.674505081 Jun 29 05:12:40 PM PDT 24 Jun 29 05:12:41 PM PDT 24 20175294 ps
T823 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.288473016 Jun 29 05:12:30 PM PDT 24 Jun 29 05:12:31 PM PDT 24 47711850 ps
T824 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1953404960 Jun 29 05:12:58 PM PDT 24 Jun 29 05:13:00 PM PDT 24 11447309 ps
T825 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.42952813 Jun 29 05:12:33 PM PDT 24 Jun 29 05:12:36 PM PDT 24 177556997 ps
T826 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.190601013 Jun 29 05:12:41 PM PDT 24 Jun 29 05:12:42 PM PDT 24 14680023 ps
T115 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2143647045 Jun 29 05:12:59 PM PDT 24 Jun 29 05:13:01 PM PDT 24 144670871 ps
T827 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2307767929 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:51 PM PDT 24 37073177 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2314180039 Jun 29 05:13:09 PM PDT 24 Jun 29 05:13:10 PM PDT 24 244179015 ps
T829 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3766859280 Jun 29 05:12:32 PM PDT 24 Jun 29 05:12:33 PM PDT 24 29584089 ps
T830 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2859567967 Jun 29 05:13:09 PM PDT 24 Jun 29 05:13:11 PM PDT 24 13531079 ps
T831 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3664135660 Jun 29 05:12:25 PM PDT 24 Jun 29 05:12:26 PM PDT 24 45852466 ps
T832 /workspace/coverage/cover_reg_top/5.gpio_intr_test.396031334 Jun 29 05:12:40 PM PDT 24 Jun 29 05:12:41 PM PDT 24 66664016 ps
T833 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3914445083 Jun 29 05:12:25 PM PDT 24 Jun 29 05:12:27 PM PDT 24 125631461 ps
T92 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2294938156 Jun 29 05:12:24 PM PDT 24 Jun 29 05:12:25 PM PDT 24 37146538 ps
T834 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3081484924 Jun 29 05:12:39 PM PDT 24 Jun 29 05:12:41 PM PDT 24 276578369 ps
T835 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.30684219 Jun 29 05:13:01 PM PDT 24 Jun 29 05:13:03 PM PDT 24 64173456 ps
T836 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3105368471 Jun 29 05:12:32 PM PDT 24 Jun 29 05:12:34 PM PDT 24 217857738 ps
T837 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2275120567 Jun 29 05:12:49 PM PDT 24 Jun 29 05:12:51 PM PDT 24 135628644 ps
T838 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2406619771 Jun 29 05:12:32 PM PDT 24 Jun 29 05:12:34 PM PDT 24 114418951 ps
T839 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3282814379 Jun 29 05:13:08 PM PDT 24 Jun 29 05:13:10 PM PDT 24 854950275 ps
T840 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3622747526 Jun 29 05:12:32 PM PDT 24 Jun 29 05:12:33 PM PDT 24 74426174 ps
T841 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4246996278 Jun 29 05:12:59 PM PDT 24 Jun 29 05:13:01 PM PDT 24 60354728 ps
T842 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2060444302 Jun 29 05:12:48 PM PDT 24 Jun 29 05:12:49 PM PDT 24 158398003 ps
T843 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3789928419 Jun 29 06:25:21 PM PDT 24 Jun 29 06:25:23 PM PDT 24 215896233 ps
T844 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2254530404 Jun 29 06:25:14 PM PDT 24 Jun 29 06:25:16 PM PDT 24 96701282 ps
T845 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233686347 Jun 29 06:25:01 PM PDT 24 Jun 29 06:25:03 PM PDT 24 144442956 ps
T846 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3250353053 Jun 29 06:25:13 PM PDT 24 Jun 29 06:25:14 PM PDT 24 25584575 ps
T847 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2017224338 Jun 29 06:25:21 PM PDT 24 Jun 29 06:25:23 PM PDT 24 68385016 ps
T848 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3854572670 Jun 29 06:25:40 PM PDT 24 Jun 29 06:25:42 PM PDT 24 146113585 ps
T849 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4271396070 Jun 29 06:24:52 PM PDT 24 Jun 29 06:24:54 PM PDT 24 154637378 ps
T850 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.658592579 Jun 29 06:24:53 PM PDT 24 Jun 29 06:24:54 PM PDT 24 224341036 ps
T851 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1198265410 Jun 29 06:25:12 PM PDT 24 Jun 29 06:25:13 PM PDT 24 117035816 ps
T852 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2327227388 Jun 29 06:25:13 PM PDT 24 Jun 29 06:25:14 PM PDT 24 221651960 ps
T853 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3529286955 Jun 29 06:25:05 PM PDT 24 Jun 29 06:25:07 PM PDT 24 99564141 ps
T854 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1815704646 Jun 29 06:25:15 PM PDT 24 Jun 29 06:25:17 PM PDT 24 70171360 ps
T855 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1986514354 Jun 29 06:24:50 PM PDT 24 Jun 29 06:24:52 PM PDT 24 52787806 ps
T856 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.748076138 Jun 29 06:25:06 PM PDT 24 Jun 29 06:25:07 PM PDT 24 105599692 ps
T857 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2696624864 Jun 29 06:24:59 PM PDT 24 Jun 29 06:25:01 PM PDT 24 71717921 ps
T858 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3605474285 Jun 29 06:25:01 PM PDT 24 Jun 29 06:25:03 PM PDT 24 46601618 ps
T859 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3399563937 Jun 29 06:25:11 PM PDT 24 Jun 29 06:25:13 PM PDT 24 54365504 ps
T860 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1926868452 Jun 29 06:25:23 PM PDT 24 Jun 29 06:25:24 PM PDT 24 239372864 ps
T861 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.122648117 Jun 29 06:25:26 PM PDT 24 Jun 29 06:25:28 PM PDT 24 88150372 ps
T862 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.608670529 Jun 29 06:24:50 PM PDT 24 Jun 29 06:24:51 PM PDT 24 33273212 ps
T863 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2027867007 Jun 29 06:25:07 PM PDT 24 Jun 29 06:25:09 PM PDT 24 162997421 ps
T864 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.423997207 Jun 29 06:25:13 PM PDT 24 Jun 29 06:25:15 PM PDT 24 50803972 ps
T865 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.459727106 Jun 29 06:25:26 PM PDT 24 Jun 29 06:25:27 PM PDT 24 83653305 ps
T866 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3977535999 Jun 29 06:24:57 PM PDT 24 Jun 29 06:24:59 PM PDT 24 57844643 ps
T867 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3122124283 Jun 29 06:24:51 PM PDT 24 Jun 29 06:24:53 PM PDT 24 85529947 ps
T868 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.642056691 Jun 29 06:25:12 PM PDT 24 Jun 29 06:25:14 PM PDT 24 157289409 ps
T869 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.877590996 Jun 29 06:24:50 PM PDT 24 Jun 29 06:24:52 PM PDT 24 134143369 ps
T870 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1347435445 Jun 29 06:25:05 PM PDT 24 Jun 29 06:25:07 PM PDT 24 295406488 ps
T871 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4209114616 Jun 29 06:24:58 PM PDT 24 Jun 29 06:25:00 PM PDT 24 252394558 ps
T872 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2173226908 Jun 29 06:25:07 PM PDT 24 Jun 29 06:25:08 PM PDT 24 43448050 ps
T873 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2235971087 Jun 29 06:24:55 PM PDT 24 Jun 29 06:24:57 PM PDT 24 46356640 ps
T874 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3378058262 Jun 29 06:25:22 PM PDT 24 Jun 29 06:25:23 PM PDT 24 162682616 ps
T875 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4237587500 Jun 29 06:24:58 PM PDT 24 Jun 29 06:24:59 PM PDT 24 98262346 ps
T876 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.946372002 Jun 29 06:24:52 PM PDT 24 Jun 29 06:24:54 PM PDT 24 239637663 ps
T877 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1018534409 Jun 29 06:25:14 PM PDT 24 Jun 29 06:25:16 PM PDT 24 64302524 ps
T878 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4282345235 Jun 29 06:24:58 PM PDT 24 Jun 29 06:24:59 PM PDT 24 65447315 ps
T879 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.229298347 Jun 29 06:25:07 PM PDT 24 Jun 29 06:25:08 PM PDT 24 84365418 ps
T880 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.143243087 Jun 29 06:24:53 PM PDT 24 Jun 29 06:24:54 PM PDT 24 19581035 ps
T881 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2802374801 Jun 29 06:25:08 PM PDT 24 Jun 29 06:25:10 PM PDT 24 68412159 ps
T882 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4190577404 Jun 29 06:25:11 PM PDT 24 Jun 29 06:25:12 PM PDT 24 62983687 ps
T883 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1622977651 Jun 29 06:25:06 PM PDT 24 Jun 29 06:25:08 PM PDT 24 53705200 ps
T884 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.384114593 Jun 29 06:25:14 PM PDT 24 Jun 29 06:25:16 PM PDT 24 141959232 ps
T885 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.481595537 Jun 29 06:24:59 PM PDT 24 Jun 29 06:25:01 PM PDT 24 94730795 ps
T886 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1735162753 Jun 29 06:25:00 PM PDT 24 Jun 29 06:25:01 PM PDT 24 54514185 ps
T887 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2759161779 Jun 29 06:24:51 PM PDT 24 Jun 29 06:24:52 PM PDT 24 88130537 ps
T888 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.850696866 Jun 29 06:25:14 PM PDT 24 Jun 29 06:25:15 PM PDT 24 61247231 ps
T889 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.778076788 Jun 29 06:25:16 PM PDT 24 Jun 29 06:25:17 PM PDT 24 497543522 ps
T890 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1392334283 Jun 29 06:25:13 PM PDT 24 Jun 29 06:25:15 PM PDT 24 157452934 ps
T891 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1832123866 Jun 29 06:24:57 PM PDT 24 Jun 29 06:24:59 PM PDT 24 72711406 ps
T892 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.654798801 Jun 29 06:25:14 PM PDT 24 Jun 29 06:25:16 PM PDT 24 263113597 ps
T893 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2696172146 Jun 29 06:25:04 PM PDT 24 Jun 29 06:25:06 PM PDT 24 1291651073 ps
T894 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.650978704 Jun 29 06:25:12 PM PDT 24 Jun 29 06:25:13 PM PDT 24 213673595 ps
T895 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3537299204 Jun 29 06:25:21 PM PDT 24 Jun 29 06:25:23 PM PDT 24 184200376 ps
T896 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2274742688 Jun 29 06:25:15 PM PDT 24 Jun 29 06:25:16 PM PDT 24 64074114 ps
T897 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1070905028 Jun 29 06:24:51 PM PDT 24 Jun 29 06:24:52 PM PDT 24 43138793 ps
T898 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.410072468 Jun 29 06:25:01 PM PDT 24 Jun 29 06:25:03 PM PDT 24 47077696 ps
T899 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.447174233 Jun 29 06:24:50 PM PDT 24 Jun 29 06:24:52 PM PDT 24 208711171 ps
T900 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1343651067 Jun 29 06:24:52 PM PDT 24 Jun 29 06:24:54 PM PDT 24 50974494 ps
T901 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2056456088 Jun 29 06:24:59 PM PDT 24 Jun 29 06:25:00 PM PDT 24 33738958 ps
T902 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.650980680 Jun 29 06:25:21 PM PDT 24 Jun 29 06:25:23 PM PDT 24 354806799 ps
T903 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2143356071 Jun 29 06:24:59 PM PDT 24 Jun 29 06:25:01 PM PDT 24 602542989 ps
T904 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3339386719 Jun 29 06:25:21 PM PDT 24 Jun 29 06:25:22 PM PDT 24 62486027 ps
T905 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.123451864 Jun 29 06:25:06 PM PDT 24 Jun 29 06:25:07 PM PDT 24 92814461 ps
T906 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1667320874 Jun 29 06:25:22 PM PDT 24 Jun 29 06:25:23 PM PDT 24 105455053 ps
T907 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4290751848 Jun 29 06:24:51 PM PDT 24 Jun 29 06:24:53 PM PDT 24 295723229 ps
T908 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3535915377 Jun 29 06:24:58 PM PDT 24 Jun 29 06:24:59 PM PDT 24 60604639 ps
T909 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3842356295 Jun 29 06:25:20 PM PDT 24 Jun 29 06:25:22 PM PDT 24 41365202 ps
T910 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4006881874 Jun 29 06:24:51 PM PDT 24 Jun 29 06:24:52 PM PDT 24 558492536 ps
T911 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2944924388 Jun 29 06:24:50 PM PDT 24 Jun 29 06:24:52 PM PDT 24 81715870 ps
T912 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1923782864 Jun 29 06:25:06 PM PDT 24 Jun 29 06:25:08 PM PDT 24 37962703 ps
T913 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.589960394 Jun 29 06:24:51 PM PDT 24 Jun 29 06:24:53 PM PDT 24 589564963 ps
T914 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3482423198 Jun 29 06:25:21 PM PDT 24 Jun 29 06:25:22 PM PDT 24 321518883 ps
T915 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3721116952 Jun 29 06:25:26 PM PDT 24 Jun 29 06:25:27 PM PDT 24 168608193 ps
T916 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.304110637 Jun 29 06:25:00 PM PDT 24 Jun 29 06:25:01 PM PDT 24 155658267 ps
T917 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2267729802 Jun 29 06:25:13 PM PDT 24 Jun 29 06:25:15 PM PDT 24 48888372 ps
T918 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466599096 Jun 29 06:24:58 PM PDT 24 Jun 29 06:25:00 PM PDT 24 32284968 ps
T919 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2678515684 Jun 29 06:25:24 PM PDT 24 Jun 29 06:25:25 PM PDT 24 149647056 ps
T920 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2071444712 Jun 29 06:25:20 PM PDT 24 Jun 29 06:25:22 PM PDT 24 79088514 ps
T921 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1531562127 Jun 29 06:24:58 PM PDT 24 Jun 29 06:25:00 PM PDT 24 96006254 ps
T922 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2474479480 Jun 29 06:25:14 PM PDT 24 Jun 29 06:25:16 PM PDT 24 295892532 ps
T923 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3560898156 Jun 29 06:25:12 PM PDT 24 Jun 29 06:25:13 PM PDT 24 84194088 ps
T924 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1522929958 Jun 29 06:25:04 PM PDT 24 Jun 29 06:25:06 PM PDT 24 177094401 ps
T925 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2001558456 Jun 29 06:25:18 PM PDT 24 Jun 29 06:25:19 PM PDT 24 29663067 ps
T926 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3246712212 Jun 29 06:25:21 PM PDT 24 Jun 29 06:25:23 PM PDT 24 200323697 ps
T927 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.911365001 Jun 29 06:24:54 PM PDT 24 Jun 29 06:24:55 PM PDT 24 68879975 ps
T928 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1708150751 Jun 29 06:25:14 PM PDT 24 Jun 29 06:25:16 PM PDT 24 109590770 ps
T929 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2574558729 Jun 29 06:25:12 PM PDT 24 Jun 29 06:25:14 PM PDT 24 66404870 ps
T930 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3217297436 Jun 29 06:24:51 PM PDT 24 Jun 29 06:24:53 PM PDT 24 53496117 ps
T931 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3093453388 Jun 29 06:25:25 PM PDT 24 Jun 29 06:25:26 PM PDT 24 62814847 ps
T932 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3603361390 Jun 29 06:25:08 PM PDT 24 Jun 29 06:25:09 PM PDT 24 202750979 ps
T933 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.398150382 Jun 29 06:25:05 PM PDT 24 Jun 29 06:25:07 PM PDT 24 331551117 ps
T934 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730268056 Jun 29 06:25:17 PM PDT 24 Jun 29 06:25:19 PM PDT 24 179067462 ps
T935 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2192043892 Jun 29 06:25:13 PM PDT 24 Jun 29 06:25:14 PM PDT 24 47660037 ps
T936 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.430257307 Jun 29 06:25:11 PM PDT 24 Jun 29 06:25:13 PM PDT 24 30827365 ps
T937 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1969480070 Jun 29 06:25:05 PM PDT 24 Jun 29 06:25:07 PM PDT 24 139594046 ps
T938 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2386387876 Jun 29 06:25:06 PM PDT 24 Jun 29 06:25:07 PM PDT 24 50550371 ps
T939 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1875391373 Jun 29 06:24:58 PM PDT 24 Jun 29 06:25:00 PM PDT 24 285013547 ps
T940 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.952395560 Jun 29 06:25:21 PM PDT 24 Jun 29 06:25:22 PM PDT 24 398551353 ps
T941 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3951389649 Jun 29 06:25:13 PM PDT 24 Jun 29 06:25:15 PM PDT 24 184642404 ps
T942 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3601349803 Jun 29 06:25:01 PM PDT 24 Jun 29 06:25:03 PM PDT 24 49891715 ps


Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.584613565
Short name T39
Test name
Test status
Simulation time 42897347549 ps
CPU time 600.75 seconds
Started Jun 29 05:14:30 PM PDT 24
Finished Jun 29 05:24:31 PM PDT 24
Peak memory 198900 kb
Host smart-5beac012-8b2b-4d6d-bbfb-42b013195a66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=584613565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.584613565
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2810057236
Short name T116
Test name
Test status
Simulation time 97072762 ps
CPU time 4.1 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:14:19 PM PDT 24
Peak memory 198768 kb
Host smart-1245dfff-8ca4-4364-be39-9b6a95ac64b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810057236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2810057236
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3515213778
Short name T40
Test name
Test status
Simulation time 64923491 ps
CPU time 1.15 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:46 PM PDT 24
Peak memory 196948 kb
Host smart-4029aeb8-d989-4d24-a0be-411d56adb84f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515213778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3515213778
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/0.gpio_sec_cm.3594136641
Short name T53
Test name
Test status
Simulation time 204111363 ps
CPU time 0.83 seconds
Started Jun 29 05:14:14 PM PDT 24
Finished Jun 29 05:14:16 PM PDT 24
Peak memory 214296 kb
Host smart-383297c2-c076-4e11-94cf-9be20750ebf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594136641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3594136641
Directory /workspace/0.gpio_sec_cm/latest


Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1991171750
Short name T78
Test name
Test status
Simulation time 14858195 ps
CPU time 0.65 seconds
Started Jun 29 05:12:57 PM PDT 24
Finished Jun 29 05:12:58 PM PDT 24
Peak memory 195640 kb
Host smart-049dd7e2-a910-4859-ae63-79f97b29f0e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991171750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1991171750
Directory /workspace/14.gpio_csr_rw/latest


Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2716784939
Short name T1
Test name
Test status
Simulation time 89726063 ps
CPU time 1.73 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:09 PM PDT 24
Peak memory 198648 kb
Host smart-63d91d55-3b89-43a3-a8c9-7771a274880a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716784939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2716784939
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2259187628
Short name T58
Test name
Test status
Simulation time 162843650 ps
CPU time 1.14 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 198752 kb
Host smart-2ed1b186-0b30-47cb-819a-502f69889f09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259187628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2259187628
Directory /workspace/7.gpio_tl_intg_err/latest


Test location /workspace/coverage/default/13.gpio_alert_test.1039010047
Short name T166
Test name
Test status
Simulation time 35830077 ps
CPU time 0.59 seconds
Started Jun 29 05:14:57 PM PDT 24
Finished Jun 29 05:14:58 PM PDT 24
Peak memory 194684 kb
Host smart-fb765aff-54a6-4425-ba7e-f79d968984b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039010047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1039010047
Directory /workspace/13.gpio_alert_test/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.691741032
Short name T60
Test name
Test status
Simulation time 234320636 ps
CPU time 1.52 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:34 PM PDT 24
Peak memory 198736 kb
Host smart-412efc93-879e-404d-9bd2-feff189c7f33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691741032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.691741032
Directory /workspace/1.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2294938156
Short name T92
Test name
Test status
Simulation time 37146538 ps
CPU time 0.61 seconds
Started Jun 29 05:12:24 PM PDT 24
Finished Jun 29 05:12:25 PM PDT 24
Peak memory 195600 kb
Host smart-ef5f3bc9-f2fe-42e0-8f96-e9989558e7e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294938156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2294938156
Directory /workspace/0.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4236102690
Short name T98
Test name
Test status
Simulation time 43119257 ps
CPU time 0.74 seconds
Started Jun 29 05:12:22 PM PDT 24
Finished Jun 29 05:12:24 PM PDT 24
Peak memory 196860 kb
Host smart-18a80589-fed2-485b-a87f-dbdd6fbd1c0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236102690 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.4236102690
Directory /workspace/0.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3495022974
Short name T50
Test name
Test status
Simulation time 131923414 ps
CPU time 1.44 seconds
Started Jun 29 05:13:01 PM PDT 24
Finished Jun 29 05:13:03 PM PDT 24
Peak memory 198724 kb
Host smart-2cfc4f18-34fe-4458-802e-3597575c3c2a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495022974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3495022974
Directory /workspace/12.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1084433787
Short name T87
Test name
Test status
Simulation time 26039223 ps
CPU time 0.77 seconds
Started Jun 29 05:12:23 PM PDT 24
Finished Jun 29 05:12:24 PM PDT 24
Peak memory 196112 kb
Host smart-bbe28f1c-79f3-4089-ad7d-adface5b8c17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084433787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1084433787
Directory /workspace/0.gpio_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2360897701
Short name T754
Test name
Test status
Simulation time 1089300958 ps
CPU time 3.34 seconds
Started Jun 29 05:12:22 PM PDT 24
Finished Jun 29 05:12:25 PM PDT 24
Peak memory 197880 kb
Host smart-ea396bc2-0560-47a9-9ce9-bb736c25fa86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360897701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2360897701
Directory /workspace/0.gpio_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2649247794
Short name T821
Test name
Test status
Simulation time 85221224 ps
CPU time 0.68 seconds
Started Jun 29 05:12:22 PM PDT 24
Finished Jun 29 05:12:23 PM PDT 24
Peak memory 196308 kb
Host smart-973c5934-c142-4b6f-be51-f2bd86935bb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649247794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2649247794
Directory /workspace/0.gpio_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2607287760
Short name T812
Test name
Test status
Simulation time 113567844 ps
CPU time 0.84 seconds
Started Jun 29 05:12:31 PM PDT 24
Finished Jun 29 05:12:32 PM PDT 24
Peak memory 198644 kb
Host smart-181e8f1a-426d-4d6d-92ed-99c4f865febb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607287760 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2607287760
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3398686802
Short name T770
Test name
Test status
Simulation time 12651156 ps
CPU time 0.6 seconds
Started Jun 29 05:12:22 PM PDT 24
Finished Jun 29 05:12:22 PM PDT 24
Peak memory 194432 kb
Host smart-484f5e67-defb-444a-ac7b-e2177992a928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398686802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3398686802
Directory /workspace/0.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.635647691
Short name T756
Test name
Test status
Simulation time 19715210 ps
CPU time 1.07 seconds
Started Jun 29 05:12:24 PM PDT 24
Finished Jun 29 05:12:26 PM PDT 24
Peak memory 198776 kb
Host smart-c5d3744b-1e36-418e-b119-193492dddb05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635647691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.635647691
Directory /workspace/0.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3914445083
Short name T833
Test name
Test status
Simulation time 125631461 ps
CPU time 1.45 seconds
Started Jun 29 05:12:25 PM PDT 24
Finished Jun 29 05:12:27 PM PDT 24
Peak memory 198680 kb
Host smart-a80666a2-975e-4bab-aaeb-4a97cd6abaa1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914445083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3914445083
Directory /workspace/0.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.469990692
Short name T86
Test name
Test status
Simulation time 273276110 ps
CPU time 0.79 seconds
Started Jun 29 05:12:23 PM PDT 24
Finished Jun 29 05:12:24 PM PDT 24
Peak memory 197356 kb
Host smart-34f34087-6c09-48fc-bc09-59b66ab8ecad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469990692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.469990692
Directory /workspace/1.gpio_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2701924429
Short name T798
Test name
Test status
Simulation time 257401082 ps
CPU time 3.42 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:36 PM PDT 24
Peak memory 197648 kb
Host smart-627bc1d8-ac5e-4d7b-8b5e-5bdccae183b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701924429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2701924429
Directory /workspace/1.gpio_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3403682478
Short name T88
Test name
Test status
Simulation time 102508750 ps
CPU time 0.62 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 195988 kb
Host smart-21068d75-3835-4f26-9b79-5a638f7d7a0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403682478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3403682478
Directory /workspace/1.gpio_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3622747526
Short name T840
Test name
Test status
Simulation time 74426174 ps
CPU time 0.88 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 198656 kb
Host smart-a6cdbe73-c90d-4b64-b947-767f5010a5cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622747526 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3622747526
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1429159429
Short name T89
Test name
Test status
Simulation time 14605405 ps
CPU time 0.61 seconds
Started Jun 29 05:12:22 PM PDT 24
Finished Jun 29 05:12:23 PM PDT 24
Peak memory 195504 kb
Host smart-de9924b7-825b-48ac-aeb2-4cd5fa6fcce7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429159429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1429159429
Directory /workspace/1.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3833231287
Short name T791
Test name
Test status
Simulation time 25299214 ps
CPU time 0.58 seconds
Started Jun 29 05:12:45 PM PDT 24
Finished Jun 29 05:12:46 PM PDT 24
Peak memory 194424 kb
Host smart-1a6ed8a6-a121-4997-b6e5-aaaa394b15a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833231287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3833231287
Directory /workspace/1.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3664135660
Short name T831
Test name
Test status
Simulation time 45852466 ps
CPU time 0.84 seconds
Started Jun 29 05:12:25 PM PDT 24
Finished Jun 29 05:12:26 PM PDT 24
Peak memory 197328 kb
Host smart-0d0b5b5f-cd9c-4834-8ced-e831feb842e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664135660 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3664135660
Directory /workspace/1.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.42952813
Short name T825
Test name
Test status
Simulation time 177556997 ps
CPU time 3.04 seconds
Started Jun 29 05:12:33 PM PDT 24
Finished Jun 29 05:12:36 PM PDT 24
Peak memory 198744 kb
Host smart-144ea030-c145-4223-bace-98c462bc1215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42952813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.42952813
Directory /workspace/1.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4067195274
Short name T766
Test name
Test status
Simulation time 30252790 ps
CPU time 1.27 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 198796 kb
Host smart-abbeb6e5-b606-4a57-a520-334a7100fef3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067195274 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.4067195274
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3068134863
Short name T111
Test name
Test status
Simulation time 14066584 ps
CPU time 0.62 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:00 PM PDT 24
Peak memory 195504 kb
Host smart-6c618809-cf12-49d0-b904-cf35f50ec8d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068134863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3068134863
Directory /workspace/10.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3758033343
Short name T771
Test name
Test status
Simulation time 41300583 ps
CPU time 0.57 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 194416 kb
Host smart-4f848a92-c13c-4965-9aba-cc87b94ec134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758033343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3758033343
Directory /workspace/10.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1916504066
Short name T79
Test name
Test status
Simulation time 20231038 ps
CPU time 0.67 seconds
Started Jun 29 05:12:57 PM PDT 24
Finished Jun 29 05:12:58 PM PDT 24
Peak memory 195404 kb
Host smart-b8089c38-12d0-4789-842d-71616e75798c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916504066 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1916504066
Directory /workspace/10.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.30684219
Short name T835
Test name
Test status
Simulation time 64173456 ps
CPU time 1.4 seconds
Started Jun 29 05:13:01 PM PDT 24
Finished Jun 29 05:13:03 PM PDT 24
Peak memory 198684 kb
Host smart-e2baf406-78a5-4907-8c73-5e60f83cac6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30684219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.30684219
Directory /workspace/10.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1425683994
Short name T794
Test name
Test status
Simulation time 53617606 ps
CPU time 0.88 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:13:00 PM PDT 24
Peak memory 197872 kb
Host smart-2b3b445a-d080-417f-b776-97c6d6a1a54c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425683994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1425683994
Directory /workspace/10.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3000981476
Short name T755
Test name
Test status
Simulation time 130553858 ps
CPU time 0.99 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 198604 kb
Host smart-6a9abc79-cc3c-4fcc-9bdf-785da877b9d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000981476 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3000981476
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1799598207
Short name T799
Test name
Test status
Simulation time 12281097 ps
CPU time 0.56 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:12:59 PM PDT 24
Peak memory 193944 kb
Host smart-7f84ca70-c8fd-4aca-858d-c085dbede737
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799598207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1799598207
Directory /workspace/11.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.127307501
Short name T759
Test name
Test status
Simulation time 21300819 ps
CPU time 0.6 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 194452 kb
Host smart-3d97e1c0-2806-4cfa-b0ee-acde3bc8fe0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127307501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.127307501
Directory /workspace/11.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.818144346
Short name T820
Test name
Test status
Simulation time 145705544 ps
CPU time 0.79 seconds
Started Jun 29 05:13:00 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 196832 kb
Host smart-ac923f41-1311-4d0b-ac74-ca67b0edb6e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818144346 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.818144346
Directory /workspace/11.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2653815224
Short name T805
Test name
Test status
Simulation time 299861560 ps
CPU time 2.48 seconds
Started Jun 29 05:12:57 PM PDT 24
Finished Jun 29 05:13:00 PM PDT 24
Peak memory 198792 kb
Host smart-8c267fed-0909-494b-b71a-a4e7684b9a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653815224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2653815224
Directory /workspace/11.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2143647045
Short name T115
Test name
Test status
Simulation time 144670871 ps
CPU time 1.21 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 198652 kb
Host smart-0a42d3b3-7bd0-4046-892b-60f7f9a14889
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143647045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2143647045
Directory /workspace/11.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3192910793
Short name T764
Test name
Test status
Simulation time 110566632 ps
CPU time 1.01 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:12:59 PM PDT 24
Peak memory 198548 kb
Host smart-be195427-9bce-4351-8aa4-125afdac534a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192910793 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3192910793
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2638956373
Short name T91
Test name
Test status
Simulation time 203462498 ps
CPU time 0.59 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 194360 kb
Host smart-27db44a3-05a6-4e4d-9c46-cae3a15232e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638956373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2638956373
Directory /workspace/12.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.197653127
Short name T774
Test name
Test status
Simulation time 14443961 ps
CPU time 0.64 seconds
Started Jun 29 05:13:00 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 194264 kb
Host smart-aeba91f6-c10b-473f-8452-10b06f5c0b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197653127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.197653127
Directory /workspace/12.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2178184229
Short name T93
Test name
Test status
Simulation time 149069339 ps
CPU time 0.84 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:12:59 PM PDT 24
Peak memory 196856 kb
Host smart-462b48c9-ceaf-4503-b99e-fe3b627aa8f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178184229 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2178184229
Directory /workspace/12.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3312985223
Short name T719
Test name
Test status
Simulation time 49422546 ps
CPU time 1.42 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 198748 kb
Host smart-47fdef78-49c0-4b75-8481-aeee42a88497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312985223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3312985223
Directory /workspace/12.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.572570043
Short name T768
Test name
Test status
Simulation time 17456491 ps
CPU time 0.66 seconds
Started Jun 29 05:12:56 PM PDT 24
Finished Jun 29 05:12:57 PM PDT 24
Peak memory 197116 kb
Host smart-254c2d9c-78d9-4e5e-95dd-f49bc89ecff3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572570043 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.572570043
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.127859867
Short name T751
Test name
Test status
Simulation time 28341021 ps
CPU time 0.6 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 195976 kb
Host smart-9bb51cab-d46b-4484-a727-9c2363478f99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127859867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.127859867
Directory /workspace/13.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1953404960
Short name T824
Test name
Test status
Simulation time 11447309 ps
CPU time 0.58 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:13:00 PM PDT 24
Peak memory 194300 kb
Host smart-d08a8ba8-7f74-4472-8e46-909c6040cd21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953404960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1953404960
Directory /workspace/13.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2113365425
Short name T816
Test name
Test status
Simulation time 17204909 ps
CPU time 0.69 seconds
Started Jun 29 05:13:01 PM PDT 24
Finished Jun 29 05:13:02 PM PDT 24
Peak memory 195632 kb
Host smart-a4ea7261-5cc7-4ade-961a-ffd44b201f44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113365425 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2113365425
Directory /workspace/13.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3399720869
Short name T761
Test name
Test status
Simulation time 109484381 ps
CPU time 2.36 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:13:02 PM PDT 24
Peak memory 198788 kb
Host smart-71109b12-1a26-484e-89ed-194b8331a27b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399720869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3399720869
Directory /workspace/13.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3105855631
Short name T52
Test name
Test status
Simulation time 237283082 ps
CPU time 1.45 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 198784 kb
Host smart-cb2b3b2a-d0fa-483d-a3dd-6f4ea94fa546
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105855631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3105855631
Directory /workspace/13.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1955746271
Short name T786
Test name
Test status
Simulation time 18745837 ps
CPU time 0.7 seconds
Started Jun 29 05:13:01 PM PDT 24
Finished Jun 29 05:13:02 PM PDT 24
Peak memory 198644 kb
Host smart-f7c4eebf-d068-4e19-9e83-612f6aae5474
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955746271 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1955746271
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1326890663
Short name T817
Test name
Test status
Simulation time 18189963 ps
CPU time 0.58 seconds
Started Jun 29 05:13:06 PM PDT 24
Finished Jun 29 05:13:07 PM PDT 24
Peak memory 194260 kb
Host smart-248f30c4-00d8-417c-905e-5ed52dc8f637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326890663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1326890663
Directory /workspace/14.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4246996278
Short name T841
Test name
Test status
Simulation time 60354728 ps
CPU time 0.63 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 195156 kb
Host smart-7a6fc63c-b25b-4922-ae13-5dca17dd1c29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246996278 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.4246996278
Directory /workspace/14.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2119375143
Short name T801
Test name
Test status
Simulation time 115030893 ps
CPU time 1.72 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 198788 kb
Host smart-8b21dc68-d5d3-4918-8906-d2f979f13462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119375143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2119375143
Directory /workspace/14.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.350293574
Short name T51
Test name
Test status
Simulation time 147584178 ps
CPU time 1.18 seconds
Started Jun 29 05:12:59 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 198756 kb
Host smart-85f3ca50-b5b8-4996-9fd9-1529b3bbdc2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350293574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.350293574
Directory /workspace/14.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3781578352
Short name T718
Test name
Test status
Simulation time 16443970 ps
CPU time 0.84 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 198768 kb
Host smart-f296cce4-9e5b-4eb4-9843-8d2c6b96b762
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781578352 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3781578352
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2859567967
Short name T830
Test name
Test status
Simulation time 13531079 ps
CPU time 0.6 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 194628 kb
Host smart-9319d0b6-76d1-42e8-99de-d06626996924
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859567967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2859567967
Directory /workspace/15.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3111027587
Short name T745
Test name
Test status
Simulation time 17681629 ps
CPU time 0.63 seconds
Started Jun 29 05:13:10 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 194380 kb
Host smart-5ace1724-a250-4688-a3a2-5f0dfff17ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111027587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3111027587
Directory /workspace/15.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2314180039
Short name T828
Test name
Test status
Simulation time 244179015 ps
CPU time 0.94 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 197068 kb
Host smart-fb82c3cc-92b6-48e6-bea8-5dcff7e65fe1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314180039 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2314180039
Directory /workspace/15.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.757406329
Short name T728
Test name
Test status
Simulation time 109631706 ps
CPU time 2.25 seconds
Started Jun 29 05:13:10 PM PDT 24
Finished Jun 29 05:13:13 PM PDT 24
Peak memory 198628 kb
Host smart-1d0b5cb1-efd2-446a-8bcf-5b98c4f663a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757406329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.757406329
Directory /workspace/15.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3909300572
Short name T62
Test name
Test status
Simulation time 189619120 ps
CPU time 1.19 seconds
Started Jun 29 05:13:08 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 198748 kb
Host smart-c7d8cea9-d272-40fa-b97b-157451a7f9cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909300572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3909300572
Directory /workspace/15.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3591861423
Short name T807
Test name
Test status
Simulation time 117767964 ps
CPU time 0.9 seconds
Started Jun 29 05:13:06 PM PDT 24
Finished Jun 29 05:13:08 PM PDT 24
Peak memory 198584 kb
Host smart-675fb051-a063-46f9-892b-3ddd87851dd5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591861423 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3591861423
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1214227378
Short name T800
Test name
Test status
Simulation time 16100626 ps
CPU time 0.61 seconds
Started Jun 29 05:13:10 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 195156 kb
Host smart-3fa08928-6434-44b1-837d-1389ac5744e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214227378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1214227378
Directory /workspace/16.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1229513516
Short name T765
Test name
Test status
Simulation time 46777788 ps
CPU time 0.61 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 194440 kb
Host smart-887c47e0-ccb8-4866-955a-e3ee8725b021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229513516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1229513516
Directory /workspace/16.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1606953859
Short name T76
Test name
Test status
Simulation time 66360314 ps
CPU time 0.89 seconds
Started Jun 29 05:13:07 PM PDT 24
Finished Jun 29 05:13:09 PM PDT 24
Peak memory 197708 kb
Host smart-cc081e42-b468-4510-8b37-d09413e628af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606953859 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1606953859
Directory /workspace/16.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2720659643
Short name T784
Test name
Test status
Simulation time 49878195 ps
CPU time 2.72 seconds
Started Jun 29 05:13:08 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 198720 kb
Host smart-fb69cc67-e3b8-4e9d-a287-4d8057e52bea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720659643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2720659643
Directory /workspace/16.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3282814379
Short name T839
Test name
Test status
Simulation time 854950275 ps
CPU time 1.15 seconds
Started Jun 29 05:13:08 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 198408 kb
Host smart-64880f03-9049-4e81-a688-7f89bb368a92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282814379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3282814379
Directory /workspace/16.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4073546951
Short name T749
Test name
Test status
Simulation time 68505389 ps
CPU time 0.84 seconds
Started Jun 29 05:13:08 PM PDT 24
Finished Jun 29 05:13:09 PM PDT 24
Peak memory 198628 kb
Host smart-16a4caca-9bf2-4c2e-8c1c-5e39c23769ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073546951 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.4073546951
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.147968844
Short name T109
Test name
Test status
Simulation time 51642955 ps
CPU time 0.61 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 194984 kb
Host smart-4062ff3e-5f18-4bc7-89a2-346b3b1ea124
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147968844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.147968844
Directory /workspace/17.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.475307620
Short name T781
Test name
Test status
Simulation time 45808096 ps
CPU time 0.59 seconds
Started Jun 29 05:13:07 PM PDT 24
Finished Jun 29 05:13:08 PM PDT 24
Peak memory 194504 kb
Host smart-8ff13cf2-58cd-43d0-b412-da3078c11408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475307620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.475307620
Directory /workspace/17.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3092269964
Short name T94
Test name
Test status
Simulation time 35617795 ps
CPU time 0.66 seconds
Started Jun 29 05:13:07 PM PDT 24
Finished Jun 29 05:13:08 PM PDT 24
Peak memory 196056 kb
Host smart-ff35330d-90fb-49aa-bd7c-547c906d75f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092269964 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3092269964
Directory /workspace/17.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3451195564
Short name T732
Test name
Test status
Simulation time 102186515 ps
CPU time 2.11 seconds
Started Jun 29 05:13:07 PM PDT 24
Finished Jun 29 05:13:09 PM PDT 24
Peak memory 198748 kb
Host smart-24828832-2b35-4626-aa1a-9a0af69f6791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451195564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3451195564
Directory /workspace/17.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3932076825
Short name T806
Test name
Test status
Simulation time 52008804 ps
CPU time 0.91 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 198440 kb
Host smart-db83966b-1f0a-4863-8e5a-76c8a497fec9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932076825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3932076825
Directory /workspace/17.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.115834612
Short name T730
Test name
Test status
Simulation time 106728390 ps
CPU time 0.82 seconds
Started Jun 29 05:13:07 PM PDT 24
Finished Jun 29 05:13:08 PM PDT 24
Peak memory 198588 kb
Host smart-afe3e286-519c-4642-9df5-70b56dfbe9f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115834612 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.115834612
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2599395047
Short name T83
Test name
Test status
Simulation time 18942283 ps
CPU time 0.63 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 196248 kb
Host smart-a958e508-6777-4db5-8d85-10db2e65907d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599395047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2599395047
Directory /workspace/18.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.164355191
Short name T717
Test name
Test status
Simulation time 43706688 ps
CPU time 0.63 seconds
Started Jun 29 05:13:07 PM PDT 24
Finished Jun 29 05:13:08 PM PDT 24
Peak memory 194572 kb
Host smart-f005acaf-a187-457d-9add-539f60db5e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164355191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.164355191
Directory /workspace/18.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2882404074
Short name T77
Test name
Test status
Simulation time 83309153 ps
CPU time 0.89 seconds
Started Jun 29 05:13:10 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 197184 kb
Host smart-b70f595f-9753-482b-96a4-bb307d872771
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882404074 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2882404074
Directory /workspace/18.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.4138257403
Short name T753
Test name
Test status
Simulation time 177608883 ps
CPU time 2.5 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:12 PM PDT 24
Peak memory 198748 kb
Host smart-6ab28fb2-40ad-49af-baa0-e405e4e0de4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138257403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.4138257403
Directory /workspace/18.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.629682914
Short name T61
Test name
Test status
Simulation time 155661076 ps
CPU time 1.22 seconds
Started Jun 29 05:13:11 PM PDT 24
Finished Jun 29 05:13:13 PM PDT 24
Peak memory 198744 kb
Host smart-b2d82271-ceca-452d-a983-36b4337c10bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629682914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.629682914
Directory /workspace/18.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1735238211
Short name T735
Test name
Test status
Simulation time 115834168 ps
CPU time 0.76 seconds
Started Jun 29 05:13:10 PM PDT 24
Finished Jun 29 05:13:12 PM PDT 24
Peak memory 198140 kb
Host smart-d289f9d3-070a-4ffb-80b0-bcee03ce95d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735238211 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1735238211
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3305465814
Short name T810
Test name
Test status
Simulation time 15922400 ps
CPU time 0.66 seconds
Started Jun 29 05:13:07 PM PDT 24
Finished Jun 29 05:13:08 PM PDT 24
Peak memory 196316 kb
Host smart-e85e20bb-05aa-4c4e-a7ad-583b3511bfca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305465814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3305465814
Directory /workspace/19.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3547240669
Short name T731
Test name
Test status
Simulation time 65360943 ps
CPU time 0.65 seconds
Started Jun 29 05:13:11 PM PDT 24
Finished Jun 29 05:13:12 PM PDT 24
Peak memory 194504 kb
Host smart-1ea2c83a-6da3-4204-9fc0-6497c2eeb393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547240669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3547240669
Directory /workspace/19.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.916449932
Short name T97
Test name
Test status
Simulation time 22121631 ps
CPU time 0.67 seconds
Started Jun 29 05:13:10 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 196040 kb
Host smart-2f56d281-40fc-4969-9d21-b7e8e4a13842
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916449932 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.916449932
Directory /workspace/19.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2836856329
Short name T783
Test name
Test status
Simulation time 206556904 ps
CPU time 2.9 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:13 PM PDT 24
Peak memory 198780 kb
Host smart-1a104dda-a73f-4804-bb19-4da681e115b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836856329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2836856329
Directory /workspace/19.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1307645460
Short name T813
Test name
Test status
Simulation time 41429380 ps
CPU time 0.89 seconds
Started Jun 29 05:13:09 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 198460 kb
Host smart-a12024b4-4b24-45e0-a78e-8f60d2ec4389
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307645460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1307645460
Directory /workspace/19.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1956365240
Short name T84
Test name
Test status
Simulation time 71151870 ps
CPU time 0.66 seconds
Started Jun 29 05:12:33 PM PDT 24
Finished Jun 29 05:12:34 PM PDT 24
Peak memory 195128 kb
Host smart-3377365c-d9eb-4dd7-a44b-3dd8babf06a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956365240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1956365240
Directory /workspace/2.gpio_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2481459970
Short name T112
Test name
Test status
Simulation time 327448012 ps
CPU time 2.4 seconds
Started Jun 29 05:12:34 PM PDT 24
Finished Jun 29 05:12:37 PM PDT 24
Peak memory 197964 kb
Host smart-ead6cb8d-d192-4e31-a43b-bbe39bb18467
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481459970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2481459970
Directory /workspace/2.gpio_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.65584258
Short name T110
Test name
Test status
Simulation time 38181566 ps
CPU time 0.66 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 195096 kb
Host smart-a545e074-6c77-4b6b-a7b3-99dec9a7fc5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65584258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.65584258
Directory /workspace/2.gpio_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.219081402
Short name T722
Test name
Test status
Simulation time 151475277 ps
CPU time 0.86 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 198560 kb
Host smart-1537ef09-724e-4868-a464-3824e2f89979
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219081402 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.219081402
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.223647421
Short name T788
Test name
Test status
Simulation time 13797838 ps
CPU time 0.62 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 195816 kb
Host smart-24eb900e-fc6e-405f-b4e2-25ae88b55c24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223647421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.223647421
Directory /workspace/2.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2918245151
Short name T777
Test name
Test status
Simulation time 31391978 ps
CPU time 0.65 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 195184 kb
Host smart-35a52a47-524b-4ae8-812c-2a5b99e2bfd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918245151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2918245151
Directory /workspace/2.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2177952277
Short name T95
Test name
Test status
Simulation time 204720149 ps
CPU time 0.63 seconds
Started Jun 29 05:12:30 PM PDT 24
Finished Jun 29 05:12:31 PM PDT 24
Peak memory 195128 kb
Host smart-0f117fc6-7ebe-4ce7-ae0d-0f2b3fedfd01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177952277 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2177952277
Directory /workspace/2.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.230270007
Short name T803
Test name
Test status
Simulation time 102103751 ps
CPU time 1.76 seconds
Started Jun 29 05:12:43 PM PDT 24
Finished Jun 29 05:12:45 PM PDT 24
Peak memory 198724 kb
Host smart-46d3020c-de98-4fc8-b2f0-504df8289878
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230270007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.230270007
Directory /workspace/2.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3105368471
Short name T836
Test name
Test status
Simulation time 217857738 ps
CPU time 1.52 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:34 PM PDT 24
Peak memory 198724 kb
Host smart-dc3b3bd0-bdfb-4244-aa1d-aa5c8173b773
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105368471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3105368471
Directory /workspace/2.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2058305610
Short name T797
Test name
Test status
Simulation time 98801647 ps
CPU time 0.62 seconds
Started Jun 29 05:13:10 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 195132 kb
Host smart-8a971cf1-1272-46d5-b144-ee4497d521a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058305610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2058305610
Directory /workspace/20.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3867961682
Short name T793
Test name
Test status
Simulation time 14884772 ps
CPU time 0.64 seconds
Started Jun 29 05:13:08 PM PDT 24
Finished Jun 29 05:13:09 PM PDT 24
Peak memory 195120 kb
Host smart-2d220385-f9e4-44ad-bd1d-57903df19b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867961682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3867961682
Directory /workspace/21.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1640463349
Short name T787
Test name
Test status
Simulation time 43879026 ps
CPU time 0.62 seconds
Started Jun 29 05:13:10 PM PDT 24
Finished Jun 29 05:13:11 PM PDT 24
Peak memory 195100 kb
Host smart-b0413953-513b-42cb-a6e6-1357c10a54ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640463349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1640463349
Directory /workspace/22.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1118473833
Short name T746
Test name
Test status
Simulation time 14495246 ps
CPU time 0.64 seconds
Started Jun 29 05:13:08 PM PDT 24
Finished Jun 29 05:13:09 PM PDT 24
Peak memory 194348 kb
Host smart-5576fb61-966b-46db-acd4-06fff99a6e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118473833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1118473833
Directory /workspace/23.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1343602875
Short name T778
Test name
Test status
Simulation time 27503353 ps
CPU time 0.63 seconds
Started Jun 29 05:13:08 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 194484 kb
Host smart-d60ad3fa-32eb-4f88-b99b-6506cafc8dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343602875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1343602875
Directory /workspace/24.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2943801285
Short name T739
Test name
Test status
Simulation time 44543313 ps
CPU time 0.64 seconds
Started Jun 29 05:13:08 PM PDT 24
Finished Jun 29 05:13:10 PM PDT 24
Peak memory 195080 kb
Host smart-1ff81163-c711-487f-99b1-baa1ea364b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943801285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2943801285
Directory /workspace/25.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.659103941
Short name T725
Test name
Test status
Simulation time 20854667 ps
CPU time 0.64 seconds
Started Jun 29 05:13:20 PM PDT 24
Finished Jun 29 05:13:21 PM PDT 24
Peak memory 194684 kb
Host smart-ca5c88de-a08a-4ad6-bad9-96c4629d43c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659103941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.659103941
Directory /workspace/26.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4184094611
Short name T752
Test name
Test status
Simulation time 11283064 ps
CPU time 0.61 seconds
Started Jun 29 05:13:17 PM PDT 24
Finished Jun 29 05:13:18 PM PDT 24
Peak memory 194412 kb
Host smart-64c140a4-268b-4b39-ab5a-f2ea1fe1ccba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184094611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4184094611
Directory /workspace/27.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2199070095
Short name T763
Test name
Test status
Simulation time 54699277 ps
CPU time 0.61 seconds
Started Jun 29 05:13:19 PM PDT 24
Finished Jun 29 05:13:20 PM PDT 24
Peak memory 194444 kb
Host smart-cb0c0158-c72c-411e-a7ee-a2d1f01281aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199070095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2199070095
Directory /workspace/28.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3542851168
Short name T782
Test name
Test status
Simulation time 42920751 ps
CPU time 0.59 seconds
Started Jun 29 05:13:17 PM PDT 24
Finished Jun 29 05:13:18 PM PDT 24
Peak memory 194480 kb
Host smart-66dd445b-7cda-4c3c-89f2-e6a618faf85a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542851168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3542851168
Directory /workspace/29.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1555451717
Short name T819
Test name
Test status
Simulation time 66034367 ps
CPU time 0.66 seconds
Started Jun 29 05:12:31 PM PDT 24
Finished Jun 29 05:12:32 PM PDT 24
Peak memory 195604 kb
Host smart-f3c5d2ee-9746-4df1-a864-b61d7d23daed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555451717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1555451717
Directory /workspace/3.gpio_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2307767929
Short name T827
Test name
Test status
Simulation time 37073177 ps
CPU time 1.33 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 197468 kb
Host smart-ef486446-fb4d-46e1-a2e0-104cbad9665a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307767929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2307767929
Directory /workspace/3.gpio_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3689671367
Short name T792
Test name
Test status
Simulation time 15584453 ps
CPU time 0.66 seconds
Started Jun 29 05:12:40 PM PDT 24
Finished Jun 29 05:12:41 PM PDT 24
Peak memory 195528 kb
Host smart-c9c368f4-c2c7-4012-9eff-b6dfd1d7d6e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689671367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3689671367
Directory /workspace/3.gpio_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2406619771
Short name T838
Test name
Test status
Simulation time 114418951 ps
CPU time 0.89 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:34 PM PDT 24
Peak memory 198652 kb
Host smart-55d29b1d-8e84-4779-9180-b898b141f269
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406619771 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2406619771
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3766859280
Short name T829
Test name
Test status
Simulation time 29584089 ps
CPU time 0.65 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 195816 kb
Host smart-8f912870-d66b-4e85-b67c-936b16a3999e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766859280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3766859280
Directory /workspace/3.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.547188219
Short name T733
Test name
Test status
Simulation time 40512372 ps
CPU time 0.6 seconds
Started Jun 29 05:12:31 PM PDT 24
Finished Jun 29 05:12:32 PM PDT 24
Peak memory 194436 kb
Host smart-d56eb980-c4c7-4cba-a69b-46515cce19ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547188219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.547188219
Directory /workspace/3.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.288473016
Short name T823
Test name
Test status
Simulation time 47711850 ps
CPU time 0.75 seconds
Started Jun 29 05:12:30 PM PDT 24
Finished Jun 29 05:12:31 PM PDT 24
Peak memory 197464 kb
Host smart-0c0f8925-6b49-44eb-b493-1e9e810cf67b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288473016 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.288473016
Directory /workspace/3.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.287350670
Short name T760
Test name
Test status
Simulation time 1622734584 ps
CPU time 2.38 seconds
Started Jun 29 05:12:32 PM PDT 24
Finished Jun 29 05:12:35 PM PDT 24
Peak memory 198712 kb
Host smart-7374cc7e-5fd0-40f8-a00d-add3528d5c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287350670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.287350670
Directory /workspace/3.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1412714809
Short name T57
Test name
Test status
Simulation time 300466309 ps
CPU time 1.16 seconds
Started Jun 29 05:12:31 PM PDT 24
Finished Jun 29 05:12:33 PM PDT 24
Peak memory 198768 kb
Host smart-0726b82f-ed68-4e1d-89ff-76218211d9e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412714809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1412714809
Directory /workspace/3.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.57884428
Short name T815
Test name
Test status
Simulation time 49500707 ps
CPU time 0.61 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 194468 kb
Host smart-a2cb011d-1b8c-4392-9242-3186f362f72a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57884428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.57884428
Directory /workspace/30.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2057165060
Short name T789
Test name
Test status
Simulation time 40990532 ps
CPU time 0.6 seconds
Started Jun 29 05:13:16 PM PDT 24
Finished Jun 29 05:13:17 PM PDT 24
Peak memory 195084 kb
Host smart-653591bb-24b8-495a-a2ee-0b67bb6dd046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057165060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2057165060
Directory /workspace/31.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2217615039
Short name T785
Test name
Test status
Simulation time 13991496 ps
CPU time 0.64 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 194480 kb
Host smart-e7bed048-7e60-4737-a280-daaa80f00f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217615039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2217615039
Directory /workspace/32.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1687319662
Short name T742
Test name
Test status
Simulation time 61424656 ps
CPU time 0.59 seconds
Started Jun 29 05:13:14 PM PDT 24
Finished Jun 29 05:13:15 PM PDT 24
Peak memory 194524 kb
Host smart-d1d48602-e893-45ab-81a6-ef281f2e82ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687319662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1687319662
Directory /workspace/33.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4112182102
Short name T736
Test name
Test status
Simulation time 31016808 ps
CPU time 0.61 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 194444 kb
Host smart-da9aa1dc-5d79-4142-a44e-10ae5c4f33c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112182102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4112182102
Directory /workspace/34.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3925962668
Short name T802
Test name
Test status
Simulation time 16026868 ps
CPU time 0.6 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 194484 kb
Host smart-86788ce0-2487-48c8-a403-c0182f8ec89f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925962668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3925962668
Directory /workspace/35.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1294787500
Short name T773
Test name
Test status
Simulation time 42462715 ps
CPU time 0.6 seconds
Started Jun 29 05:13:21 PM PDT 24
Finished Jun 29 05:13:21 PM PDT 24
Peak memory 195080 kb
Host smart-b6eb7415-6af0-48ee-bf26-2f621bef8491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294787500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1294787500
Directory /workspace/36.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.728840228
Short name T779
Test name
Test status
Simulation time 15548389 ps
CPU time 0.62 seconds
Started Jun 29 05:13:16 PM PDT 24
Finished Jun 29 05:13:17 PM PDT 24
Peak memory 194492 kb
Host smart-7f0ff049-bff9-4de0-88a0-553f2ea8463c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728840228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.728840228
Directory /workspace/37.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3630690258
Short name T818
Test name
Test status
Simulation time 12597480 ps
CPU time 0.64 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 195188 kb
Host smart-ad489911-fb5b-4f65-8630-ef467dd59545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630690258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3630690258
Directory /workspace/38.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3877795091
Short name T747
Test name
Test status
Simulation time 59223320 ps
CPU time 0.61 seconds
Started Jun 29 05:13:17 PM PDT 24
Finished Jun 29 05:13:18 PM PDT 24
Peak memory 195040 kb
Host smart-c8576177-8a73-4995-9360-2464bd0df572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877795091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3877795091
Directory /workspace/39.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2998478579
Short name T90
Test name
Test status
Simulation time 18456067 ps
CPU time 0.76 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:50 PM PDT 24
Peak memory 196652 kb
Host smart-8550f6ba-4acc-4ed3-8ed2-10b75f8964dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998478579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2998478579
Directory /workspace/4.gpio_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1953762028
Short name T804
Test name
Test status
Simulation time 179157845 ps
CPU time 2.3 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:52 PM PDT 24
Peak memory 197308 kb
Host smart-31492126-a54e-4022-b123-1ead0ab9581f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953762028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1953762028
Directory /workspace/4.gpio_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1746108208
Short name T113
Test name
Test status
Simulation time 23831961 ps
CPU time 0.63 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:50 PM PDT 24
Peak memory 195200 kb
Host smart-149abf3e-33ad-4a3b-8264-16bc208227b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746108208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1746108208
Directory /workspace/4.gpio_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.373388425
Short name T720
Test name
Test status
Simulation time 68229222 ps
CPU time 0.95 seconds
Started Jun 29 05:12:39 PM PDT 24
Finished Jun 29 05:12:41 PM PDT 24
Peak memory 198600 kb
Host smart-05d510a4-e3de-4222-ae3a-fa41cf85a6f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373388425 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.373388425
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1303842054
Short name T85
Test name
Test status
Simulation time 25348814 ps
CPU time 0.59 seconds
Started Jun 29 05:12:41 PM PDT 24
Finished Jun 29 05:12:42 PM PDT 24
Peak memory 194716 kb
Host smart-5cf2b40b-1fd7-4c05-be58-ce1be9c7fd6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303842054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1303842054
Directory /workspace/4.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1459943918
Short name T796
Test name
Test status
Simulation time 48373453 ps
CPU time 0.57 seconds
Started Jun 29 05:12:40 PM PDT 24
Finished Jun 29 05:12:41 PM PDT 24
Peak memory 194456 kb
Host smart-9319c41f-15e7-4a96-8036-434d9346c88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459943918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1459943918
Directory /workspace/4.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.674505081
Short name T822
Test name
Test status
Simulation time 20175294 ps
CPU time 0.64 seconds
Started Jun 29 05:12:40 PM PDT 24
Finished Jun 29 05:12:41 PM PDT 24
Peak memory 196052 kb
Host smart-12b2a90e-477c-4090-b904-e0242e014415
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674505081 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.674505081
Directory /workspace/4.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3595787528
Short name T740
Test name
Test status
Simulation time 127117661 ps
CPU time 2.73 seconds
Started Jun 29 05:12:40 PM PDT 24
Finished Jun 29 05:12:43 PM PDT 24
Peak memory 198616 kb
Host smart-b41d5e8c-3aa9-48f2-901b-59f8a296c081
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595787528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3595787528
Directory /workspace/4.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.677528545
Short name T56
Test name
Test status
Simulation time 255145762 ps
CPU time 1.13 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 198268 kb
Host smart-8829bc50-35f4-43f7-88bf-c1a5706ae0f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677528545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.677528545
Directory /workspace/4.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3594553638
Short name T734
Test name
Test status
Simulation time 18337625 ps
CPU time 0.62 seconds
Started Jun 29 05:13:16 PM PDT 24
Finished Jun 29 05:13:17 PM PDT 24
Peak memory 194488 kb
Host smart-9839c977-812d-42cb-b69f-1167f72d7890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594553638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3594553638
Directory /workspace/40.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.4061542168
Short name T780
Test name
Test status
Simulation time 14950708 ps
CPU time 0.63 seconds
Started Jun 29 05:13:16 PM PDT 24
Finished Jun 29 05:13:17 PM PDT 24
Peak memory 194292 kb
Host smart-d1777d78-2dc2-459a-bd67-db32dc21e554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061542168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.4061542168
Directory /workspace/41.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.889128853
Short name T726
Test name
Test status
Simulation time 34947380 ps
CPU time 0.59 seconds
Started Jun 29 05:13:19 PM PDT 24
Finished Jun 29 05:13:20 PM PDT 24
Peak memory 194400 kb
Host smart-426a83d7-bfdf-4835-ab71-2f9d57876004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889128853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.889128853
Directory /workspace/42.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2561990916
Short name T729
Test name
Test status
Simulation time 11547454 ps
CPU time 0.61 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 195128 kb
Host smart-de9b771f-cbc0-4b61-abde-b0caf5ec1c45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561990916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2561990916
Directory /workspace/43.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1020719432
Short name T723
Test name
Test status
Simulation time 14508895 ps
CPU time 0.61 seconds
Started Jun 29 05:13:19 PM PDT 24
Finished Jun 29 05:13:20 PM PDT 24
Peak memory 194440 kb
Host smart-dbde5ef8-0d64-4e5e-ac3b-d173d396775e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020719432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1020719432
Directory /workspace/44.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1076183609
Short name T762
Test name
Test status
Simulation time 142491771 ps
CPU time 0.6 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 194444 kb
Host smart-e8287e6c-3b14-4783-8fd3-0ca8ce69c927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076183609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1076183609
Directory /workspace/45.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2124046430
Short name T809
Test name
Test status
Simulation time 54007750 ps
CPU time 0.59 seconds
Started Jun 29 05:13:15 PM PDT 24
Finished Jun 29 05:13:16 PM PDT 24
Peak memory 194392 kb
Host smart-9c4c613b-b547-47a0-9ee9-a3ae793d22bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124046430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2124046430
Directory /workspace/46.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3056710416
Short name T757
Test name
Test status
Simulation time 55028848 ps
CPU time 0.62 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 194512 kb
Host smart-1ff3afaa-cbfe-4ba2-9963-a49e7fbacfc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056710416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3056710416
Directory /workspace/47.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2668124905
Short name T727
Test name
Test status
Simulation time 13926788 ps
CPU time 0.64 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:19 PM PDT 24
Peak memory 194332 kb
Host smart-93c897fd-46d8-440b-b2ad-78decf0b61d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668124905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2668124905
Directory /workspace/48.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.4263185438
Short name T741
Test name
Test status
Simulation time 22897581 ps
CPU time 0.62 seconds
Started Jun 29 05:13:18 PM PDT 24
Finished Jun 29 05:13:20 PM PDT 24
Peak memory 194944 kb
Host smart-72c5168c-f254-48b2-9389-66743e1835b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263185438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.4263185438
Directory /workspace/49.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2275120567
Short name T837
Test name
Test status
Simulation time 135628644 ps
CPU time 1.19 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 194668 kb
Host smart-6801798f-06cc-46e4-8490-3498b311a778
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275120567 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2275120567
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1617010351
Short name T82
Test name
Test status
Simulation time 21670281 ps
CPU time 0.6 seconds
Started Jun 29 05:12:41 PM PDT 24
Finished Jun 29 05:12:42 PM PDT 24
Peak memory 194596 kb
Host smart-f4e7d3eb-ce0e-4bbb-9937-6d6f5c568f82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617010351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1617010351
Directory /workspace/5.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.396031334
Short name T832
Test name
Test status
Simulation time 66664016 ps
CPU time 0.63 seconds
Started Jun 29 05:12:40 PM PDT 24
Finished Jun 29 05:12:41 PM PDT 24
Peak memory 195088 kb
Host smart-f6e10753-b748-4c0a-8a12-7b60897bc302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396031334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.396031334
Directory /workspace/5.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.190601013
Short name T826
Test name
Test status
Simulation time 14680023 ps
CPU time 0.68 seconds
Started Jun 29 05:12:41 PM PDT 24
Finished Jun 29 05:12:42 PM PDT 24
Peak memory 196000 kb
Host smart-bdcf8add-ff31-4999-a07f-02ec192cbfa0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190601013 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.190601013
Directory /workspace/5.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3162540333
Short name T744
Test name
Test status
Simulation time 180491964 ps
CPU time 1.16 seconds
Started Jun 29 05:12:41 PM PDT 24
Finished Jun 29 05:12:43 PM PDT 24
Peak memory 198756 kb
Host smart-c594811d-bfdc-42fc-929a-9d5fb3210225
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162540333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3162540333
Directory /workspace/5.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3081484924
Short name T834
Test name
Test status
Simulation time 276578369 ps
CPU time 0.88 seconds
Started Jun 29 05:12:39 PM PDT 24
Finished Jun 29 05:12:41 PM PDT 24
Peak memory 197568 kb
Host smart-b75355e7-482c-4d1f-96f8-f35c2533c41c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081484924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3081484924
Directory /workspace/5.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2852815306
Short name T814
Test name
Test status
Simulation time 53580279 ps
CPU time 0.79 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 198656 kb
Host smart-26c75c6f-eec9-40a5-8ecc-c588e90e672c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852815306 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2852815306
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2992065733
Short name T748
Test name
Test status
Simulation time 38598886 ps
CPU time 0.62 seconds
Started Jun 29 05:12:48 PM PDT 24
Finished Jun 29 05:12:49 PM PDT 24
Peak memory 195420 kb
Host smart-c255a31f-8f78-4901-b54e-5cd5409da991
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992065733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2992065733
Directory /workspace/6.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1739411797
Short name T738
Test name
Test status
Simulation time 27732120 ps
CPU time 0.62 seconds
Started Jun 29 05:12:48 PM PDT 24
Finished Jun 29 05:12:49 PM PDT 24
Peak memory 194464 kb
Host smart-38fee73e-8b1b-4729-9e0a-cf1fc4e1627b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739411797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1739411797
Directory /workspace/6.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.611475112
Short name T808
Test name
Test status
Simulation time 15142222 ps
CPU time 0.68 seconds
Started Jun 29 05:12:48 PM PDT 24
Finished Jun 29 05:12:49 PM PDT 24
Peak memory 195308 kb
Host smart-7c228ce8-6c3a-49a2-ac8f-19d30567346c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611475112 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.611475112
Directory /workspace/6.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1270857177
Short name T790
Test name
Test status
Simulation time 35620398 ps
CPU time 1.09 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 198576 kb
Host smart-ab1bc0ac-c4c2-4c8b-b594-f83991faef61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270857177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1270857177
Directory /workspace/6.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3879042286
Short name T758
Test name
Test status
Simulation time 47588802 ps
CPU time 0.88 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 197712 kb
Host smart-323ec4c4-888f-4cb6-adcc-e8096c1a43ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879042286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3879042286
Directory /workspace/6.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1177313150
Short name T724
Test name
Test status
Simulation time 189565357 ps
CPU time 0.9 seconds
Started Jun 29 05:12:50 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 198652 kb
Host smart-6562dd43-e6bc-477c-a873-0439471d1e30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177313150 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1177313150
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.637251667
Short name T81
Test name
Test status
Simulation time 33266335 ps
CPU time 0.62 seconds
Started Jun 29 05:12:48 PM PDT 24
Finished Jun 29 05:12:49 PM PDT 24
Peak memory 195888 kb
Host smart-1be5e933-5cac-42d5-8fc9-b3439c62f1e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637251667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.637251667
Directory /workspace/7.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1725591089
Short name T776
Test name
Test status
Simulation time 18219166 ps
CPU time 0.62 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 194544 kb
Host smart-b20f3a1b-b4ac-44d0-a9aa-07f23d16653f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725591089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1725591089
Directory /workspace/7.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2060444302
Short name T842
Test name
Test status
Simulation time 158398003 ps
CPU time 0.88 seconds
Started Jun 29 05:12:48 PM PDT 24
Finished Jun 29 05:12:49 PM PDT 24
Peak memory 197796 kb
Host smart-0e72530d-5dce-4b61-9aa3-81fa493880f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060444302 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2060444302
Directory /workspace/7.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2293694092
Short name T795
Test name
Test status
Simulation time 352191059 ps
CPU time 2.98 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:53 PM PDT 24
Peak memory 198716 kb
Host smart-547bb9bf-1aff-478b-9899-f11bd4edf652
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293694092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2293694092
Directory /workspace/7.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4001909905
Short name T737
Test name
Test status
Simulation time 71142447 ps
CPU time 1.08 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 198652 kb
Host smart-830147f4-c5d7-4ae4-85b6-d6d436e180f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001909905 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.4001909905
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2168538140
Short name T767
Test name
Test status
Simulation time 14742322 ps
CPU time 0.61 seconds
Started Jun 29 05:12:48 PM PDT 24
Finished Jun 29 05:12:50 PM PDT 24
Peak memory 196096 kb
Host smart-5ea44926-3e09-414c-b2d8-199f71722912
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168538140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2168538140
Directory /workspace/8.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.474088
Short name T750
Test name
Test status
Simulation time 53534351 ps
CPU time 0.59 seconds
Started Jun 29 05:12:57 PM PDT 24
Finished Jun 29 05:12:58 PM PDT 24
Peak memory 194404 kb
Host smart-796e9916-0781-4084-8da3-153e9883fdc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.474088
Directory /workspace/8.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2783355619
Short name T80
Test name
Test status
Simulation time 81823547 ps
CPU time 0.93 seconds
Started Jun 29 05:12:50 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 197048 kb
Host smart-75f6399a-ddcb-4214-b3c1-bc6747e494a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783355619 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2783355619
Directory /workspace/8.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4274204655
Short name T772
Test name
Test status
Simulation time 53230371 ps
CPU time 1.49 seconds
Started Jun 29 05:12:50 PM PDT 24
Finished Jun 29 05:12:52 PM PDT 24
Peak memory 198716 kb
Host smart-feebe434-b682-4cc8-971a-a63315fd48a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274204655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4274204655
Directory /workspace/8.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2608868760
Short name T59
Test name
Test status
Simulation time 115773056 ps
CPU time 1.54 seconds
Started Jun 29 05:12:49 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 198792 kb
Host smart-d2c27938-9b86-43e3-92fa-dadad4132340
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608868760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2608868760
Directory /workspace/8.gpio_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.185221419
Short name T743
Test name
Test status
Simulation time 81857106 ps
CPU time 0.82 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:13:00 PM PDT 24
Peak memory 198652 kb
Host smart-519fec45-09d5-4252-8814-de58483d9e14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185221419 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.185221419
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3453433596
Short name T775
Test name
Test status
Simulation time 19405822 ps
CPU time 0.67 seconds
Started Jun 29 05:13:01 PM PDT 24
Finished Jun 29 05:13:02 PM PDT 24
Peak memory 195600 kb
Host smart-84287e76-e316-4020-aa63-4338b7a46bad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453433596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3453433596
Directory /workspace/9.gpio_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1383885200
Short name T721
Test name
Test status
Simulation time 27634955 ps
CPU time 0.57 seconds
Started Jun 29 05:13:01 PM PDT 24
Finished Jun 29 05:13:02 PM PDT 24
Peak memory 194420 kb
Host smart-381a6919-ba78-4e20-af93-a0031428f5fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383885200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1383885200
Directory /workspace/9.gpio_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2782631787
Short name T96
Test name
Test status
Simulation time 18369783 ps
CPU time 0.72 seconds
Started Jun 29 05:13:00 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 196748 kb
Host smart-24b942ea-d39d-46fc-9888-9149d1c67097
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782631787 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2782631787
Directory /workspace/9.gpio_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1685833269
Short name T769
Test name
Test status
Simulation time 228741582 ps
CPU time 2.02 seconds
Started Jun 29 05:12:58 PM PDT 24
Finished Jun 29 05:13:01 PM PDT 24
Peak memory 198792 kb
Host smart-b17287cd-a2c8-43ec-a828-c05cf9dfa4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685833269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1685833269
Directory /workspace/9.gpio_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2465571942
Short name T811
Test name
Test status
Simulation time 209978551 ps
CPU time 1.19 seconds
Started Jun 29 05:13:00 PM PDT 24
Finished Jun 29 05:13:02 PM PDT 24
Peak memory 198752 kb
Host smart-184351b5-d4f9-47d6-be84-04eabc314018
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465571942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2465571942
Directory /workspace/9.gpio_tl_intg_err/latest


Test location /workspace/coverage/default/0.gpio_alert_test.1425571086
Short name T593
Test name
Test status
Simulation time 17710196 ps
CPU time 0.59 seconds
Started Jun 29 05:14:12 PM PDT 24
Finished Jun 29 05:14:13 PM PDT 24
Peak memory 196400 kb
Host smart-b2fa1c64-722e-4888-9a37-2e18809e76c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425571086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1425571086
Directory /workspace/0.gpio_alert_test/latest


Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.615377799
Short name T392
Test name
Test status
Simulation time 434616846 ps
CPU time 0.82 seconds
Started Jun 29 05:14:14 PM PDT 24
Finished Jun 29 05:14:15 PM PDT 24
Peak memory 196064 kb
Host smart-0a9fa52b-b422-4344-abce-0d90e6356b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615377799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.615377799
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/0.gpio_filter_stress.1469292210
Short name T575
Test name
Test status
Simulation time 906073023 ps
CPU time 25.15 seconds
Started Jun 29 05:14:15 PM PDT 24
Finished Jun 29 05:14:41 PM PDT 24
Peak memory 197652 kb
Host smart-31b3d6f5-ba73-47da-9b09-dabefbd634ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469292210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1469292210
Directory /workspace/0.gpio_filter_stress/latest


Test location /workspace/coverage/default/0.gpio_full_random.3413678069
Short name T658
Test name
Test status
Simulation time 68274873 ps
CPU time 0.63 seconds
Started Jun 29 05:14:18 PM PDT 24
Finished Jun 29 05:14:19 PM PDT 24
Peak memory 195008 kb
Host smart-23cef930-2224-4f5d-8108-6be9019c24ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413678069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3413678069
Directory /workspace/0.gpio_full_random/latest


Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.151537298
Short name T128
Test name
Test status
Simulation time 58261285 ps
CPU time 1.03 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:14:15 PM PDT 24
Peak memory 196976 kb
Host smart-7c832dc9-34ff-4003-a7e7-e4832e703f87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151537298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.151537298
Directory /workspace/0.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1322056697
Short name T537
Test name
Test status
Simulation time 60424849 ps
CPU time 2.51 seconds
Started Jun 29 05:14:18 PM PDT 24
Finished Jun 29 05:14:21 PM PDT 24
Peak memory 198812 kb
Host smart-42bde1a5-e299-490e-a481-217eb1671b63
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322056697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1322056697
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2503721424
Short name T467
Test name
Test status
Simulation time 90829294 ps
CPU time 1 seconds
Started Jun 29 05:14:12 PM PDT 24
Finished Jun 29 05:14:14 PM PDT 24
Peak memory 196256 kb
Host smart-460247af-e219-47f0-bb2c-a77b08fa4bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503721424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2503721424
Directory /workspace/0.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/0.gpio_random_dout_din.1509613366
Short name T530
Test name
Test status
Simulation time 200652102 ps
CPU time 1.24 seconds
Started Jun 29 05:14:14 PM PDT 24
Finished Jun 29 05:14:16 PM PDT 24
Peak memory 198076 kb
Host smart-aadf4c27-f742-4eea-a81f-1026fbde52c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509613366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1509613366
Directory /workspace/0.gpio_random_dout_din/latest


Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1676413061
Short name T14
Test name
Test status
Simulation time 87185461 ps
CPU time 0.88 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:14:15 PM PDT 24
Peak memory 197452 kb
Host smart-9a422d95-a0ff-41f4-a6dd-0238979d05f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676413061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1676413061
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.443220351
Short name T349
Test name
Test status
Simulation time 518074866 ps
CPU time 3.36 seconds
Started Jun 29 05:14:12 PM PDT 24
Finished Jun 29 05:14:17 PM PDT 24
Peak memory 198660 kb
Host smart-fe4b1941-eb90-49cd-b9a0-dd4827fdfa49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443220351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.443220351
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/0.gpio_smoke.2713782039
Short name T182
Test name
Test status
Simulation time 68367191 ps
CPU time 1.18 seconds
Started Jun 29 05:14:12 PM PDT 24
Finished Jun 29 05:14:14 PM PDT 24
Peak memory 196528 kb
Host smart-e544f2b0-23b5-4971-8b02-c1cdf3695abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713782039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2713782039
Directory /workspace/0.gpio_smoke/latest


Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3696332489
Short name T41
Test name
Test status
Simulation time 46127269 ps
CPU time 1.19 seconds
Started Jun 29 05:14:15 PM PDT 24
Finished Jun 29 05:14:17 PM PDT 24
Peak memory 196460 kb
Host smart-c59d309c-b04c-4451-86e6-fd0f60e1a518
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696332489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3696332489
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/0.gpio_stress_all.2732920588
Short name T410
Test name
Test status
Simulation time 70321325755 ps
CPU time 173.45 seconds
Started Jun 29 05:14:14 PM PDT 24
Finished Jun 29 05:17:08 PM PDT 24
Peak memory 198732 kb
Host smart-1046fa7a-5dce-4115-9c3c-28ec7ce5988c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732920588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2732920588
Directory /workspace/0.gpio_stress_all/latest


Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3450731390
Short name T695
Test name
Test status
Simulation time 588986192587 ps
CPU time 901.96 seconds
Started Jun 29 05:14:19 PM PDT 24
Finished Jun 29 05:29:21 PM PDT 24
Peak memory 198892 kb
Host smart-72344f68-b14c-4ea6-9b19-15f966fba731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3450731390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3450731390
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/1.gpio_alert_test.879350028
Short name T651
Test name
Test status
Simulation time 60357212 ps
CPU time 0.6 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 195376 kb
Host smart-eaef9d5d-254d-4fdb-824e-3ed9db90dc25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879350028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.879350028
Directory /workspace/1.gpio_alert_test/latest


Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1143924683
Short name T444
Test name
Test status
Simulation time 54032746 ps
CPU time 0.67 seconds
Started Jun 29 05:14:14 PM PDT 24
Finished Jun 29 05:14:16 PM PDT 24
Peak memory 194808 kb
Host smart-b7f6404c-d030-48fe-ab72-44378b8c0015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143924683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1143924683
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/1.gpio_filter_stress.1310627425
Short name T336
Test name
Test status
Simulation time 196263941 ps
CPU time 7.4 seconds
Started Jun 29 05:14:16 PM PDT 24
Finished Jun 29 05:14:24 PM PDT 24
Peak memory 198672 kb
Host smart-6a3087a1-0355-4bdf-954c-477c6f89337f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310627425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1310627425
Directory /workspace/1.gpio_filter_stress/latest


Test location /workspace/coverage/default/1.gpio_full_random.1284031746
Short name T628
Test name
Test status
Simulation time 122756365 ps
CPU time 0.74 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:14:15 PM PDT 24
Peak memory 196016 kb
Host smart-87f3fc6a-a0af-4a76-af9b-35b340027b5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284031746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1284031746
Directory /workspace/1.gpio_full_random/latest


Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.521603296
Short name T671
Test name
Test status
Simulation time 39253832 ps
CPU time 1.16 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:14:15 PM PDT 24
Peak memory 196692 kb
Host smart-94d0c118-b10c-4f38-95df-1cc95c43a548
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521603296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.521603296
Directory /workspace/1.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3142999665
Short name T660
Test name
Test status
Simulation time 222211374 ps
CPU time 3.38 seconds
Started Jun 29 05:14:14 PM PDT 24
Finished Jun 29 05:14:18 PM PDT 24
Peak memory 197836 kb
Host smart-5d8624ec-5667-4068-acf8-8ebfd430c886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142999665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3142999665
Directory /workspace/1.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/1.gpio_random_dout_din.2816447422
Short name T254
Test name
Test status
Simulation time 46104590 ps
CPU time 1 seconds
Started Jun 29 05:14:18 PM PDT 24
Finished Jun 29 05:14:19 PM PDT 24
Peak memory 196668 kb
Host smart-3a400edc-6180-466a-b224-dd0e2252c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816447422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2816447422
Directory /workspace/1.gpio_random_dout_din/latest


Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.485463589
Short name T287
Test name
Test status
Simulation time 85888711 ps
CPU time 1.05 seconds
Started Jun 29 05:14:18 PM PDT 24
Finished Jun 29 05:14:20 PM PDT 24
Peak memory 197196 kb
Host smart-647f2c86-5e07-46ca-a1cc-b2b66ff79353
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485463589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.485463589
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1764048874
Short name T523
Test name
Test status
Simulation time 205046833 ps
CPU time 2.09 seconds
Started Jun 29 05:14:18 PM PDT 24
Finished Jun 29 05:14:21 PM PDT 24
Peak memory 198640 kb
Host smart-233b9358-9c4d-4919-905e-a563f346da65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764048874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1764048874
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/1.gpio_sec_cm.3972563909
Short name T27
Test name
Test status
Simulation time 83091591 ps
CPU time 0.94 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 215324 kb
Host smart-e560661b-2117-4437-aa18-05303f8359c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972563909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3972563909
Directory /workspace/1.gpio_sec_cm/latest


Test location /workspace/coverage/default/1.gpio_smoke.1801315668
Short name T314
Test name
Test status
Simulation time 33620606 ps
CPU time 0.81 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:14:14 PM PDT 24
Peak memory 195840 kb
Host smart-64677c73-2573-43db-8dc5-ec48bc4bf2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801315668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1801315668
Directory /workspace/1.gpio_smoke/latest


Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2472484607
Short name T200
Test name
Test status
Simulation time 76515914 ps
CPU time 1.33 seconds
Started Jun 29 05:14:12 PM PDT 24
Finished Jun 29 05:14:14 PM PDT 24
Peak memory 198684 kb
Host smart-277fb8b8-4454-4f40-b49b-d18366abd3fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472484607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2472484607
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/1.gpio_stress_all.2406949741
Short name T106
Test name
Test status
Simulation time 6881487582 ps
CPU time 87.33 seconds
Started Jun 29 05:14:14 PM PDT 24
Finished Jun 29 05:15:42 PM PDT 24
Peak memory 198812 kb
Host smart-7d8a0c02-e551-46b9-bf97-022793cfeddf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406949741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2406949741
Directory /workspace/1.gpio_stress_all/latest


Test location /workspace/coverage/default/10.gpio_alert_test.862322383
Short name T327
Test name
Test status
Simulation time 31665760 ps
CPU time 0.55 seconds
Started Jun 29 05:14:50 PM PDT 24
Finished Jun 29 05:14:52 PM PDT 24
Peak memory 194680 kb
Host smart-9f9a26c6-7862-4876-ae64-a5a3d368ac5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862322383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.862322383
Directory /workspace/10.gpio_alert_test/latest


Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2425094324
Short name T123
Test name
Test status
Simulation time 51983501 ps
CPU time 0.87 seconds
Started Jun 29 05:14:46 PM PDT 24
Finished Jun 29 05:14:47 PM PDT 24
Peak memory 197888 kb
Host smart-46351ce6-9f62-4cc9-9cbe-fd22ceddfd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425094324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2425094324
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/10.gpio_filter_stress.2037647475
Short name T223
Test name
Test status
Simulation time 131728393 ps
CPU time 6.98 seconds
Started Jun 29 05:14:40 PM PDT 24
Finished Jun 29 05:14:48 PM PDT 24
Peak memory 197608 kb
Host smart-78c3dabd-68cd-4e9b-b8b5-7d096df2ebe4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037647475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2037647475
Directory /workspace/10.gpio_filter_stress/latest


Test location /workspace/coverage/default/10.gpio_full_random.1344675005
Short name T559
Test name
Test status
Simulation time 272612743 ps
CPU time 0.88 seconds
Started Jun 29 05:14:46 PM PDT 24
Finished Jun 29 05:14:48 PM PDT 24
Peak memory 197648 kb
Host smart-a1ac4e83-cc20-4a21-b690-0dadbd39ae68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344675005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1344675005
Directory /workspace/10.gpio_full_random/latest


Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3728821946
Short name T591
Test name
Test status
Simulation time 86629124 ps
CPU time 1 seconds
Started Jun 29 05:14:42 PM PDT 24
Finished Jun 29 05:14:44 PM PDT 24
Peak memory 196672 kb
Host smart-2adb2f9b-59c6-417b-a674-0a755e706303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728821946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3728821946
Directory /workspace/10.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1396393018
Short name T227
Test name
Test status
Simulation time 83337749 ps
CPU time 3.45 seconds
Started Jun 29 05:14:41 PM PDT 24
Finished Jun 29 05:14:45 PM PDT 24
Peak memory 198592 kb
Host smart-84005a5e-053a-4161-8f7d-063c3bc69a18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396393018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1396393018
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2283170215
Short name T662
Test name
Test status
Simulation time 116809069 ps
CPU time 2.14 seconds
Started Jun 29 05:14:42 PM PDT 24
Finished Jun 29 05:14:44 PM PDT 24
Peak memory 197808 kb
Host smart-318e1878-5e3a-4293-95e2-df2469bd3535
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283170215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2283170215
Directory /workspace/10.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/10.gpio_random_dout_din.2897782685
Short name T638
Test name
Test status
Simulation time 87403107 ps
CPU time 0.93 seconds
Started Jun 29 05:14:40 PM PDT 24
Finished Jun 29 05:14:41 PM PDT 24
Peak memory 196504 kb
Host smart-9641c25d-eafe-4728-a92f-d73567eebf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897782685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2897782685
Directory /workspace/10.gpio_random_dout_din/latest


Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3514496277
Short name T197
Test name
Test status
Simulation time 39294432 ps
CPU time 0.71 seconds
Started Jun 29 05:14:42 PM PDT 24
Finished Jun 29 05:14:43 PM PDT 24
Peak memory 195964 kb
Host smart-7809deaf-85f4-447e-aac1-e027af72d130
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514496277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3514496277
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.916269943
Short name T208
Test name
Test status
Simulation time 139948396 ps
CPU time 6.16 seconds
Started Jun 29 05:14:42 PM PDT 24
Finished Jun 29 05:14:49 PM PDT 24
Peak memory 198648 kb
Host smart-c8c6c100-ab58-420b-bad0-3d1d5595b48e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916269943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.916269943
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/10.gpio_smoke.875899880
Short name T345
Test name
Test status
Simulation time 48542494 ps
CPU time 1.02 seconds
Started Jun 29 05:14:43 PM PDT 24
Finished Jun 29 05:14:45 PM PDT 24
Peak memory 196308 kb
Host smart-3a78cbaa-83c4-470a-95e0-e9aa8b21702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875899880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.875899880
Directory /workspace/10.gpio_smoke/latest


Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.348682716
Short name T159
Test name
Test status
Simulation time 60310157 ps
CPU time 1.15 seconds
Started Jun 29 05:14:49 PM PDT 24
Finished Jun 29 05:14:51 PM PDT 24
Peak memory 196552 kb
Host smart-0081cb41-5846-4d55-b53d-4da9330d57b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348682716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.348682716
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/10.gpio_stress_all.1690022241
Short name T300
Test name
Test status
Simulation time 3380915672 ps
CPU time 95.85 seconds
Started Jun 29 05:14:41 PM PDT 24
Finished Jun 29 05:16:17 PM PDT 24
Peak memory 198804 kb
Host smart-d50482da-c17e-4571-9e51-e76690d12326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690022241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1690022241
Directory /workspace/10.gpio_stress_all/latest


Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.768629790
Short name T104
Test name
Test status
Simulation time 184400288735 ps
CPU time 2392.81 seconds
Started Jun 29 05:14:51 PM PDT 24
Finished Jun 29 05:54:44 PM PDT 24
Peak memory 198936 kb
Host smart-d61bd4f5-9c73-455c-b2b6-0926b5c48d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=768629790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.768629790
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/11.gpio_alert_test.3613051623
Short name T241
Test name
Test status
Simulation time 19232391 ps
CPU time 0.58 seconds
Started Jun 29 05:14:39 PM PDT 24
Finished Jun 29 05:14:40 PM PDT 24
Peak memory 195384 kb
Host smart-5a10762c-682f-413f-aa86-95e3652bbf45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613051623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3613051623
Directory /workspace/11.gpio_alert_test/latest


Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1346011940
Short name T413
Test name
Test status
Simulation time 97154384 ps
CPU time 0.92 seconds
Started Jun 29 05:14:46 PM PDT 24
Finished Jun 29 05:14:48 PM PDT 24
Peak memory 196652 kb
Host smart-4d11a3f8-2c15-4ca5-9dbd-42dcaa6d712c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346011940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1346011940
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/11.gpio_filter_stress.3429945898
Short name T492
Test name
Test status
Simulation time 1746870371 ps
CPU time 17.38 seconds
Started Jun 29 05:14:46 PM PDT 24
Finished Jun 29 05:15:04 PM PDT 24
Peak memory 198648 kb
Host smart-f05e5637-a9cd-4352-af80-f1c77e3defdc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429945898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3429945898
Directory /workspace/11.gpio_filter_stress/latest


Test location /workspace/coverage/default/11.gpio_full_random.3899517514
Short name T251
Test name
Test status
Simulation time 276468302 ps
CPU time 0.92 seconds
Started Jun 29 05:14:46 PM PDT 24
Finished Jun 29 05:14:48 PM PDT 24
Peak memory 197232 kb
Host smart-ed2e3705-19ac-4d00-a4eb-e1618936905e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899517514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3899517514
Directory /workspace/11.gpio_full_random/latest


Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1031097597
Short name T252
Test name
Test status
Simulation time 66444508 ps
CPU time 0.92 seconds
Started Jun 29 05:14:46 PM PDT 24
Finished Jun 29 05:14:48 PM PDT 24
Peak memory 196744 kb
Host smart-54c47cf8-8e9c-4d77-bfe8-0ed45abe0a5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031097597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1031097597
Directory /workspace/11.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2960822554
Short name T465
Test name
Test status
Simulation time 33026874 ps
CPU time 0.95 seconds
Started Jun 29 05:14:45 PM PDT 24
Finished Jun 29 05:14:46 PM PDT 24
Peak memory 196636 kb
Host smart-53631676-9783-41bf-a3d0-9e960eeb2736
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960822554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2960822554
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3769059777
Short name T587
Test name
Test status
Simulation time 281296343 ps
CPU time 2.33 seconds
Started Jun 29 05:14:45 PM PDT 24
Finished Jun 29 05:14:48 PM PDT 24
Peak memory 197836 kb
Host smart-b48220e5-0dc5-48da-8a84-5f08fe75f799
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769059777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3769059777
Directory /workspace/11.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/11.gpio_random_dout_din.1906487644
Short name T419
Test name
Test status
Simulation time 188835430 ps
CPU time 1.07 seconds
Started Jun 29 05:14:43 PM PDT 24
Finished Jun 29 05:14:45 PM PDT 24
Peak memory 197192 kb
Host smart-e4bd40ff-1d6b-4d72-bf1c-d8577d4254a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906487644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1906487644
Directory /workspace/11.gpio_random_dout_din/latest


Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3937035256
Short name T513
Test name
Test status
Simulation time 85592565 ps
CPU time 0.8 seconds
Started Jun 29 05:14:42 PM PDT 24
Finished Jun 29 05:14:43 PM PDT 24
Peak memory 196760 kb
Host smart-ca937abe-c77a-4996-b58e-d33f58dea1cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937035256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3937035256
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.959075480
Short name T624
Test name
Test status
Simulation time 803355969 ps
CPU time 6.56 seconds
Started Jun 29 05:14:45 PM PDT 24
Finished Jun 29 05:14:52 PM PDT 24
Peak memory 198676 kb
Host smart-59974c4c-888f-426d-8ee1-a558e9c96efd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959075480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.959075480
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/11.gpio_smoke.539178962
Short name T258
Test name
Test status
Simulation time 793027681 ps
CPU time 1.27 seconds
Started Jun 29 05:14:42 PM PDT 24
Finished Jun 29 05:14:43 PM PDT 24
Peak memory 196248 kb
Host smart-c820dc19-f2d6-49b1-955c-bdc4b3608667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539178962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.539178962
Directory /workspace/11.gpio_smoke/latest


Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.4008016815
Short name T337
Test name
Test status
Simulation time 33582161 ps
CPU time 1.05 seconds
Started Jun 29 05:14:44 PM PDT 24
Finished Jun 29 05:14:45 PM PDT 24
Peak memory 196460 kb
Host smart-3ddeeb80-f806-4953-8aad-b314703790cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008016815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.4008016815
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/11.gpio_stress_all.1402838713
Short name T449
Test name
Test status
Simulation time 4070718449 ps
CPU time 106.45 seconds
Started Jun 29 05:14:43 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 198728 kb
Host smart-eeb39160-e428-420f-9156-4db4860e64b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402838713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1402838713
Directory /workspace/11.gpio_stress_all/latest


Test location /workspace/coverage/default/12.gpio_alert_test.2056697546
Short name T623
Test name
Test status
Simulation time 31601684 ps
CPU time 0.6 seconds
Started Jun 29 05:14:59 PM PDT 24
Finished Jun 29 05:15:00 PM PDT 24
Peak memory 194852 kb
Host smart-49c66dbe-4541-4fc3-92c3-d7c2117489b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056697546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2056697546
Directory /workspace/12.gpio_alert_test/latest


Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1308474239
Short name T499
Test name
Test status
Simulation time 25854154 ps
CPU time 0.82 seconds
Started Jun 29 05:14:46 PM PDT 24
Finished Jun 29 05:14:48 PM PDT 24
Peak memory 196060 kb
Host smart-7c63efe7-5836-4948-9156-eca52f5121b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308474239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1308474239
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/12.gpio_filter_stress.2749384948
Short name T440
Test name
Test status
Simulation time 567708211 ps
CPU time 19.9 seconds
Started Jun 29 05:14:49 PM PDT 24
Finished Jun 29 05:15:09 PM PDT 24
Peak memory 197536 kb
Host smart-0a94f41d-f863-4668-acc4-373a4b24bb12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749384948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2749384948
Directory /workspace/12.gpio_filter_stress/latest


Test location /workspace/coverage/default/12.gpio_full_random.4191802108
Short name T643
Test name
Test status
Simulation time 48164899 ps
CPU time 0.7 seconds
Started Jun 29 05:14:52 PM PDT 24
Finished Jun 29 05:14:53 PM PDT 24
Peak memory 195964 kb
Host smart-55077613-e65b-43cd-94ba-75c468109d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191802108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4191802108
Directory /workspace/12.gpio_full_random/latest


Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3554152565
Short name T306
Test name
Test status
Simulation time 316918701 ps
CPU time 1.08 seconds
Started Jun 29 05:14:46 PM PDT 24
Finished Jun 29 05:14:48 PM PDT 24
Peak memory 196716 kb
Host smart-4d4d55fb-3a79-4581-a79f-2608d677fb5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554152565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3554152565
Directory /workspace/12.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.400324679
Short name T620
Test name
Test status
Simulation time 397631383 ps
CPU time 3.16 seconds
Started Jun 29 05:14:49 PM PDT 24
Finished Jun 29 05:14:52 PM PDT 24
Peak memory 197164 kb
Host smart-c377f8ad-0a96-4582-834d-a619558831f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400324679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.400324679
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1480358609
Short name T417
Test name
Test status
Simulation time 524079910 ps
CPU time 2.93 seconds
Started Jun 29 05:14:41 PM PDT 24
Finished Jun 29 05:14:44 PM PDT 24
Peak memory 198684 kb
Host smart-24624275-4ef8-45f7-9712-c19adf8a2f23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480358609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1480358609
Directory /workspace/12.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/12.gpio_random_dout_din.3602254088
Short name T190
Test name
Test status
Simulation time 50197879 ps
CPU time 1.09 seconds
Started Jun 29 05:14:49 PM PDT 24
Finished Jun 29 05:14:51 PM PDT 24
Peak memory 197344 kb
Host smart-1bc6603e-7934-42bc-9a0d-4570b9b564aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602254088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3602254088
Directory /workspace/12.gpio_random_dout_din/latest


Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3166713165
Short name T656
Test name
Test status
Simulation time 62347011 ps
CPU time 0.82 seconds
Started Jun 29 05:14:41 PM PDT 24
Finished Jun 29 05:14:42 PM PDT 24
Peak memory 196232 kb
Host smart-5f3af893-90fb-4277-82eb-b098dcfdb5c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166713165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3166713165
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3768024197
Short name T380
Test name
Test status
Simulation time 836910653 ps
CPU time 4.75 seconds
Started Jun 29 05:14:51 PM PDT 24
Finished Jun 29 05:14:56 PM PDT 24
Peak memory 198612 kb
Host smart-c69570b0-33d3-41bc-a34f-88eeddd2f5ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768024197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3768024197
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/12.gpio_smoke.598123562
Short name T580
Test name
Test status
Simulation time 57183743 ps
CPU time 1.11 seconds
Started Jun 29 05:14:40 PM PDT 24
Finished Jun 29 05:14:42 PM PDT 24
Peak memory 196572 kb
Host smart-941960c7-72e5-4c7b-8d65-aeeabfc2a012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598123562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.598123562
Directory /workspace/12.gpio_smoke/latest


Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3581058203
Short name T464
Test name
Test status
Simulation time 177143597 ps
CPU time 0.85 seconds
Started Jun 29 05:14:42 PM PDT 24
Finished Jun 29 05:14:44 PM PDT 24
Peak memory 196624 kb
Host smart-0ee368c3-fc51-4e32-8002-759d2600d5b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581058203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3581058203
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/12.gpio_stress_all.1009014457
Short name T476
Test name
Test status
Simulation time 5286202504 ps
CPU time 55.69 seconds
Started Jun 29 05:14:51 PM PDT 24
Finished Jun 29 05:15:47 PM PDT 24
Peak memory 198768 kb
Host smart-65862075-fbae-4563-a99b-8d84b23d64d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009014457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1009014457
Directory /workspace/12.gpio_stress_all/latest


Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1946259338
Short name T288
Test name
Test status
Simulation time 42145590 ps
CPU time 0.89 seconds
Started Jun 29 05:14:58 PM PDT 24
Finished Jun 29 05:15:00 PM PDT 24
Peak memory 196092 kb
Host smart-21cd33d1-bbab-427f-bb45-5206287b5c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946259338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1946259338
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/13.gpio_filter_stress.2844219631
Short name T697
Test name
Test status
Simulation time 162764885 ps
CPU time 5.22 seconds
Started Jun 29 05:14:56 PM PDT 24
Finished Jun 29 05:15:02 PM PDT 24
Peak memory 196948 kb
Host smart-be7a764f-c6ea-4f4a-a401-cf518aca2152
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844219631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2844219631
Directory /workspace/13.gpio_filter_stress/latest


Test location /workspace/coverage/default/13.gpio_full_random.3140047375
Short name T420
Test name
Test status
Simulation time 223694569 ps
CPU time 0.93 seconds
Started Jun 29 05:15:02 PM PDT 24
Finished Jun 29 05:15:03 PM PDT 24
Peak memory 197700 kb
Host smart-9d410065-6c96-44bf-88a8-711bdc9f39ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140047375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3140047375
Directory /workspace/13.gpio_full_random/latest


Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1347890762
Short name T469
Test name
Test status
Simulation time 44615425 ps
CPU time 1.28 seconds
Started Jun 29 05:14:57 PM PDT 24
Finished Jun 29 05:14:59 PM PDT 24
Peak memory 196524 kb
Host smart-c5ff3e5f-c6c9-4f3a-9b44-0ad7f25c9d30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347890762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1347890762
Directory /workspace/13.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3903784367
Short name T315
Test name
Test status
Simulation time 335449502 ps
CPU time 3.56 seconds
Started Jun 29 05:14:59 PM PDT 24
Finished Jun 29 05:15:03 PM PDT 24
Peak memory 198684 kb
Host smart-dddde862-9b01-4399-aecc-fc27df268a51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903784367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3903784367
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2850626619
Short name T517
Test name
Test status
Simulation time 402766682 ps
CPU time 2.23 seconds
Started Jun 29 05:14:59 PM PDT 24
Finished Jun 29 05:15:02 PM PDT 24
Peak memory 198724 kb
Host smart-b0bfb64f-89b0-4d2f-afb4-913b7b4dbfb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850626619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2850626619
Directory /workspace/13.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/13.gpio_random_dout_din.2301577140
Short name T595
Test name
Test status
Simulation time 99259856 ps
CPU time 0.98 seconds
Started Jun 29 05:14:58 PM PDT 24
Finished Jun 29 05:14:59 PM PDT 24
Peak memory 197284 kb
Host smart-eae63b60-8764-44e2-bdb6-57abb9de0b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301577140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2301577140
Directory /workspace/13.gpio_random_dout_din/latest


Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3639400349
Short name T415
Test name
Test status
Simulation time 145173117 ps
CPU time 0.98 seconds
Started Jun 29 05:14:59 PM PDT 24
Finished Jun 29 05:15:00 PM PDT 24
Peak memory 196700 kb
Host smart-789ab46b-8f0f-4d9b-9511-6013da8b20da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639400349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3639400349
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4169045203
Short name T22
Test name
Test status
Simulation time 159323619 ps
CPU time 1.53 seconds
Started Jun 29 05:15:05 PM PDT 24
Finished Jun 29 05:15:07 PM PDT 24
Peak memory 198672 kb
Host smart-aab04465-d9c0-4f78-be52-db7c1dd92f9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169045203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4169045203
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/13.gpio_smoke.7161429
Short name T528
Test name
Test status
Simulation time 262752515 ps
CPU time 1.3 seconds
Started Jun 29 05:14:58 PM PDT 24
Finished Jun 29 05:15:00 PM PDT 24
Peak memory 196456 kb
Host smart-fd6ffeab-62c3-45a0-b994-1a2fc126ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7161429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.7161429
Directory /workspace/13.gpio_smoke/latest


Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2892419820
Short name T212
Test name
Test status
Simulation time 97389709 ps
CPU time 1.45 seconds
Started Jun 29 05:15:02 PM PDT 24
Finished Jun 29 05:15:04 PM PDT 24
Peak memory 197428 kb
Host smart-d9cce387-df89-40dc-bb32-1dec46cee276
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892419820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2892419820
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/13.gpio_stress_all.3112196601
Short name T519
Test name
Test status
Simulation time 11614493506 ps
CPU time 33.35 seconds
Started Jun 29 05:14:59 PM PDT 24
Finished Jun 29 05:15:33 PM PDT 24
Peak memory 198784 kb
Host smart-076b3a27-b74f-46d2-8667-3fe8f9b1e053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112196601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3112196601
Directory /workspace/13.gpio_stress_all/latest


Test location /workspace/coverage/default/14.gpio_alert_test.379632617
Short name T43
Test name
Test status
Simulation time 25925681 ps
CPU time 0.57 seconds
Started Jun 29 05:15:09 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 193060 kb
Host smart-35d950af-a234-4ccc-ad32-f5d62d59bfa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379632617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.379632617
Directory /workspace/14.gpio_alert_test/latest


Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2255666027
Short name T342
Test name
Test status
Simulation time 38087433 ps
CPU time 0.6 seconds
Started Jun 29 05:14:58 PM PDT 24
Finished Jun 29 05:14:59 PM PDT 24
Peak memory 194564 kb
Host smart-39054399-ec80-4ae5-9695-669f956bc267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255666027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2255666027
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/14.gpio_filter_stress.3338133092
Short name T687
Test name
Test status
Simulation time 1356517628 ps
CPU time 16.83 seconds
Started Jun 29 05:15:06 PM PDT 24
Finished Jun 29 05:15:23 PM PDT 24
Peak memory 198700 kb
Host smart-d159d6c8-dbe2-465c-93f9-3dfe719632b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338133092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3338133092
Directory /workspace/14.gpio_filter_stress/latest


Test location /workspace/coverage/default/14.gpio_full_random.1290819684
Short name T630
Test name
Test status
Simulation time 49855152 ps
CPU time 0.68 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 195960 kb
Host smart-ddacc389-085f-438e-943a-60c9b8389914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290819684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1290819684
Directory /workspace/14.gpio_full_random/latest


Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.278983746
Short name T542
Test name
Test status
Simulation time 39425168 ps
CPU time 0.87 seconds
Started Jun 29 05:15:02 PM PDT 24
Finished Jun 29 05:15:03 PM PDT 24
Peak memory 196184 kb
Host smart-e3c0bf88-921f-42fe-8315-da9927550fd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278983746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.278983746
Directory /workspace/14.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2143143457
Short name T502
Test name
Test status
Simulation time 66835529 ps
CPU time 2.65 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:11 PM PDT 24
Peak memory 198764 kb
Host smart-6906b1ae-c605-40c3-94f6-32b7fd5bb0ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143143457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2143143457
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1661260133
Short name T708
Test name
Test status
Simulation time 77651826 ps
CPU time 1.29 seconds
Started Jun 29 05:14:58 PM PDT 24
Finished Jun 29 05:15:00 PM PDT 24
Peak memory 196388 kb
Host smart-f2a89f48-40a5-41eb-98ba-bad254d2ce46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661260133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1661260133
Directory /workspace/14.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/14.gpio_random_dout_din.3712420391
Short name T429
Test name
Test status
Simulation time 14135133 ps
CPU time 0.63 seconds
Started Jun 29 05:14:57 PM PDT 24
Finished Jun 29 05:14:59 PM PDT 24
Peak memory 194976 kb
Host smart-5f7a61cb-ceb1-47dd-b5f9-c68317ed6a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712420391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3712420391
Directory /workspace/14.gpio_random_dout_din/latest


Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.261184317
Short name T316
Test name
Test status
Simulation time 66036346 ps
CPU time 1.19 seconds
Started Jun 29 05:14:56 PM PDT 24
Finished Jun 29 05:14:57 PM PDT 24
Peak memory 197664 kb
Host smart-57e2341c-1cc4-445c-800a-352f0f05482c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261184317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.261184317
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/14.gpio_smoke.254543072
Short name T119
Test name
Test status
Simulation time 58123625 ps
CPU time 0.99 seconds
Started Jun 29 05:14:57 PM PDT 24
Finished Jun 29 05:14:58 PM PDT 24
Peak memory 195852 kb
Host smart-edbf36f2-8530-45cf-be23-caa682f94593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254543072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.254543072
Directory /workspace/14.gpio_smoke/latest


Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.4213765816
Short name T416
Test name
Test status
Simulation time 20037159 ps
CPU time 0.76 seconds
Started Jun 29 05:14:58 PM PDT 24
Finished Jun 29 05:15:00 PM PDT 24
Peak memory 196548 kb
Host smart-b67b7573-28b9-44cd-9f99-0ba5ac99b0cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213765816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.4213765816
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/14.gpio_stress_all.2298870441
Short name T373
Test name
Test status
Simulation time 5050463847 ps
CPU time 72.84 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:16:21 PM PDT 24
Peak memory 198776 kb
Host smart-39740815-4821-4445-bb53-eee3f86e41e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298870441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2298870441
Directory /workspace/14.gpio_stress_all/latest


Test location /workspace/coverage/default/15.gpio_alert_test.2096139465
Short name T243
Test name
Test status
Simulation time 12194520 ps
CPU time 0.55 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:08 PM PDT 24
Peak memory 195372 kb
Host smart-427bfe18-6b55-4f8c-8fbc-69ab869c680d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096139465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2096139465
Directory /workspace/15.gpio_alert_test/latest


Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1099778385
Short name T262
Test name
Test status
Simulation time 100383224 ps
CPU time 0.64 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:09 PM PDT 24
Peak memory 194620 kb
Host smart-c57ade6c-2aaf-4f21-8ad3-02bcbe8bfe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099778385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1099778385
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/15.gpio_filter_stress.4048342168
Short name T685
Test name
Test status
Simulation time 470492738 ps
CPU time 6.78 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:14 PM PDT 24
Peak memory 197520 kb
Host smart-e79070da-f794-4c36-b2bb-001f315e8581
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048342168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4048342168
Directory /workspace/15.gpio_filter_stress/latest


Test location /workspace/coverage/default/15.gpio_full_random.2432462729
Short name T282
Test name
Test status
Simulation time 411235356 ps
CPU time 1.12 seconds
Started Jun 29 05:15:09 PM PDT 24
Finished Jun 29 05:15:11 PM PDT 24
Peak memory 198740 kb
Host smart-e710248d-32aa-4aa3-82c8-75ddc485a55a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432462729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2432462729
Directory /workspace/15.gpio_full_random/latest


Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4190055736
Short name T561
Test name
Test status
Simulation time 70595501 ps
CPU time 1.16 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:08 PM PDT 24
Peak memory 197584 kb
Host smart-2435c34d-1401-411b-b8bf-5c09524236b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190055736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4190055736
Directory /workspace/15.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1056546212
Short name T661
Test name
Test status
Simulation time 52849143 ps
CPU time 2.28 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:11 PM PDT 24
Peak memory 198724 kb
Host smart-6a9af645-8ff0-4d0c-a1ea-4ab7f52817b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056546212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1056546212
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3454188452
Short name T571
Test name
Test status
Simulation time 220924792 ps
CPU time 1.87 seconds
Started Jun 29 05:15:05 PM PDT 24
Finished Jun 29 05:15:08 PM PDT 24
Peak memory 197556 kb
Host smart-7e3b9dca-4519-4c01-86fb-137f74814f56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454188452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3454188452
Directory /workspace/15.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/15.gpio_random_dout_din.2872328081
Short name T427
Test name
Test status
Simulation time 159208714 ps
CPU time 0.71 seconds
Started Jun 29 05:15:09 PM PDT 24
Finished Jun 29 05:15:11 PM PDT 24
Peak memory 195724 kb
Host smart-531fdc29-c468-41d2-a70a-96c4f8e7dcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872328081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2872328081
Directory /workspace/15.gpio_random_dout_din/latest


Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4264655976
Short name T371
Test name
Test status
Simulation time 41077934 ps
CPU time 1.02 seconds
Started Jun 29 05:15:06 PM PDT 24
Finished Jun 29 05:15:08 PM PDT 24
Peak memory 196764 kb
Host smart-e5d226fd-1a90-4644-8c2d-a9f6ff4a5131
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264655976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4264655976
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2833779464
Short name T118
Test name
Test status
Simulation time 98937716 ps
CPU time 4.55 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:13 PM PDT 24
Peak memory 198624 kb
Host smart-d05805c9-18a1-43e0-90d2-bc86374a6cff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833779464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2833779464
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/15.gpio_smoke.2213353055
Short name T448
Test name
Test status
Simulation time 151580030 ps
CPU time 0.96 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 197224 kb
Host smart-92569c14-eaf3-4155-bd4a-635192c8e7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213353055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2213353055
Directory /workspace/15.gpio_smoke/latest


Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1970198852
Short name T700
Test name
Test status
Simulation time 130116556 ps
CPU time 1.31 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:09 PM PDT 24
Peak memory 196240 kb
Host smart-95f0a0a6-df24-4917-ac54-b37f21a5a872
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970198852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1970198852
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/15.gpio_stress_all.4240272024
Short name T674
Test name
Test status
Simulation time 13638413120 ps
CPU time 147.47 seconds
Started Jun 29 05:15:09 PM PDT 24
Finished Jun 29 05:17:37 PM PDT 24
Peak memory 198764 kb
Host smart-8a0fe993-d84b-4726-87d2-2905225daf90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240272024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4240272024
Directory /workspace/15.gpio_stress_all/latest


Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.196451322
Short name T699
Test name
Test status
Simulation time 68371898463 ps
CPU time 1066.29 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:32:55 PM PDT 24
Peak memory 198948 kb
Host smart-76bd29f7-d422-4e86-acc0-50246db69d85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=196451322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.196451322
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/16.gpio_alert_test.130504109
Short name T535
Test name
Test status
Simulation time 35645329 ps
CPU time 0.59 seconds
Started Jun 29 05:15:05 PM PDT 24
Finished Jun 29 05:15:06 PM PDT 24
Peak memory 194880 kb
Host smart-4ce93bdf-a810-4ef1-84a9-09ea4be1938e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130504109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.130504109
Directory /workspace/16.gpio_alert_test/latest


Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1022538574
Short name T484
Test name
Test status
Simulation time 19359085 ps
CPU time 0.63 seconds
Started Jun 29 05:15:05 PM PDT 24
Finished Jun 29 05:15:06 PM PDT 24
Peak memory 194592 kb
Host smart-c26ac43f-6e4f-491b-97ec-18908d727a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022538574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1022538574
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/16.gpio_filter_stress.3498967156
Short name T446
Test name
Test status
Simulation time 297533658 ps
CPU time 8.6 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:17 PM PDT 24
Peak memory 196136 kb
Host smart-f169d94d-a4ac-4893-8b60-0b46ff2cc52d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498967156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3498967156
Directory /workspace/16.gpio_filter_stress/latest


Test location /workspace/coverage/default/16.gpio_full_random.2524671426
Short name T2
Test name
Test status
Simulation time 1744738289 ps
CPU time 1.18 seconds
Started Jun 29 05:15:09 PM PDT 24
Finished Jun 29 05:15:11 PM PDT 24
Peak memory 196496 kb
Host smart-5a9d534f-8cd6-4dfc-9e3a-7969086fded9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524671426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2524671426
Directory /workspace/16.gpio_full_random/latest


Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1533083914
Short name T402
Test name
Test status
Simulation time 20998785 ps
CPU time 0.67 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:09 PM PDT 24
Peak memory 195004 kb
Host smart-385d242c-ead0-43bc-b998-f5956637a2bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533083914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1533083914
Directory /workspace/16.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.990210183
Short name T498
Test name
Test status
Simulation time 251553966 ps
CPU time 2.56 seconds
Started Jun 29 05:15:06 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 198696 kb
Host smart-162cf87c-c67d-4142-81e6-0a4be45cb489
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990210183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.990210183
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1230137849
Short name T185
Test name
Test status
Simulation time 167222804 ps
CPU time 2.66 seconds
Started Jun 29 05:15:09 PM PDT 24
Finished Jun 29 05:15:13 PM PDT 24
Peak memory 198744 kb
Host smart-95c62bd6-e054-4a6d-999b-0d741cbb41df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230137849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1230137849
Directory /workspace/16.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/16.gpio_random_dout_din.977862747
Short name T67
Test name
Test status
Simulation time 112632322 ps
CPU time 1.35 seconds
Started Jun 29 05:15:09 PM PDT 24
Finished Jun 29 05:15:11 PM PDT 24
Peak memory 197276 kb
Host smart-d5d45125-8d5d-4297-8aa8-32c1d24e1bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977862747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.977862747
Directory /workspace/16.gpio_random_dout_din/latest


Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2993056464
Short name T456
Test name
Test status
Simulation time 63597154 ps
CPU time 1.09 seconds
Started Jun 29 05:15:05 PM PDT 24
Finished Jun 29 05:15:06 PM PDT 24
Peak memory 196548 kb
Host smart-f5c80190-f39a-4524-a2a5-48c8e1fec0b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993056464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2993056464
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.553126731
Short name T581
Test name
Test status
Simulation time 338881760 ps
CPU time 4.13 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:13 PM PDT 24
Peak memory 198672 kb
Host smart-f474e96a-51d1-4f68-a1d6-3eafc0940952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553126731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.553126731
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/16.gpio_smoke.1115785265
Short name T148
Test name
Test status
Simulation time 297835756 ps
CPU time 1.33 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 196260 kb
Host smart-3c710f10-5ea7-49e9-891e-d3a0073bdba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115785265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1115785265
Directory /workspace/16.gpio_smoke/latest


Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1442879670
Short name T271
Test name
Test status
Simulation time 22100400 ps
CPU time 0.76 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:09 PM PDT 24
Peak memory 195836 kb
Host smart-12dc1fab-08f4-4378-80c9-f55b19afcd78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442879670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1442879670
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/16.gpio_stress_all.2658530300
Short name T486
Test name
Test status
Simulation time 3105370606 ps
CPU time 51.02 seconds
Started Jun 29 05:15:07 PM PDT 24
Finished Jun 29 05:15:58 PM PDT 24
Peak memory 198804 kb
Host smart-2119269d-5a0b-4b25-94cd-f555bc36c4f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658530300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2658530300
Directory /workspace/16.gpio_stress_all/latest


Test location /workspace/coverage/default/17.gpio_alert_test.2418432761
Short name T341
Test name
Test status
Simulation time 12340100 ps
CPU time 0.61 seconds
Started Jun 29 05:15:21 PM PDT 24
Finished Jun 29 05:15:22 PM PDT 24
Peak memory 194856 kb
Host smart-186e7533-3d6c-46ef-9148-12e3af442a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418432761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2418432761
Directory /workspace/17.gpio_alert_test/latest


Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2489109983
Short name T642
Test name
Test status
Simulation time 241694712 ps
CPU time 0.92 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 196652 kb
Host smart-4e3ae598-fe76-4345-ab5c-30073f986b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489109983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2489109983
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/17.gpio_filter_stress.3189349070
Short name T31
Test name
Test status
Simulation time 3784056368 ps
CPU time 19.87 seconds
Started Jun 29 05:15:24 PM PDT 24
Finished Jun 29 05:15:44 PM PDT 24
Peak memory 198148 kb
Host smart-6380f50d-8921-469d-9878-53bf662e5d63
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189349070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3189349070
Directory /workspace/17.gpio_filter_stress/latest


Test location /workspace/coverage/default/17.gpio_full_random.1872262348
Short name T5
Test name
Test status
Simulation time 86927464 ps
CPU time 0.92 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 197828 kb
Host smart-b0508394-7bc0-42fe-b7cf-4918ed5005cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872262348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1872262348
Directory /workspace/17.gpio_full_random/latest


Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1967749060
Short name T201
Test name
Test status
Simulation time 39635499 ps
CPU time 1.12 seconds
Started Jun 29 05:15:06 PM PDT 24
Finished Jun 29 05:15:07 PM PDT 24
Peak memory 197264 kb
Host smart-d536a798-a925-4acb-8af3-7778a59b0ed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967749060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1967749060
Directory /workspace/17.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3766364170
Short name T485
Test name
Test status
Simulation time 367601541 ps
CPU time 1.08 seconds
Started Jun 29 05:15:09 PM PDT 24
Finished Jun 29 05:15:11 PM PDT 24
Peak memory 197456 kb
Host smart-67c46bcc-8e08-4795-9ddf-4ff68c724564
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766364170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3766364170
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1115066824
Short name T390
Test name
Test status
Simulation time 60364326 ps
CPU time 1.57 seconds
Started Jun 29 05:15:05 PM PDT 24
Finished Jun 29 05:15:07 PM PDT 24
Peak memory 197352 kb
Host smart-81b55036-4974-4416-b693-cab86c6e1572
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115066824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1115066824
Directory /workspace/17.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/17.gpio_random_dout_din.928315654
Short name T668
Test name
Test status
Simulation time 38073929 ps
CPU time 0.87 seconds
Started Jun 29 05:15:06 PM PDT 24
Finished Jun 29 05:15:07 PM PDT 24
Peak memory 197128 kb
Host smart-0d9643ff-bc45-4c84-8443-91dbb21da3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928315654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.928315654
Directory /workspace/17.gpio_random_dout_din/latest


Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.502571187
Short name T114
Test name
Test status
Simulation time 75966462 ps
CPU time 0.86 seconds
Started Jun 29 05:15:06 PM PDT 24
Finished Jun 29 05:15:07 PM PDT 24
Peak memory 197376 kb
Host smart-64f66f9a-aada-4d6a-995c-8ab914ecd9be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502571187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.502571187
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.491018351
Short name T586
Test name
Test status
Simulation time 245178750 ps
CPU time 3.18 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:20 PM PDT 24
Peak memory 198680 kb
Host smart-0c53b976-b570-4e50-a244-38c8174d1e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491018351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.491018351
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/17.gpio_smoke.1356831469
Short name T598
Test name
Test status
Simulation time 31013158 ps
CPU time 0.93 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 197496 kb
Host smart-24efbbb6-dd33-425d-944d-1a7a9fc55a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356831469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1356831469
Directory /workspace/17.gpio_smoke/latest


Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1522248609
Short name T210
Test name
Test status
Simulation time 177146812 ps
CPU time 1.13 seconds
Started Jun 29 05:15:08 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 196940 kb
Host smart-3c15304c-40f9-47cb-9f3e-54ab820dcc52
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522248609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1522248609
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/17.gpio_stress_all.47829894
Short name T401
Test name
Test status
Simulation time 43680089891 ps
CPU time 220.24 seconds
Started Jun 29 05:15:18 PM PDT 24
Finished Jun 29 05:19:00 PM PDT 24
Peak memory 198788 kb
Host smart-c6d49f84-2edc-4798-a9de-c773ac96ece0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47829894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gp
io_stress_all.47829894
Directory /workspace/17.gpio_stress_all/latest


Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.4105310381
Short name T653
Test name
Test status
Simulation time 438464518464 ps
CPU time 2483.19 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:56:42 PM PDT 24
Peak memory 198896 kb
Host smart-52ccb17d-3a9d-4372-b427-885e6bd365de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4105310381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.4105310381
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/18.gpio_alert_test.2744759259
Short name T647
Test name
Test status
Simulation time 13962945 ps
CPU time 0.58 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 195328 kb
Host smart-ec4a4a83-da3a-4ce7-b728-2e46bdab5f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744759259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2744759259
Directory /workspace/18.gpio_alert_test/latest


Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3919587900
Short name T355
Test name
Test status
Simulation time 272795094 ps
CPU time 0.85 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 196644 kb
Host smart-2070496c-2bc6-46f1-87c6-5428333125c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919587900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3919587900
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/18.gpio_filter_stress.4133324281
Short name T141
Test name
Test status
Simulation time 593571597 ps
CPU time 17.71 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:34 PM PDT 24
Peak memory 196964 kb
Host smart-dd37ee8f-450b-44a2-b868-8818732e37ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133324281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4133324281
Directory /workspace/18.gpio_filter_stress/latest


Test location /workspace/coverage/default/18.gpio_full_random.2438812517
Short name T213
Test name
Test status
Simulation time 83625205 ps
CPU time 1.01 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 198604 kb
Host smart-9e4267de-60f6-427d-b660-a38bb1add2c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438812517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2438812517
Directory /workspace/18.gpio_full_random/latest


Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.85057950
Short name T494
Test name
Test status
Simulation time 26762022 ps
CPU time 0.91 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:18 PM PDT 24
Peak memory 196300 kb
Host smart-eab252fc-1da4-4a1a-b608-96095de1b476
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85057950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.85057950
Directory /workspace/18.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1545070678
Short name T455
Test name
Test status
Simulation time 329298532 ps
CPU time 2.52 seconds
Started Jun 29 05:15:18 PM PDT 24
Finished Jun 29 05:15:22 PM PDT 24
Peak memory 198704 kb
Host smart-a9e2c128-dba7-4d78-aeff-9bda207ee942
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545070678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1545070678
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.19510747
Short name T704
Test name
Test status
Simulation time 316261208 ps
CPU time 2.36 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 196868 kb
Host smart-9363ba25-b6c1-43d1-bb18-ad18adaff771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19510747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.19510747
Directory /workspace/18.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/18.gpio_random_dout_din.254458960
Short name T221
Test name
Test status
Simulation time 49912287 ps
CPU time 1.05 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:18 PM PDT 24
Peak memory 197184 kb
Host smart-7f483e08-5e1e-4b53-b6c4-7e76f84de3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254458960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.254458960
Directory /workspace/18.gpio_random_dout_din/latest


Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2149707997
Short name T352
Test name
Test status
Simulation time 880913734 ps
CPU time 1.38 seconds
Started Jun 29 05:15:18 PM PDT 24
Finished Jun 29 05:15:21 PM PDT 24
Peak memory 198692 kb
Host smart-05bcd378-f65a-49a0-ad34-57c640724718
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149707997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2149707997
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.300146842
Short name T344
Test name
Test status
Simulation time 301081842 ps
CPU time 4.85 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:24 PM PDT 24
Peak memory 198668 kb
Host smart-24431af5-04ca-492c-85f7-4378e91d0681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300146842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.300146842
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/18.gpio_smoke.1797754129
Short name T354
Test name
Test status
Simulation time 80357665 ps
CPU time 1.29 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:18 PM PDT 24
Peak memory 196256 kb
Host smart-17713253-6e1c-4026-aec8-81a353d7c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797754129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1797754129
Directory /workspace/18.gpio_smoke/latest


Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.939108869
Short name T170
Test name
Test status
Simulation time 50225085 ps
CPU time 1.12 seconds
Started Jun 29 05:15:18 PM PDT 24
Finished Jun 29 05:15:20 PM PDT 24
Peak memory 197132 kb
Host smart-1e176cb0-7006-4607-935e-5c5a21bd16ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939108869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.939108869
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/18.gpio_stress_all.3539000216
Short name T447
Test name
Test status
Simulation time 4128601595 ps
CPU time 53.19 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:16:12 PM PDT 24
Peak memory 198744 kb
Host smart-b42c4760-eed5-48bd-a486-0ecae1a87e87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539000216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3539000216
Directory /workspace/18.gpio_stress_all/latest


Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1883615892
Short name T607
Test name
Test status
Simulation time 47870125984 ps
CPU time 628.22 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:25:47 PM PDT 24
Peak memory 198928 kb
Host smart-64f7f699-6324-48e5-8756-36fd544c3b61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1883615892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1883615892
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/19.gpio_alert_test.3548514064
Short name T334
Test name
Test status
Simulation time 11825524 ps
CPU time 0.55 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 193488 kb
Host smart-780ebf6b-17f9-4abf-ba5f-df528af6a8ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548514064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3548514064
Directory /workspace/19.gpio_alert_test/latest


Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3895536946
Short name T302
Test name
Test status
Simulation time 71046369 ps
CPU time 0.94 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:18 PM PDT 24
Peak memory 196648 kb
Host smart-80657dc2-ff41-459a-b3cc-5e790b644eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895536946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3895536946
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/19.gpio_filter_stress.1968199546
Short name T423
Test name
Test status
Simulation time 1821581129 ps
CPU time 16.67 seconds
Started Jun 29 05:15:21 PM PDT 24
Finished Jun 29 05:15:38 PM PDT 24
Peak memory 197596 kb
Host smart-84ec76b1-6247-4227-b570-de40794b5c57
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968199546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1968199546
Directory /workspace/19.gpio_filter_stress/latest


Test location /workspace/coverage/default/19.gpio_full_random.3278936854
Short name T46
Test name
Test status
Simulation time 172239128 ps
CPU time 0.8 seconds
Started Jun 29 05:15:19 PM PDT 24
Finished Jun 29 05:15:21 PM PDT 24
Peak memory 196600 kb
Host smart-c52580a4-31a4-471e-9740-e848baea0fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278936854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3278936854
Directory /workspace/19.gpio_full_random/latest


Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.389553041
Short name T411
Test name
Test status
Simulation time 892629748 ps
CPU time 1.37 seconds
Started Jun 29 05:15:19 PM PDT 24
Finished Jun 29 05:15:21 PM PDT 24
Peak memory 197668 kb
Host smart-9e27fca8-87ac-45c5-8471-95fa7e1fc65d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389553041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.389553041
Directory /workspace/19.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4209492430
Short name T164
Test name
Test status
Simulation time 77132525 ps
CPU time 3.17 seconds
Started Jun 29 05:15:24 PM PDT 24
Finished Jun 29 05:15:27 PM PDT 24
Peak memory 198788 kb
Host smart-8295a9a2-fc9a-4b03-b53b-2050ca472e53
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209492430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.4209492430
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3761892564
Short name T568
Test name
Test status
Simulation time 230737480 ps
CPU time 1.38 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:18 PM PDT 24
Peak memory 197484 kb
Host smart-6a5f8d48-4db3-48ca-b884-9a6b8d131be7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761892564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3761892564
Directory /workspace/19.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/19.gpio_random_dout_din.487125210
Short name T636
Test name
Test status
Simulation time 451178078 ps
CPU time 1.29 seconds
Started Jun 29 05:15:19 PM PDT 24
Finished Jun 29 05:15:21 PM PDT 24
Peak memory 198596 kb
Host smart-451453b1-dfbb-4e5c-86d7-1d1aac85ecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487125210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.487125210
Directory /workspace/19.gpio_random_dout_din/latest


Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3181514759
Short name T303
Test name
Test status
Simulation time 44191218 ps
CPU time 0.96 seconds
Started Jun 29 05:15:18 PM PDT 24
Finished Jun 29 05:15:20 PM PDT 24
Peak memory 197384 kb
Host smart-b49fe794-6b0f-415e-93e0-efd5ba7e31c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181514759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3181514759
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1639746249
Short name T6
Test name
Test status
Simulation time 447284528 ps
CPU time 3.07 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:22 PM PDT 24
Peak memory 198656 kb
Host smart-3a0bbc3a-f5f1-4f09-ab88-27fae4771022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639746249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1639746249
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/19.gpio_smoke.263518013
Short name T490
Test name
Test status
Simulation time 48081318 ps
CPU time 1.37 seconds
Started Jun 29 05:15:14 PM PDT 24
Finished Jun 29 05:15:16 PM PDT 24
Peak memory 197604 kb
Host smart-ffc6705f-ccb9-4797-8dc9-d0d4dae96263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263518013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.263518013
Directory /workspace/19.gpio_smoke/latest


Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3431239503
Short name T29
Test name
Test status
Simulation time 58440172 ps
CPU time 0.84 seconds
Started Jun 29 05:15:22 PM PDT 24
Finished Jun 29 05:15:23 PM PDT 24
Peak memory 195976 kb
Host smart-5767350f-e453-4bad-9d90-ff07a281b068
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431239503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3431239503
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/19.gpio_stress_all.3921573385
Short name T329
Test name
Test status
Simulation time 3725859169 ps
CPU time 33.49 seconds
Started Jun 29 05:15:18 PM PDT 24
Finished Jun 29 05:15:53 PM PDT 24
Peak memory 198684 kb
Host smart-f4c8ae93-e9ab-4e51-9380-d45822e565a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921573385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3921573385
Directory /workspace/19.gpio_stress_all/latest


Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.318160984
Short name T521
Test name
Test status
Simulation time 21090978095 ps
CPU time 566.38 seconds
Started Jun 29 05:15:15 PM PDT 24
Finished Jun 29 05:24:42 PM PDT 24
Peak memory 198980 kb
Host smart-2544cfed-d360-4324-b4fc-ba428e5e8a0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=318160984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.318160984
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/2.gpio_alert_test.707846159
Short name T696
Test name
Test status
Simulation time 30218350 ps
CPU time 0.56 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 194680 kb
Host smart-40e13f68-b2dc-492a-9b30-bd252846b500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707846159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.707846159
Directory /workspace/2.gpio_alert_test/latest


Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3749505071
Short name T136
Test name
Test status
Simulation time 26813184 ps
CPU time 0.86 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 195976 kb
Host smart-d13d36aa-bc31-4b54-b626-ae0daa6d6072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749505071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3749505071
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/2.gpio_filter_stress.3694960286
Short name T412
Test name
Test status
Simulation time 361484527 ps
CPU time 9.43 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 197704 kb
Host smart-0e5eec43-13a8-4045-8bce-f46a19e4c393
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694960286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3694960286
Directory /workspace/2.gpio_filter_stress/latest


Test location /workspace/coverage/default/2.gpio_full_random.1708451651
Short name T564
Test name
Test status
Simulation time 225412377 ps
CPU time 1.01 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 198688 kb
Host smart-79b96890-c9e8-4f54-8c62-568c637d99f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708451651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1708451651
Directory /workspace/2.gpio_full_random/latest


Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3715270558
Short name T158
Test name
Test status
Simulation time 60610193 ps
CPU time 0.81 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 196196 kb
Host smart-3283e6b0-a743-4dfe-8953-abd9b1361570
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715270558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3715270558
Directory /workspace/2.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2282033290
Short name T698
Test name
Test status
Simulation time 326913242 ps
CPU time 1.89 seconds
Started Jun 29 05:14:22 PM PDT 24
Finished Jun 29 05:14:24 PM PDT 24
Peak memory 198812 kb
Host smart-9b55c745-fee2-4f1c-a941-3aad6b991dbe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282033290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2282033290
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2303151959
Short name T527
Test name
Test status
Simulation time 470703011 ps
CPU time 2.71 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:28 PM PDT 24
Peak memory 197200 kb
Host smart-c6428650-f2c9-4a4f-90ae-618b5a8cf4b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303151959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2303151959
Directory /workspace/2.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/2.gpio_random_dout_din.2498899074
Short name T237
Test name
Test status
Simulation time 56154815 ps
CPU time 1.29 seconds
Started Jun 29 05:14:22 PM PDT 24
Finished Jun 29 05:14:24 PM PDT 24
Peak memory 197684 kb
Host smart-cb3b5483-20a9-4dc6-a6d2-2e558a87f896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498899074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2498899074
Directory /workspace/2.gpio_random_dout_din/latest


Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2282370865
Short name T582
Test name
Test status
Simulation time 157294928 ps
CPU time 0.82 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 196140 kb
Host smart-ac5cc56f-da11-4363-80ad-d970da7cc08b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282370865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2282370865
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.279577107
Short name T318
Test name
Test status
Simulation time 525470027 ps
CPU time 3.31 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:27 PM PDT 24
Peak memory 198656 kb
Host smart-cc8d09ab-7722-45a7-951e-bd3f84087ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279577107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.279577107
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/2.gpio_sec_cm.2663334199
Short name T64
Test name
Test status
Simulation time 479430755 ps
CPU time 0.96 seconds
Started Jun 29 05:14:26 PM PDT 24
Finished Jun 29 05:14:28 PM PDT 24
Peak memory 215312 kb
Host smart-44a3c6aa-5b3e-43bb-ad1d-7e6b33cc404f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663334199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2663334199
Directory /workspace/2.gpio_sec_cm/latest


Test location /workspace/coverage/default/2.gpio_smoke.1485942885
Short name T317
Test name
Test status
Simulation time 76701609 ps
CPU time 1.38 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:27 PM PDT 24
Peak memory 197532 kb
Host smart-3e50115a-d86c-4899-bc7c-911a0e799cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485942885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1485942885
Directory /workspace/2.gpio_smoke/latest


Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1130686832
Short name T120
Test name
Test status
Simulation time 139310259 ps
CPU time 1.08 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 196396 kb
Host smart-8b45c903-f429-4621-8543-f4d0c26dbcbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130686832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1130686832
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/2.gpio_stress_all.2788645256
Short name T42
Test name
Test status
Simulation time 20348006501 ps
CPU time 125.73 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:16:32 PM PDT 24
Peak memory 198812 kb
Host smart-19768131-3cf7-4f78-a431-2e42cd63a52e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788645256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2788645256
Directory /workspace/2.gpio_stress_all/latest


Test location /workspace/coverage/default/20.gpio_alert_test.3725834618
Short name T28
Test name
Test status
Simulation time 15019929 ps
CPU time 0.6 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 194836 kb
Host smart-8f65497a-f40b-4775-bf44-bedab4f532c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725834618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3725834618
Directory /workspace/20.gpio_alert_test/latest


Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.289821315
Short name T550
Test name
Test status
Simulation time 89293826 ps
CPU time 0.73 seconds
Started Jun 29 05:15:24 PM PDT 24
Finished Jun 29 05:15:25 PM PDT 24
Peak memory 195656 kb
Host smart-e40da730-678b-4592-afeb-cd2f2898f11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289821315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.289821315
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/20.gpio_filter_stress.3847250732
Short name T573
Test name
Test status
Simulation time 131039632 ps
CPU time 3.48 seconds
Started Jun 29 05:15:19 PM PDT 24
Finished Jun 29 05:15:23 PM PDT 24
Peak memory 196224 kb
Host smart-369a0c5d-c752-47c3-93ec-d069eb0c10ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847250732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3847250732
Directory /workspace/20.gpio_filter_stress/latest


Test location /workspace/coverage/default/20.gpio_full_random.2904552746
Short name T25
Test name
Test status
Simulation time 39547556 ps
CPU time 0.7 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:17 PM PDT 24
Peak memory 195228 kb
Host smart-5fb15923-767f-4b08-aea7-9ac1dacb851d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904552746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2904552746
Directory /workspace/20.gpio_full_random/latest


Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1958354038
Short name T35
Test name
Test status
Simulation time 341041870 ps
CPU time 1.34 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 197904 kb
Host smart-a10422e5-c623-4e74-9988-7e234f20988e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958354038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1958354038
Directory /workspace/20.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3398553276
Short name T171
Test name
Test status
Simulation time 79639092 ps
CPU time 3.17 seconds
Started Jun 29 05:15:15 PM PDT 24
Finished Jun 29 05:15:18 PM PDT 24
Peak memory 198764 kb
Host smart-696f21c0-8f1d-480a-a02b-7e3af99d5fdc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398553276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3398553276
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4213578769
Short name T157
Test name
Test status
Simulation time 64780064 ps
CPU time 1.19 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 197988 kb
Host smart-75e56bb2-1737-420d-9168-4f5e4fe2e46b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213578769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4213578769
Directory /workspace/20.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/20.gpio_random_dout_din.684132393
Short name T130
Test name
Test status
Simulation time 71148012 ps
CPU time 1.27 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:18 PM PDT 24
Peak memory 197692 kb
Host smart-ec61acf5-fc09-4bf6-80b0-463dd2910703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684132393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.684132393
Directory /workspace/20.gpio_random_dout_din/latest


Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1882206430
Short name T461
Test name
Test status
Simulation time 395028338 ps
CPU time 1.17 seconds
Started Jun 29 05:15:18 PM PDT 24
Finished Jun 29 05:15:21 PM PDT 24
Peak memory 196844 kb
Host smart-308986c2-f740-4abe-8264-84283593a8ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882206430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1882206430
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2797295887
Short name T367
Test name
Test status
Simulation time 852595513 ps
CPU time 3.79 seconds
Started Jun 29 05:15:15 PM PDT 24
Finished Jun 29 05:15:19 PM PDT 24
Peak memory 198708 kb
Host smart-12f79f7f-125a-4c68-8e6c-cc1575b8b98d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797295887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2797295887
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/20.gpio_smoke.52873159
Short name T325
Test name
Test status
Simulation time 175342537 ps
CPU time 0.94 seconds
Started Jun 29 05:15:23 PM PDT 24
Finished Jun 29 05:15:24 PM PDT 24
Peak memory 197232 kb
Host smart-907fbe3c-2eee-4688-8d62-568e78f4a7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52873159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.52873159
Directory /workspace/20.gpio_smoke/latest


Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.548144919
Short name T625
Test name
Test status
Simulation time 1372165353 ps
CPU time 1.42 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:15:20 PM PDT 24
Peak memory 197408 kb
Host smart-bbc9a255-7b9b-43f9-9033-25d9f7b78465
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548144919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.548144919
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/20.gpio_stress_all.3740811048
Short name T311
Test name
Test status
Simulation time 25689550031 ps
CPU time 163.73 seconds
Started Jun 29 05:15:24 PM PDT 24
Finished Jun 29 05:18:08 PM PDT 24
Peak memory 198828 kb
Host smart-43f60a57-68d4-40e7-ac0f-a00cc060f00b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740811048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3740811048
Directory /workspace/20.gpio_stress_all/latest


Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.4184512066
Short name T49
Test name
Test status
Simulation time 453815485858 ps
CPU time 1202.49 seconds
Started Jun 29 05:15:17 PM PDT 24
Finished Jun 29 05:35:20 PM PDT 24
Peak memory 198832 kb
Host smart-ea756f6f-0d14-4f7d-92fe-348fe90a0d69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4184512066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.4184512066
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/21.gpio_alert_test.802172330
Short name T688
Test name
Test status
Simulation time 55173473 ps
CPU time 0.6 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:27 PM PDT 24
Peak memory 194680 kb
Host smart-7573ebd8-db2b-449c-99dc-f85a24c7d053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802172330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.802172330
Directory /workspace/21.gpio_alert_test/latest


Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1081016854
Short name T576
Test name
Test status
Simulation time 38008357 ps
CPU time 0.62 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:15:27 PM PDT 24
Peak memory 194700 kb
Host smart-5cfc838e-ab07-42e0-9e28-e86c5a310744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081016854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1081016854
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/21.gpio_filter_stress.374423697
Short name T657
Test name
Test status
Simulation time 2981580397 ps
CPU time 24.48 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:15:50 PM PDT 24
Peak memory 198956 kb
Host smart-6407b5cb-1c73-4207-a41b-b120812c198f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374423697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.374423697
Directory /workspace/21.gpio_filter_stress/latest


Test location /workspace/coverage/default/21.gpio_full_random.146508247
Short name T267
Test name
Test status
Simulation time 35196084 ps
CPU time 0.8 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:28 PM PDT 24
Peak memory 196572 kb
Host smart-1fcf1938-dd42-48aa-9ca7-2cda6841a239
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146508247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.146508247
Directory /workspace/21.gpio_full_random/latest


Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3774061681
Short name T558
Test name
Test status
Simulation time 869042068 ps
CPU time 1.36 seconds
Started Jun 29 05:15:24 PM PDT 24
Finished Jun 29 05:15:26 PM PDT 24
Peak memory 196860 kb
Host smart-bf01501f-8d4e-4a46-9a5c-664c4c89d88b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774061681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3774061681
Directory /workspace/21.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2719320490
Short name T298
Test name
Test status
Simulation time 57214124 ps
CPU time 2.41 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:29 PM PDT 24
Peak memory 197160 kb
Host smart-8f102265-8388-4ede-9ec2-6a3eb43a36ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719320490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2719320490
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.351392914
Short name T555
Test name
Test status
Simulation time 33857018 ps
CPU time 1.22 seconds
Started Jun 29 05:15:28 PM PDT 24
Finished Jun 29 05:15:29 PM PDT 24
Peak memory 198216 kb
Host smart-7544b215-e1f4-417c-8557-4e168beb59c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351392914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
351392914
Directory /workspace/21.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/21.gpio_random_dout_din.253150929
Short name T374
Test name
Test status
Simulation time 47447262 ps
CPU time 1.33 seconds
Started Jun 29 05:15:16 PM PDT 24
Finished Jun 29 05:15:18 PM PDT 24
Peak memory 197584 kb
Host smart-f4bf41ec-5b2f-4db5-a8c2-b48c47fbdaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253150929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.253150929
Directory /workspace/21.gpio_random_dout_din/latest


Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1167252574
Short name T457
Test name
Test status
Simulation time 144273377 ps
CPU time 0.69 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:15:26 PM PDT 24
Peak memory 195032 kb
Host smart-659a6a7f-ea86-46b3-86e7-97f66cfb85f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167252574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1167252574
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1307038174
Short name T422
Test name
Test status
Simulation time 100807095 ps
CPU time 3.16 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:30 PM PDT 24
Peak memory 198672 kb
Host smart-a54314bf-4c60-41f2-a736-b9786761af7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307038174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1307038174
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/21.gpio_smoke.1332668200
Short name T180
Test name
Test status
Simulation time 41355579 ps
CPU time 1.26 seconds
Started Jun 29 05:15:18 PM PDT 24
Finished Jun 29 05:15:20 PM PDT 24
Peak memory 197460 kb
Host smart-2f267fa1-a033-4103-9362-bc49e40bbbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332668200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1332668200
Directory /workspace/21.gpio_smoke/latest


Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.364362389
Short name T247
Test name
Test status
Simulation time 173144627 ps
CPU time 1.35 seconds
Started Jun 29 05:15:21 PM PDT 24
Finished Jun 29 05:15:23 PM PDT 24
Peak memory 197468 kb
Host smart-5f5f1a82-c049-4352-baa7-9f1bb2c24149
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364362389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.364362389
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/21.gpio_stress_all.2370429718
Short name T470
Test name
Test status
Simulation time 58275172956 ps
CPU time 164.2 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:18:10 PM PDT 24
Peak memory 198812 kb
Host smart-b8f449dc-226e-4836-b585-fc317acca1d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370429718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2370429718
Directory /workspace/21.gpio_stress_all/latest


Test location /workspace/coverage/default/22.gpio_alert_test.3723210172
Short name T500
Test name
Test status
Simulation time 76233463 ps
CPU time 0.57 seconds
Started Jun 29 05:15:29 PM PDT 24
Finished Jun 29 05:15:30 PM PDT 24
Peak memory 194868 kb
Host smart-1da63432-5cce-42de-89fc-72dc5cd55662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723210172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3723210172
Directory /workspace/22.gpio_alert_test/latest


Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.32249773
Short name T635
Test name
Test status
Simulation time 23641800 ps
CPU time 0.79 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:15:27 PM PDT 24
Peak memory 196680 kb
Host smart-0aa995de-f3c7-41ca-bb51-1e05f056ca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32249773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.32249773
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/22.gpio_filter_stress.3328550925
Short name T304
Test name
Test status
Simulation time 175646984 ps
CPU time 8.79 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:36 PM PDT 24
Peak memory 197668 kb
Host smart-a3ae4403-b51d-4f68-b9b3-7c05e1e85bbd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328550925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3328550925
Directory /workspace/22.gpio_filter_stress/latest


Test location /workspace/coverage/default/22.gpio_full_random.3571479710
Short name T3
Test name
Test status
Simulation time 1025761976 ps
CPU time 0.89 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:27 PM PDT 24
Peak memory 197808 kb
Host smart-bceea0c2-fb49-473c-a36b-b30c5bf219e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571479710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3571479710
Directory /workspace/22.gpio_full_random/latest


Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3643035292
Short name T451
Test name
Test status
Simulation time 378045559 ps
CPU time 0.68 seconds
Started Jun 29 05:15:24 PM PDT 24
Finished Jun 29 05:15:25 PM PDT 24
Peak memory 195452 kb
Host smart-a67cafff-cec1-4a28-b730-95221148472e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643035292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3643035292
Directory /workspace/22.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2980124077
Short name T169
Test name
Test status
Simulation time 281749511 ps
CPU time 3.12 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:30 PM PDT 24
Peak memory 198652 kb
Host smart-475cf5b0-14d0-4188-b389-eb810c59e3e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980124077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2980124077
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.4207616448
Short name T214
Test name
Test status
Simulation time 115745399 ps
CPU time 0.86 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:15:26 PM PDT 24
Peak memory 195072 kb
Host smart-720eece1-a0f0-4394-a84a-e7545b24ab7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207616448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.4207616448
Directory /workspace/22.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/22.gpio_random_dout_din.3686816190
Short name T441
Test name
Test status
Simulation time 108698343 ps
CPU time 1.16 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:28 PM PDT 24
Peak memory 197376 kb
Host smart-4f0a38f2-6186-4b9c-95c7-0f4877d3f513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686816190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3686816190
Directory /workspace/22.gpio_random_dout_din/latest


Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.807060461
Short name T452
Test name
Test status
Simulation time 154087123 ps
CPU time 0.79 seconds
Started Jun 29 05:15:24 PM PDT 24
Finished Jun 29 05:15:25 PM PDT 24
Peak memory 197212 kb
Host smart-77c46932-77c5-4b14-a034-5c627785a3b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807060461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.807060461
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1579708323
Short name T137
Test name
Test status
Simulation time 51269185 ps
CPU time 2.54 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:15:28 PM PDT 24
Peak memory 198716 kb
Host smart-913f5de7-d248-4368-9468-ef9dc3226a44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579708323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1579708323
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/22.gpio_smoke.3329042580
Short name T273
Test name
Test status
Simulation time 102497403 ps
CPU time 0.75 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:15:26 PM PDT 24
Peak memory 194768 kb
Host smart-f5107d1d-caef-41f7-b826-00bc14e3835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329042580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3329042580
Directory /workspace/22.gpio_smoke/latest


Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3644825631
Short name T529
Test name
Test status
Simulation time 120602154 ps
CPU time 0.92 seconds
Started Jun 29 05:15:24 PM PDT 24
Finished Jun 29 05:15:25 PM PDT 24
Peak memory 196392 kb
Host smart-f37a1ee5-44b7-4126-9fcd-ed25f15b3b02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644825631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3644825631
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/22.gpio_stress_all.3975288962
Short name T259
Test name
Test status
Simulation time 22194604408 ps
CPU time 154.25 seconds
Started Jun 29 05:15:23 PM PDT 24
Finished Jun 29 05:17:57 PM PDT 24
Peak memory 198724 kb
Host smart-4fd83de9-1054-4ef8-907f-9943aff939cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975288962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3975288962
Directory /workspace/22.gpio_stress_all/latest


Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1218366259
Short name T99
Test name
Test status
Simulation time 99866348965 ps
CPU time 1486.75 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:40:13 PM PDT 24
Peak memory 198944 kb
Host smart-7b2535c3-db17-41e2-be83-c71781916bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1218366259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1218366259
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/23.gpio_alert_test.3789176709
Short name T309
Test name
Test status
Simulation time 13870192 ps
CPU time 0.59 seconds
Started Jun 29 05:15:37 PM PDT 24
Finished Jun 29 05:15:38 PM PDT 24
Peak memory 194700 kb
Host smart-f269f102-5455-4ebc-a9d0-1173193ba7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789176709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3789176709
Directory /workspace/23.gpio_alert_test/latest


Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3466915597
Short name T404
Test name
Test status
Simulation time 14198448 ps
CPU time 0.59 seconds
Started Jun 29 05:15:33 PM PDT 24
Finished Jun 29 05:15:34 PM PDT 24
Peak memory 194600 kb
Host smart-6aff9978-fe0c-4f44-a3c3-b5b9b1af02c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466915597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3466915597
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/23.gpio_filter_stress.2510643259
Short name T418
Test name
Test status
Simulation time 599542807 ps
CPU time 18.15 seconds
Started Jun 29 05:15:32 PM PDT 24
Finished Jun 29 05:15:51 PM PDT 24
Peak memory 198688 kb
Host smart-dca86a77-cc89-4e0b-9f7f-d389da912077
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510643259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2510643259
Directory /workspace/23.gpio_filter_stress/latest


Test location /workspace/coverage/default/23.gpio_full_random.65034609
Short name T160
Test name
Test status
Simulation time 53710407 ps
CPU time 0.63 seconds
Started Jun 29 05:15:32 PM PDT 24
Finished Jun 29 05:15:33 PM PDT 24
Peak memory 195824 kb
Host smart-454b51b0-5495-411e-8ebe-2fdb33dbc2c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65034609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.65034609
Directory /workspace/23.gpio_full_random/latest


Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2157932839
Short name T637
Test name
Test status
Simulation time 109738124 ps
CPU time 1.21 seconds
Started Jun 29 05:15:33 PM PDT 24
Finished Jun 29 05:15:35 PM PDT 24
Peak memory 197564 kb
Host smart-37a1627a-c0aa-44f0-8ae2-c7594851364a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157932839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2157932839
Directory /workspace/23.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3892681501
Short name T471
Test name
Test status
Simulation time 365318702 ps
CPU time 3.82 seconds
Started Jun 29 05:15:39 PM PDT 24
Finished Jun 29 05:15:43 PM PDT 24
Peak memory 198740 kb
Host smart-c03fff5f-e4aa-4512-9076-b9df25de301c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892681501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3892681501
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1586453184
Short name T381
Test name
Test status
Simulation time 644074146 ps
CPU time 1.83 seconds
Started Jun 29 05:15:38 PM PDT 24
Finished Jun 29 05:15:40 PM PDT 24
Peak memory 196852 kb
Host smart-2f2f82e5-a6b8-4348-a239-82187e742d50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586453184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1586453184
Directory /workspace/23.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/23.gpio_random_dout_din.2588856916
Short name T639
Test name
Test status
Simulation time 35865313 ps
CPU time 1.37 seconds
Started Jun 29 05:15:26 PM PDT 24
Finished Jun 29 05:15:28 PM PDT 24
Peak memory 197772 kb
Host smart-ded545cb-a92a-4884-9bba-35096906cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588856916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2588856916
Directory /workspace/23.gpio_random_dout_din/latest


Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1368586942
Short name T233
Test name
Test status
Simulation time 63296607 ps
CPU time 0.89 seconds
Started Jun 29 05:15:25 PM PDT 24
Finished Jun 29 05:15:26 PM PDT 24
Peak memory 196776 kb
Host smart-56f038e8-da54-473c-9d60-0a707f171bd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368586942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1368586942
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4203713207
Short name T385
Test name
Test status
Simulation time 129673792 ps
CPU time 5.51 seconds
Started Jun 29 05:15:38 PM PDT 24
Finished Jun 29 05:15:44 PM PDT 24
Peak memory 198620 kb
Host smart-81da8b71-dfe5-4a04-af2e-7e7b3bb46d9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203713207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4203713207
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/23.gpio_smoke.1547827156
Short name T278
Test name
Test status
Simulation time 247712548 ps
CPU time 1.1 seconds
Started Jun 29 05:15:28 PM PDT 24
Finished Jun 29 05:15:30 PM PDT 24
Peak memory 196260 kb
Host smart-13ed23c6-91eb-4456-b958-76a8e81b2196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547827156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1547827156
Directory /workspace/23.gpio_smoke/latest


Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2152361445
Short name T126
Test name
Test status
Simulation time 106403815 ps
CPU time 1.46 seconds
Started Jun 29 05:15:29 PM PDT 24
Finished Jun 29 05:15:31 PM PDT 24
Peak memory 198676 kb
Host smart-7e90ce3a-6863-4152-a41e-0d5c5cf61a76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152361445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2152361445
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/23.gpio_stress_all.1230487658
Short name T548
Test name
Test status
Simulation time 19587546307 ps
CPU time 196.77 seconds
Started Jun 29 05:15:41 PM PDT 24
Finished Jun 29 05:18:59 PM PDT 24
Peak memory 198808 kb
Host smart-1d4ae773-60ee-4dc8-8aad-58f9340d8f0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230487658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1230487658
Directory /workspace/23.gpio_stress_all/latest


Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4104867806
Short name T69
Test name
Test status
Simulation time 472179966973 ps
CPU time 615.36 seconds
Started Jun 29 05:15:39 PM PDT 24
Finished Jun 29 05:25:55 PM PDT 24
Peak memory 207136 kb
Host smart-2fa8b2ca-dfc6-4bca-a5a4-0091b64f2a8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4104867806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.4104867806
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/24.gpio_alert_test.4149824638
Short name T281
Test name
Test status
Simulation time 28025154 ps
CPU time 0.6 seconds
Started Jun 29 05:15:41 PM PDT 24
Finished Jun 29 05:15:42 PM PDT 24
Peak memory 194688 kb
Host smart-d96f05c2-672d-464a-865b-7990e6b64b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149824638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4149824638
Directory /workspace/24.gpio_alert_test/latest


Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3984432085
Short name T546
Test name
Test status
Simulation time 21312048 ps
CPU time 0.63 seconds
Started Jun 29 05:15:32 PM PDT 24
Finished Jun 29 05:15:33 PM PDT 24
Peak memory 194628 kb
Host smart-e8dcc131-3051-4d74-9c08-623cde526aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984432085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3984432085
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/24.gpio_filter_stress.454050832
Short name T146
Test name
Test status
Simulation time 1063928991 ps
CPU time 16.37 seconds
Started Jun 29 05:15:34 PM PDT 24
Finished Jun 29 05:15:51 PM PDT 24
Peak memory 196240 kb
Host smart-1da03b67-f597-4387-94cc-764127e60ccd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454050832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.454050832
Directory /workspace/24.gpio_filter_stress/latest


Test location /workspace/coverage/default/24.gpio_full_random.2867976733
Short name T335
Test name
Test status
Simulation time 108549635 ps
CPU time 0.91 seconds
Started Jun 29 05:15:35 PM PDT 24
Finished Jun 29 05:15:36 PM PDT 24
Peak memory 196676 kb
Host smart-38897b5f-0d04-4ac5-ad4b-594acfb0aaa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867976733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2867976733
Directory /workspace/24.gpio_full_random/latest


Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.291394070
Short name T706
Test name
Test status
Simulation time 146172083 ps
CPU time 1.25 seconds
Started Jun 29 05:15:40 PM PDT 24
Finished Jun 29 05:15:42 PM PDT 24
Peak memory 196720 kb
Host smart-d0ecf401-3b43-4dfa-8205-6062b2c7cd8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291394070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.291394070
Directory /workspace/24.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.877648783
Short name T217
Test name
Test status
Simulation time 340010242 ps
CPU time 3.53 seconds
Started Jun 29 05:15:36 PM PDT 24
Finished Jun 29 05:15:40 PM PDT 24
Peak memory 198816 kb
Host smart-fdee5b1c-1a98-473b-aed3-a25b35a3da07
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877648783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.877648783
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.736758088
Short name T219
Test name
Test status
Simulation time 54487233 ps
CPU time 1.29 seconds
Started Jun 29 05:15:34 PM PDT 24
Finished Jun 29 05:15:36 PM PDT 24
Peak memory 196920 kb
Host smart-1adf2650-5d46-408b-8ef3-22b845ed8b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736758088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
736758088
Directory /workspace/24.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/24.gpio_random_dout_din.145762712
Short name T297
Test name
Test status
Simulation time 244799031 ps
CPU time 1.28 seconds
Started Jun 29 05:15:39 PM PDT 24
Finished Jun 29 05:15:41 PM PDT 24
Peak memory 197752 kb
Host smart-b50a8c63-8029-45df-9c35-5b754f534f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145762712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.145762712
Directory /workspace/24.gpio_random_dout_din/latest


Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.183331225
Short name T424
Test name
Test status
Simulation time 338959431 ps
CPU time 1.12 seconds
Started Jun 29 05:15:37 PM PDT 24
Finished Jun 29 05:15:38 PM PDT 24
Peak memory 196804 kb
Host smart-f76feb3f-5b4d-48a3-bf14-e0a11812384d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183331225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.183331225
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.279283706
Short name T32
Test name
Test status
Simulation time 334921220 ps
CPU time 4.39 seconds
Started Jun 29 05:15:39 PM PDT 24
Finished Jun 29 05:15:44 PM PDT 24
Peak memory 198632 kb
Host smart-c1727671-ab17-4831-a313-17e1bb800270
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279283706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.279283706
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/24.gpio_smoke.1957936028
Short name T181
Test name
Test status
Simulation time 116467585 ps
CPU time 1.27 seconds
Started Jun 29 05:15:33 PM PDT 24
Finished Jun 29 05:15:35 PM PDT 24
Peak memory 197260 kb
Host smart-49c45415-1f33-4498-bf0f-649884cab9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957936028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1957936028
Directory /workspace/24.gpio_smoke/latest


Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2253380823
Short name T482
Test name
Test status
Simulation time 51777234 ps
CPU time 1.31 seconds
Started Jun 29 05:15:31 PM PDT 24
Finished Jun 29 05:15:33 PM PDT 24
Peak memory 197472 kb
Host smart-6cfb4622-734d-43fd-bf41-22bcae11bf15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253380823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2253380823
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/24.gpio_stress_all.1527310408
Short name T323
Test name
Test status
Simulation time 14898267568 ps
CPU time 102.2 seconds
Started Jun 29 05:15:39 PM PDT 24
Finished Jun 29 05:17:22 PM PDT 24
Peak memory 198780 kb
Host smart-0c49219f-db2e-44d6-a436-0eb913051b38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527310408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1527310408
Directory /workspace/24.gpio_stress_all/latest


Test location /workspace/coverage/default/25.gpio_alert_test.4099151644
Short name T246
Test name
Test status
Simulation time 13690959 ps
CPU time 0.58 seconds
Started Jun 29 05:15:43 PM PDT 24
Finished Jun 29 05:15:45 PM PDT 24
Peak memory 194656 kb
Host smart-b6e9811a-95e5-4fe7-87d0-eb19175c62b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099151644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4099151644
Directory /workspace/25.gpio_alert_test/latest


Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3892519440
Short name T179
Test name
Test status
Simulation time 482797277 ps
CPU time 0.87 seconds
Started Jun 29 05:15:44 PM PDT 24
Finished Jun 29 05:15:45 PM PDT 24
Peak memory 197032 kb
Host smart-e6cea71f-17bb-4f1d-8b26-440426985a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892519440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3892519440
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/25.gpio_filter_stress.489510230
Short name T387
Test name
Test status
Simulation time 743664065 ps
CPU time 12.96 seconds
Started Jun 29 05:15:42 PM PDT 24
Finished Jun 29 05:15:56 PM PDT 24
Peak memory 196188 kb
Host smart-853702c4-f262-4a44-aa10-a1d914899dfd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489510230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.489510230
Directory /workspace/25.gpio_filter_stress/latest


Test location /workspace/coverage/default/25.gpio_full_random.1881815490
Short name T557
Test name
Test status
Simulation time 275904488 ps
CPU time 1.08 seconds
Started Jun 29 05:15:44 PM PDT 24
Finished Jun 29 05:15:46 PM PDT 24
Peak memory 197280 kb
Host smart-89a6c210-a68c-4520-a4dc-74f8629d5ee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881815490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1881815490
Directory /workspace/25.gpio_full_random/latest


Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2138382941
Short name T384
Test name
Test status
Simulation time 364431347 ps
CPU time 1.34 seconds
Started Jun 29 05:15:46 PM PDT 24
Finished Jun 29 05:15:48 PM PDT 24
Peak memory 197844 kb
Host smart-6ae7a839-85ec-4d7b-8e5b-1bb7a4c52b4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138382941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2138382941
Directory /workspace/25.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1052936052
Short name T496
Test name
Test status
Simulation time 30934225 ps
CPU time 1.29 seconds
Started Jun 29 05:15:44 PM PDT 24
Finished Jun 29 05:15:46 PM PDT 24
Peak memory 197388 kb
Host smart-1ba50bcc-f265-4684-8de1-d82f26ffe44d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052936052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1052936052
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2645360000
Short name T167
Test name
Test status
Simulation time 731925081 ps
CPU time 2.64 seconds
Started Jun 29 05:15:41 PM PDT 24
Finished Jun 29 05:15:44 PM PDT 24
Peak memory 198744 kb
Host smart-15cb6b09-a581-484a-9ac3-9ea173ce646e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645360000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2645360000
Directory /workspace/25.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/25.gpio_random_dout_din.1395155504
Short name T263
Test name
Test status
Simulation time 35017577 ps
CPU time 0.86 seconds
Started Jun 29 05:15:43 PM PDT 24
Finished Jun 29 05:15:44 PM PDT 24
Peak memory 197176 kb
Host smart-3cf4a523-1893-4a74-930a-203c28ee9298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395155504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1395155504
Directory /workspace/25.gpio_random_dout_din/latest


Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1449492642
Short name T477
Test name
Test status
Simulation time 51121099 ps
CPU time 1.11 seconds
Started Jun 29 05:15:42 PM PDT 24
Finished Jun 29 05:15:44 PM PDT 24
Peak memory 197268 kb
Host smart-a42a9e20-913d-43da-9697-6876722adb58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449492642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1449492642
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3138368076
Short name T711
Test name
Test status
Simulation time 62814411 ps
CPU time 2.88 seconds
Started Jun 29 05:15:46 PM PDT 24
Finished Jun 29 05:15:49 PM PDT 24
Peak memory 198728 kb
Host smart-c071a5f0-8279-48da-ac04-5cf6d47ec2fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138368076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3138368076
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/25.gpio_smoke.409140531
Short name T135
Test name
Test status
Simulation time 48293711 ps
CPU time 1.31 seconds
Started Jun 29 05:15:33 PM PDT 24
Finished Jun 29 05:15:34 PM PDT 24
Peak memory 197336 kb
Host smart-b7208a0a-6b67-4759-b537-c3740c62e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409140531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.409140531
Directory /workspace/25.gpio_smoke/latest


Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.490102927
Short name T497
Test name
Test status
Simulation time 62289145 ps
CPU time 0.92 seconds
Started Jun 29 05:15:33 PM PDT 24
Finished Jun 29 05:15:34 PM PDT 24
Peak memory 197200 kb
Host smart-b42a0a93-975a-4948-aeef-afaa6bf878bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490102927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.490102927
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/25.gpio_stress_all.2869201093
Short name T378
Test name
Test status
Simulation time 12926864620 ps
CPU time 90.67 seconds
Started Jun 29 05:15:43 PM PDT 24
Finished Jun 29 05:17:14 PM PDT 24
Peak memory 198812 kb
Host smart-a33a07ff-fede-442e-a3a1-a3589f4cf970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869201093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2869201093
Directory /workspace/25.gpio_stress_all/latest


Test location /workspace/coverage/default/26.gpio_alert_test.402288346
Short name T293
Test name
Test status
Simulation time 38516076 ps
CPU time 0.58 seconds
Started Jun 29 05:15:41 PM PDT 24
Finished Jun 29 05:15:43 PM PDT 24
Peak memory 195376 kb
Host smart-c15868cb-8552-4a47-a982-f441b321c8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402288346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.402288346
Directory /workspace/26.gpio_alert_test/latest


Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2386837274
Short name T189
Test name
Test status
Simulation time 316637738 ps
CPU time 0.84 seconds
Started Jun 29 05:15:40 PM PDT 24
Finished Jun 29 05:15:42 PM PDT 24
Peak memory 196724 kb
Host smart-968e0da0-23f4-405a-b733-197603470141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386837274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2386837274
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/26.gpio_filter_stress.3141257413
Short name T260
Test name
Test status
Simulation time 280286263 ps
CPU time 15.28 seconds
Started Jun 29 05:15:44 PM PDT 24
Finished Jun 29 05:16:00 PM PDT 24
Peak memory 196208 kb
Host smart-992bc221-f15a-4f4c-a813-a529fff5b619
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141257413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3141257413
Directory /workspace/26.gpio_filter_stress/latest


Test location /workspace/coverage/default/26.gpio_full_random.123103218
Short name T107
Test name
Test status
Simulation time 89722340 ps
CPU time 0.86 seconds
Started Jun 29 05:15:47 PM PDT 24
Finished Jun 29 05:15:48 PM PDT 24
Peak memory 196532 kb
Host smart-2b17f7c5-49f2-43f4-bd4a-59d86e0652b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123103218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.123103218
Directory /workspace/26.gpio_full_random/latest


Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1113540867
Short name T478
Test name
Test status
Simulation time 182008518 ps
CPU time 0.91 seconds
Started Jun 29 05:15:40 PM PDT 24
Finished Jun 29 05:15:42 PM PDT 24
Peak memory 197196 kb
Host smart-fb6fd782-5696-4aa4-b839-84b38d4995a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113540867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1113540867
Directory /workspace/26.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.122523396
Short name T383
Test name
Test status
Simulation time 87488301 ps
CPU time 3.4 seconds
Started Jun 29 05:15:43 PM PDT 24
Finished Jun 29 05:15:47 PM PDT 24
Peak memory 198664 kb
Host smart-f18e183a-d26d-41d2-aa35-b4eaaabab677
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122523396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.122523396
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3820896030
Short name T578
Test name
Test status
Simulation time 113961483 ps
CPU time 3.59 seconds
Started Jun 29 05:15:42 PM PDT 24
Finished Jun 29 05:15:46 PM PDT 24
Peak memory 198728 kb
Host smart-66fb7161-4486-4c6d-b3a0-dece6563541a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820896030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3820896030
Directory /workspace/26.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/26.gpio_random_dout_din.1396318629
Short name T407
Test name
Test status
Simulation time 58532974 ps
CPU time 1.29 seconds
Started Jun 29 05:15:45 PM PDT 24
Finished Jun 29 05:15:46 PM PDT 24
Peak memory 197544 kb
Host smart-b71c6165-d8e3-47f6-95f1-758bf5c7e4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396318629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1396318629
Directory /workspace/26.gpio_random_dout_din/latest


Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.89968079
Short name T518
Test name
Test status
Simulation time 22364020 ps
CPU time 0.72 seconds
Started Jun 29 05:15:44 PM PDT 24
Finished Jun 29 05:15:45 PM PDT 24
Peak memory 195648 kb
Host smart-734f320e-f90f-4937-9462-f089a29d3218
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89968079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup_
pulldown.89968079
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3542149281
Short name T520
Test name
Test status
Simulation time 163234841 ps
CPU time 3.74 seconds
Started Jun 29 05:15:42 PM PDT 24
Finished Jun 29 05:15:47 PM PDT 24
Peak memory 198716 kb
Host smart-12c4cbb9-8bb6-4590-b031-8d775058f676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542149281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3542149281
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/26.gpio_smoke.1610836991
Short name T142
Test name
Test status
Simulation time 274063703 ps
CPU time 1.33 seconds
Started Jun 29 05:15:46 PM PDT 24
Finished Jun 29 05:15:48 PM PDT 24
Peak memory 197468 kb
Host smart-2539af83-aa3f-47be-96e6-f3955dd64128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610836991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1610836991
Directory /workspace/26.gpio_smoke/latest


Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.588831410
Short name T269
Test name
Test status
Simulation time 115743242 ps
CPU time 0.78 seconds
Started Jun 29 05:15:42 PM PDT 24
Finished Jun 29 05:15:43 PM PDT 24
Peak memory 195924 kb
Host smart-ff46c90d-6c98-4d46-948d-cd371eafbc3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588831410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.588831410
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/26.gpio_stress_all.3268785411
Short name T21
Test name
Test status
Simulation time 5722685264 ps
CPU time 58.22 seconds
Started Jun 29 05:15:48 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 198804 kb
Host smart-94179eba-7b89-47cc-a7f2-8f830283d57c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268785411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3268785411
Directory /workspace/26.gpio_stress_all/latest


Test location /workspace/coverage/default/27.gpio_alert_test.4083469925
Short name T299
Test name
Test status
Simulation time 23711289 ps
CPU time 0.58 seconds
Started Jun 29 05:15:50 PM PDT 24
Finished Jun 29 05:15:50 PM PDT 24
Peak memory 194580 kb
Host smart-b5dafe52-2ddd-4ffa-953b-6e5114846f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083469925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.4083469925
Directory /workspace/27.gpio_alert_test/latest


Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.219472995
Short name T255
Test name
Test status
Simulation time 86674866 ps
CPU time 0.78 seconds
Started Jun 29 05:15:52 PM PDT 24
Finished Jun 29 05:15:54 PM PDT 24
Peak memory 195760 kb
Host smart-eceefb24-e1b4-43d1-92ac-f452d702ec60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219472995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.219472995
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/27.gpio_filter_stress.2328810976
Short name T289
Test name
Test status
Simulation time 765612412 ps
CPU time 12.97 seconds
Started Jun 29 05:15:50 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 198660 kb
Host smart-8c893cb7-5b26-4fe0-9d53-0f71103bc032
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328810976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2328810976
Directory /workspace/27.gpio_filter_stress/latest


Test location /workspace/coverage/default/27.gpio_full_random.614988712
Short name T556
Test name
Test status
Simulation time 22698324 ps
CPU time 0.64 seconds
Started Jun 29 05:15:52 PM PDT 24
Finished Jun 29 05:15:53 PM PDT 24
Peak memory 195048 kb
Host smart-f25d1371-87f2-4f6a-b935-ac55a84ee415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614988712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.614988712
Directory /workspace/27.gpio_full_random/latest


Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.972343564
Short name T434
Test name
Test status
Simulation time 56203157 ps
CPU time 0.72 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:52 PM PDT 24
Peak memory 196732 kb
Host smart-059929a3-8b0c-41c8-aa85-ff5f385a8e8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972343564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.972343564
Directory /workspace/27.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.585773544
Short name T536
Test name
Test status
Simulation time 447100772 ps
CPU time 2.9 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:55 PM PDT 24
Peak memory 198704 kb
Host smart-95eb8b0c-2d88-4a5b-8cd5-e213d0c1b813
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585773544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.585773544
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2742459542
Short name T134
Test name
Test status
Simulation time 192992876 ps
CPU time 1.61 seconds
Started Jun 29 05:15:50 PM PDT 24
Finished Jun 29 05:15:52 PM PDT 24
Peak memory 196664 kb
Host smart-e53b42d1-7c03-4e76-9fe3-01ec12d07091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742459542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2742459542
Directory /workspace/27.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/27.gpio_random_dout_din.3596539841
Short name T331
Test name
Test status
Simulation time 115873496 ps
CPU time 1.26 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:53 PM PDT 24
Peak memory 196444 kb
Host smart-162ffeb8-fe9c-460c-af4b-eca626d00287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596539841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3596539841
Directory /workspace/27.gpio_random_dout_din/latest


Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1194563061
Short name T127
Test name
Test status
Simulation time 149553319 ps
CPU time 1.03 seconds
Started Jun 29 05:15:49 PM PDT 24
Finished Jun 29 05:15:51 PM PDT 24
Peak memory 197452 kb
Host smart-722f3626-dabb-4cc6-a8d3-10084215505f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194563061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1194563061
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2784800264
Short name T218
Test name
Test status
Simulation time 82307369 ps
CPU time 1.93 seconds
Started Jun 29 05:15:50 PM PDT 24
Finished Jun 29 05:15:52 PM PDT 24
Peak memory 198652 kb
Host smart-5b5547e2-adf3-44cd-adf4-630a79b24569
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784800264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2784800264
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/27.gpio_smoke.1090822488
Short name T175
Test name
Test status
Simulation time 109795335 ps
CPU time 1.04 seconds
Started Jun 29 05:15:44 PM PDT 24
Finished Jun 29 05:15:46 PM PDT 24
Peak memory 196244 kb
Host smart-94ed301c-c948-4daa-9af2-084edead04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090822488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1090822488
Directory /workspace/27.gpio_smoke/latest


Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1024769712
Short name T606
Test name
Test status
Simulation time 95084863 ps
CPU time 0.89 seconds
Started Jun 29 05:15:43 PM PDT 24
Finished Jun 29 05:15:45 PM PDT 24
Peak memory 197000 kb
Host smart-ad670ea8-bdfa-4354-ace8-caa519b6d31e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024769712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1024769712
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/27.gpio_stress_all.4079042368
Short name T613
Test name
Test status
Simulation time 91757631526 ps
CPU time 115.35 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:17:47 PM PDT 24
Peak memory 198800 kb
Host smart-4789663a-253b-4f6c-b37d-0bef034ec62c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079042368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4079042368
Directory /workspace/27.gpio_stress_all/latest


Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2418168069
Short name T602
Test name
Test status
Simulation time 79258048364 ps
CPU time 1667.99 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:43:41 PM PDT 24
Peak memory 198948 kb
Host smart-9552b9ef-daec-4db4-ae1f-c39467324599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2418168069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2418168069
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/28.gpio_alert_test.1379857817
Short name T473
Test name
Test status
Simulation time 16192563 ps
CPU time 0.6 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:52 PM PDT 24
Peak memory 194876 kb
Host smart-33260cb4-9306-4785-95c7-45c65589880c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379857817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1379857817
Directory /workspace/28.gpio_alert_test/latest


Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4157889751
Short name T479
Test name
Test status
Simulation time 52491029 ps
CPU time 0.95 seconds
Started Jun 29 05:15:54 PM PDT 24
Finished Jun 29 05:15:55 PM PDT 24
Peak memory 196624 kb
Host smart-e805c175-01f9-46e5-a5cb-3d4f88e6f7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157889751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4157889751
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/28.gpio_filter_stress.3087200068
Short name T207
Test name
Test status
Simulation time 644970758 ps
CPU time 16.45 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:16:08 PM PDT 24
Peak memory 197568 kb
Host smart-98746d02-973a-4e33-b31f-3b96ddeb9402
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087200068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3087200068
Directory /workspace/28.gpio_filter_stress/latest


Test location /workspace/coverage/default/28.gpio_full_random.348390677
Short name T24
Test name
Test status
Simulation time 170043471 ps
CPU time 0.77 seconds
Started Jun 29 05:15:53 PM PDT 24
Finished Jun 29 05:15:54 PM PDT 24
Peak memory 196484 kb
Host smart-5622ac1f-5a2b-4151-afcd-09dd8fc2850b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348390677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.348390677
Directory /workspace/28.gpio_full_random/latest


Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.279097424
Short name T199
Test name
Test status
Simulation time 476227392 ps
CPU time 1.52 seconds
Started Jun 29 05:15:50 PM PDT 24
Finished Jun 29 05:15:53 PM PDT 24
Peak memory 197712 kb
Host smart-9fe3ca2e-2717-45ef-9f87-61a6aba4c259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279097424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.279097424
Directory /workspace/28.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3958044274
Short name T622
Test name
Test status
Simulation time 307907909 ps
CPU time 3.08 seconds
Started Jun 29 05:15:49 PM PDT 24
Finished Jun 29 05:15:52 PM PDT 24
Peak memory 198744 kb
Host smart-cb4479d7-0b69-4574-8198-d384172e88da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958044274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3958044274
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2391570208
Short name T626
Test name
Test status
Simulation time 252597088 ps
CPU time 2.68 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:55 PM PDT 24
Peak memory 198576 kb
Host smart-00135691-7755-425e-ae74-f497a5facf6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391570208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2391570208
Directory /workspace/28.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/28.gpio_random_dout_din.1352111449
Short name T619
Test name
Test status
Simulation time 75736972 ps
CPU time 1 seconds
Started Jun 29 05:15:53 PM PDT 24
Finished Jun 29 05:15:55 PM PDT 24
Peak memory 197124 kb
Host smart-1603e2fc-1db4-4bc8-9550-81efef341b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352111449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1352111449
Directory /workspace/28.gpio_random_dout_din/latest


Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3751612983
Short name T129
Test name
Test status
Simulation time 127360025 ps
CPU time 1.37 seconds
Started Jun 29 05:15:49 PM PDT 24
Finished Jun 29 05:15:51 PM PDT 24
Peak memory 197264 kb
Host smart-4cae7e45-a492-4d9b-9981-d47cac899c5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751612983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3751612983
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3296942273
Short name T403
Test name
Test status
Simulation time 1006688135 ps
CPU time 4.64 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:57 PM PDT 24
Peak memory 198668 kb
Host smart-2cde6b45-a321-49e1-a825-a0e485110f0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296942273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3296942273
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/28.gpio_smoke.1868975616
Short name T601
Test name
Test status
Simulation time 108162523 ps
CPU time 1.05 seconds
Started Jun 29 05:15:50 PM PDT 24
Finished Jun 29 05:15:52 PM PDT 24
Peak memory 197080 kb
Host smart-0ad46a4c-ce46-4e00-8f57-444d2c5f57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868975616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1868975616
Directory /workspace/28.gpio_smoke/latest


Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3151254882
Short name T406
Test name
Test status
Simulation time 56872446 ps
CPU time 1.02 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:53 PM PDT 24
Peak memory 197252 kb
Host smart-3a8c44f5-a8f4-461a-835f-5003fbfab7ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151254882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3151254882
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/28.gpio_stress_all.580992227
Short name T350
Test name
Test status
Simulation time 1647478689 ps
CPU time 46.7 seconds
Started Jun 29 05:15:54 PM PDT 24
Finished Jun 29 05:16:41 PM PDT 24
Peak memory 198652 kb
Host smart-842770cb-afc2-479d-9340-066138270c2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580992227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.580992227
Directory /workspace/28.gpio_stress_all/latest


Test location /workspace/coverage/default/29.gpio_alert_test.606747836
Short name T310
Test name
Test status
Simulation time 23650645 ps
CPU time 0.65 seconds
Started Jun 29 05:15:53 PM PDT 24
Finished Jun 29 05:15:54 PM PDT 24
Peak memory 195300 kb
Host smart-dedc971a-daf3-4e18-800c-1e0a646fd600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606747836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.606747836
Directory /workspace/29.gpio_alert_test/latest


Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2791241111
Short name T376
Test name
Test status
Simulation time 25848585 ps
CPU time 0.79 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:53 PM PDT 24
Peak memory 196688 kb
Host smart-938811cb-bb35-43c6-ace6-3499aabb964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791241111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2791241111
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/29.gpio_filter_stress.2005024152
Short name T265
Test name
Test status
Simulation time 559305944 ps
CPU time 18.37 seconds
Started Jun 29 05:15:53 PM PDT 24
Finished Jun 29 05:16:12 PM PDT 24
Peak memory 196240 kb
Host smart-02c031c3-66bd-4981-ae8d-846c3896e7b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005024152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2005024152
Directory /workspace/29.gpio_filter_stress/latest


Test location /workspace/coverage/default/29.gpio_full_random.339374896
Short name T425
Test name
Test status
Simulation time 76229858 ps
CPU time 1.04 seconds
Started Jun 29 05:15:54 PM PDT 24
Finished Jun 29 05:15:55 PM PDT 24
Peak memory 197852 kb
Host smart-4862381a-c9c0-4e43-85e2-8b5fa662f0de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339374896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.339374896
Directory /workspace/29.gpio_full_random/latest


Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1578911311
Short name T356
Test name
Test status
Simulation time 41338369 ps
CPU time 0.87 seconds
Started Jun 29 05:15:54 PM PDT 24
Finished Jun 29 05:15:55 PM PDT 24
Peak memory 196808 kb
Host smart-edadf9b5-d83d-4451-b2f6-780140cb53a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578911311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1578911311
Directory /workspace/29.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3526447377
Short name T426
Test name
Test status
Simulation time 84732958 ps
CPU time 1.85 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:54 PM PDT 24
Peak memory 198768 kb
Host smart-e80c367b-6c41-48c0-bb74-7a32cc9e0e70
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526447377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3526447377
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3633243672
Short name T140
Test name
Test status
Simulation time 75758269 ps
CPU time 0.99 seconds
Started Jun 29 05:15:53 PM PDT 24
Finished Jun 29 05:15:54 PM PDT 24
Peak memory 196076 kb
Host smart-3d78a642-f100-488d-abfc-83934dafc52d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633243672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3633243672
Directory /workspace/29.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/29.gpio_random_dout_din.2060644653
Short name T290
Test name
Test status
Simulation time 69556987 ps
CPU time 0.66 seconds
Started Jun 29 05:15:54 PM PDT 24
Finished Jun 29 05:15:55 PM PDT 24
Peak memory 194976 kb
Host smart-b47c76e0-1fec-4eac-ac20-2a49d890d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060644653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2060644653
Directory /workspace/29.gpio_random_dout_din/latest


Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.151869521
Short name T597
Test name
Test status
Simulation time 32453873 ps
CPU time 1.17 seconds
Started Jun 29 05:15:50 PM PDT 24
Finished Jun 29 05:15:52 PM PDT 24
Peak memory 196540 kb
Host smart-167f5429-9826-4a97-9289-b5ca6e622810
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151869521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.151869521
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3977388775
Short name T549
Test name
Test status
Simulation time 692956512 ps
CPU time 4.39 seconds
Started Jun 29 05:15:53 PM PDT 24
Finished Jun 29 05:15:58 PM PDT 24
Peak memory 198652 kb
Host smart-44bc0a90-74db-4712-883c-dd43d3f082ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977388775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3977388775
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/29.gpio_smoke.2673354735
Short name T122
Test name
Test status
Simulation time 201843725 ps
CPU time 0.89 seconds
Started Jun 29 05:15:48 PM PDT 24
Finished Jun 29 05:15:49 PM PDT 24
Peak memory 195900 kb
Host smart-f84714ee-f8a6-4c96-958c-c7ae0b79087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673354735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2673354735
Directory /workspace/29.gpio_smoke/latest


Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.341906644
Short name T663
Test name
Test status
Simulation time 76473673 ps
CPU time 1.2 seconds
Started Jun 29 05:15:50 PM PDT 24
Finished Jun 29 05:15:51 PM PDT 24
Peak memory 196084 kb
Host smart-34efc016-e882-4af2-9732-07862bd7b5df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341906644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.341906644
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/29.gpio_stress_all.3409629937
Short name T147
Test name
Test status
Simulation time 18999074780 ps
CPU time 129.09 seconds
Started Jun 29 05:15:52 PM PDT 24
Finished Jun 29 05:18:02 PM PDT 24
Peak memory 198828 kb
Host smart-a912288c-3782-4c52-834a-ee62f820e5d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409629937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3409629937
Directory /workspace/29.gpio_stress_all/latest


Test location /workspace/coverage/default/3.gpio_alert_test.214127175
Short name T168
Test name
Test status
Simulation time 29002070 ps
CPU time 0.56 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:27 PM PDT 24
Peak memory 194652 kb
Host smart-80c46c25-29ff-431b-91aa-2c3edd20d957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214127175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.214127175
Directory /workspace/3.gpio_alert_test/latest


Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.571962186
Short name T377
Test name
Test status
Simulation time 44892495 ps
CPU time 0.92 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:27 PM PDT 24
Peak memory 197228 kb
Host smart-534d36ae-83da-4f3e-be15-ce24ccb5485b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571962186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.571962186
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/3.gpio_filter_stress.1332699710
Short name T631
Test name
Test status
Simulation time 469849047 ps
CPU time 24.31 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:50 PM PDT 24
Peak memory 197680 kb
Host smart-58f769c9-074b-460e-9006-353a74f6c3d0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332699710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1332699710
Directory /workspace/3.gpio_filter_stress/latest


Test location /workspace/coverage/default/3.gpio_full_random.4026015308
Short name T7
Test name
Test status
Simulation time 365922048 ps
CPU time 0.73 seconds
Started Jun 29 05:14:21 PM PDT 24
Finished Jun 29 05:14:22 PM PDT 24
Peak memory 195368 kb
Host smart-e85a3e3d-c2f7-4b42-b28d-03281b9ea7d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026015308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.4026015308
Directory /workspace/3.gpio_full_random/latest


Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1051849283
Short name T691
Test name
Test status
Simulation time 72460236 ps
CPU time 1.04 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 196668 kb
Host smart-dd05ba3a-ab71-40e4-a63f-f24585b6f5ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051849283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1051849283
Directory /workspace/3.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4232359111
Short name T253
Test name
Test status
Simulation time 45990547 ps
CPU time 0.98 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 196712 kb
Host smart-10258fa0-c255-45e2-9254-a4edad45f1a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232359111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4232359111
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2043262559
Short name T641
Test name
Test status
Simulation time 76892211 ps
CPU time 2.32 seconds
Started Jun 29 05:14:22 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 198728 kb
Host smart-a9ef4e41-6e4d-41fc-ba75-c143e37e022a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043262559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2043262559
Directory /workspace/3.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/3.gpio_random_dout_din.3675120981
Short name T153
Test name
Test status
Simulation time 164736396 ps
CPU time 0.92 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 196764 kb
Host smart-bd00724d-a9ed-4d3d-841f-82564e73c5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675120981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3675120981
Directory /workspace/3.gpio_random_dout_din/latest


Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.681666357
Short name T654
Test name
Test status
Simulation time 24860966 ps
CPU time 0.78 seconds
Started Jun 29 05:14:22 PM PDT 24
Finished Jun 29 05:14:23 PM PDT 24
Peak memory 196700 kb
Host smart-cbcd3e49-00f3-448e-8ebc-ab90efb730ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681666357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.681666357
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3147934060
Short name T504
Test name
Test status
Simulation time 113148025 ps
CPU time 1.94 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:28 PM PDT 24
Peak memory 198416 kb
Host smart-f0c8470e-917d-4cca-ac84-96d89b4d232b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147934060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3147934060
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/3.gpio_sec_cm.1972815542
Short name T65
Test name
Test status
Simulation time 136925509 ps
CPU time 0.81 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 214188 kb
Host smart-447549ba-b57d-428a-b80e-7f00ca3770fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972815542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1972815542
Directory /workspace/3.gpio_sec_cm/latest


Test location /workspace/coverage/default/3.gpio_smoke.3837021385
Short name T693
Test name
Test status
Simulation time 157734987 ps
CPU time 1.07 seconds
Started Jun 29 05:14:26 PM PDT 24
Finished Jun 29 05:14:28 PM PDT 24
Peak memory 196568 kb
Host smart-941acbdb-b9ff-4e1c-89ae-6df16020b40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837021385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3837021385
Directory /workspace/3.gpio_smoke/latest


Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1973544134
Short name T343
Test name
Test status
Simulation time 208915124 ps
CPU time 1.04 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 196428 kb
Host smart-af4dbf88-a6d1-4a67-bd2f-4af11057e7c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973544134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1973544134
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/3.gpio_stress_all.2270270256
Short name T206
Test name
Test status
Simulation time 15922815794 ps
CPU time 66.51 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:15:30 PM PDT 24
Peak memory 198808 kb
Host smart-20961bd3-3239-4bc3-859c-a67a448238fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270270256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2270270256
Directory /workspace/3.gpio_stress_all/latest


Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2418871329
Short name T74
Test name
Test status
Simulation time 49820728344 ps
CPU time 566.07 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:23:50 PM PDT 24
Peak memory 198924 kb
Host smart-c110fb3b-8dd3-42c8-9891-73e6083eba9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2418871329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2418871329
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/30.gpio_alert_test.3124490793
Short name T313
Test name
Test status
Simulation time 52969818 ps
CPU time 0.6 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:03 PM PDT 24
Peak memory 195204 kb
Host smart-6c682c7f-a100-44f6-8629-0e46f03fa5ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124490793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3124490793
Directory /workspace/30.gpio_alert_test/latest


Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3998898680
Short name T347
Test name
Test status
Simulation time 26099561 ps
CPU time 0.85 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 196848 kb
Host smart-22accc5a-cdde-4da3-b2df-1b594134c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998898680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3998898680
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/30.gpio_filter_stress.2594918711
Short name T562
Test name
Test status
Simulation time 176734252 ps
CPU time 9.33 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:16:14 PM PDT 24
Peak memory 197536 kb
Host smart-e7099244-0251-42e1-ba5b-c7f7f19d8cd6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594918711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2594918711
Directory /workspace/30.gpio_filter_stress/latest


Test location /workspace/coverage/default/30.gpio_full_random.4214541642
Short name T701
Test name
Test status
Simulation time 279096147 ps
CPU time 1.04 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 198676 kb
Host smart-9930f8b3-11ec-47db-a8b9-e41c2974e8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214541642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.4214541642
Directory /workspace/30.gpio_full_random/latest


Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3385970629
Short name T453
Test name
Test status
Simulation time 194767231 ps
CPU time 0.95 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 197388 kb
Host smart-8888d519-1de1-44a4-9761-6ed0b0fca704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385970629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3385970629
Directory /workspace/30.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3215242703
Short name T100
Test name
Test status
Simulation time 67309302 ps
CPU time 2.79 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 198768 kb
Host smart-ee09da63-ef8a-4383-8bd6-f547e34b839e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215242703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3215242703
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3535957317
Short name T274
Test name
Test status
Simulation time 179226451 ps
CPU time 2.3 seconds
Started Jun 29 05:16:01 PM PDT 24
Finished Jun 29 05:16:03 PM PDT 24
Peak memory 197864 kb
Host smart-893f6d52-ba9c-424c-8a63-34ef9dc99a3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535957317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3535957317
Directory /workspace/30.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/30.gpio_random_dout_din.449066984
Short name T220
Test name
Test status
Simulation time 56675080 ps
CPU time 1.08 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:53 PM PDT 24
Peak memory 196556 kb
Host smart-50a4469e-baa0-4055-a8c4-fe86c0c80eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449066984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.449066984
Directory /workspace/30.gpio_random_dout_din/latest


Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.751871061
Short name T103
Test name
Test status
Simulation time 239092887 ps
CPU time 1.31 seconds
Started Jun 29 05:15:52 PM PDT 24
Finished Jun 29 05:15:54 PM PDT 24
Peak memory 196576 kb
Host smart-ea6d4737-7bbf-43a8-8feb-a47f8dbb90ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751871061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.751871061
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4034244676
Short name T9
Test name
Test status
Simulation time 362533127 ps
CPU time 4.84 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:10 PM PDT 24
Peak memory 198648 kb
Host smart-8ab22255-af69-43ab-96d4-2b39b00f13b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034244676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4034244676
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/30.gpio_smoke.2871413990
Short name T579
Test name
Test status
Simulation time 146364127 ps
CPU time 1.09 seconds
Started Jun 29 05:15:52 PM PDT 24
Finished Jun 29 05:15:54 PM PDT 24
Peak memory 196264 kb
Host smart-7e829dbe-02a2-43f4-8cc2-ddd36cbb3675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871413990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2871413990
Directory /workspace/30.gpio_smoke/latest


Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1789409470
Short name T198
Test name
Test status
Simulation time 141043664 ps
CPU time 0.93 seconds
Started Jun 29 05:15:51 PM PDT 24
Finished Jun 29 05:15:53 PM PDT 24
Peak memory 196696 kb
Host smart-beb5a9c5-80d9-4230-a131-91315ae31a99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789409470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1789409470
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/30.gpio_stress_all.1530361761
Short name T388
Test name
Test status
Simulation time 7141789370 ps
CPU time 101.07 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:17:44 PM PDT 24
Peak memory 198712 kb
Host smart-f3b0601f-4c65-435b-9416-4959ec1f219f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530361761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1530361761
Directory /workspace/30.gpio_stress_all/latest


Test location /workspace/coverage/default/31.gpio_alert_test.4178604257
Short name T629
Test name
Test status
Simulation time 11579426 ps
CPU time 0.58 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 194628 kb
Host smart-df4f0da6-a3ef-4e1e-bdbf-1029b7beb45a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178604257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4178604257
Directory /workspace/31.gpio_alert_test/latest


Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.674891385
Short name T435
Test name
Test status
Simulation time 19271540 ps
CPU time 0.63 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:16:05 PM PDT 24
Peak memory 194632 kb
Host smart-2f872f29-8a6f-4722-a2bb-f451dd48cb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674891385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.674891385
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/31.gpio_filter_stress.2622900080
Short name T194
Test name
Test status
Simulation time 483293859 ps
CPU time 27.07 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:32 PM PDT 24
Peak memory 198568 kb
Host smart-90902552-c277-4a29-99c8-ecf699b77555
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622900080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2622900080
Directory /workspace/31.gpio_filter_stress/latest


Test location /workspace/coverage/default/31.gpio_full_random.4109980445
Short name T161
Test name
Test status
Simulation time 85000776 ps
CPU time 1.12 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 197320 kb
Host smart-f2a51145-7659-402a-99a1-a62d26bb33ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109980445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.4109980445
Directory /workspace/31.gpio_full_random/latest


Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3169192036
Short name T386
Test name
Test status
Simulation time 121715791 ps
CPU time 1.09 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 196800 kb
Host smart-e1a724b0-7f8a-4cd7-81e8-05d6e9e2366d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169192036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3169192036
Directory /workspace/31.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1926079418
Short name T17
Test name
Test status
Simulation time 78036100 ps
CPU time 3.24 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:08 PM PDT 24
Peak memory 198716 kb
Host smart-6b1014dd-d2fc-4458-a10b-0b3efef83d75
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926079418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1926079418
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1419125424
Short name T174
Test name
Test status
Simulation time 196781511 ps
CPU time 1.88 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:07 PM PDT 24
Peak memory 196636 kb
Host smart-10e35043-383f-4698-ab60-c38aef0146ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419125424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1419125424
Directory /workspace/31.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/31.gpio_random_dout_din.3746842897
Short name T37
Test name
Test status
Simulation time 116298703 ps
CPU time 1.02 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 197468 kb
Host smart-73bfa41f-b284-42da-925d-8a9a5258a2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746842897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3746842897
Directory /workspace/31.gpio_random_dout_din/latest


Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3032439710
Short name T543
Test name
Test status
Simulation time 118923730 ps
CPU time 1.26 seconds
Started Jun 29 05:16:05 PM PDT 24
Finished Jun 29 05:16:07 PM PDT 24
Peak memory 196440 kb
Host smart-07396186-427b-478a-b3ba-bbe8b7be5d87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032439710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3032439710
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3807057176
Short name T209
Test name
Test status
Simulation time 214416727 ps
CPU time 2.25 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:05 PM PDT 24
Peak memory 198692 kb
Host smart-e72ee64e-ab9e-4096-b127-4781350cf8d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807057176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3807057176
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/31.gpio_smoke.1720201567
Short name T176
Test name
Test status
Simulation time 135677743 ps
CPU time 1.18 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 197148 kb
Host smart-c78bb084-5e4d-45cf-a7bc-8a6b3d4ccb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720201567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1720201567
Directory /workspace/31.gpio_smoke/latest


Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.4126505391
Short name T395
Test name
Test status
Simulation time 274170939 ps
CPU time 1.4 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 197588 kb
Host smart-f4525741-5477-4549-b416-461c4777c5f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126505391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.4126505391
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/31.gpio_stress_all.519794731
Short name T459
Test name
Test status
Simulation time 18331169358 ps
CPU time 79.3 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:17:24 PM PDT 24
Peak memory 198804 kb
Host smart-f34347d9-2217-4de8-af6c-14dd01499bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519794731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.519794731
Directory /workspace/31.gpio_stress_all/latest


Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3093190674
Short name T72
Test name
Test status
Simulation time 31481098965 ps
CPU time 444.42 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:23:28 PM PDT 24
Peak memory 198940 kb
Host smart-5e107fb3-3910-4ab5-868c-c11d904668ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3093190674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3093190674
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/32.gpio_alert_test.1587209839
Short name T133
Test name
Test status
Simulation time 17311950 ps
CPU time 0.64 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:16:05 PM PDT 24
Peak memory 194692 kb
Host smart-71ec398f-26ea-419f-8c21-3a6e4643e950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587209839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1587209839
Directory /workspace/32.gpio_alert_test/latest


Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1800522011
Short name T358
Test name
Test status
Simulation time 46363566 ps
CPU time 0.83 seconds
Started Jun 29 05:16:05 PM PDT 24
Finished Jun 29 05:16:07 PM PDT 24
Peak memory 195812 kb
Host smart-3a6f9f71-8c94-4e41-a7b2-b92e4f0c5e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800522011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1800522011
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/32.gpio_filter_stress.43561095
Short name T648
Test name
Test status
Simulation time 1486940641 ps
CPU time 19.06 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:24 PM PDT 24
Peak memory 197280 kb
Host smart-85e13d75-747a-4e41-bcd4-b86a3fcc6db0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43561095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stress
.43561095
Directory /workspace/32.gpio_filter_stress/latest


Test location /workspace/coverage/default/32.gpio_full_random.2999031325
Short name T483
Test name
Test status
Simulation time 264841810 ps
CPU time 1.07 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 198512 kb
Host smart-30beb1eb-bc2a-4c47-8f9d-8c1a5c6336f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999031325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2999031325
Directory /workspace/32.gpio_full_random/latest


Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.996553656
Short name T615
Test name
Test status
Simulation time 90821566 ps
CPU time 0.96 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 198128 kb
Host smart-e56bb31f-3207-4ab2-abc4-d73de1f7394d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996553656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.996553656
Directory /workspace/32.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2389575349
Short name T574
Test name
Test status
Simulation time 50946650 ps
CPU time 2.11 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:05 PM PDT 24
Peak memory 198744 kb
Host smart-0fedc622-a4a3-46c6-b58a-143cc4488d79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389575349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2389575349
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1968751815
Short name T13
Test name
Test status
Simulation time 152468411 ps
CPU time 1.16 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 197048 kb
Host smart-799e2759-547f-415a-b48c-0626c0363113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968751815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1968751815
Directory /workspace/32.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/32.gpio_random_dout_din.2587220674
Short name T541
Test name
Test status
Simulation time 148401143 ps
CPU time 0.87 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:16:05 PM PDT 24
Peak memory 197144 kb
Host smart-b40ba276-11a6-49d1-9bff-507601331a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587220674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2587220674
Directory /workspace/32.gpio_random_dout_din/latest


Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3167720643
Short name T609
Test name
Test status
Simulation time 38031949 ps
CPU time 1.33 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 198740 kb
Host smart-4ed9ea2a-35a0-4f72-822c-6fe4365c809e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167720643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3167720643
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.915417833
Short name T235
Test name
Test status
Simulation time 472123433 ps
CPU time 2.58 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:08 PM PDT 24
Peak memory 198592 kb
Host smart-9d14cc3b-ee0e-44c6-ac4a-4a6be241f732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915417833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.915417833
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/32.gpio_smoke.1939101682
Short name T330
Test name
Test status
Simulation time 54013892 ps
CPU time 1.04 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 196368 kb
Host smart-9aa8e7ef-838f-4a2b-a48a-90f4113af5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939101682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1939101682
Directory /workspace/32.gpio_smoke/latest


Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2658819142
Short name T583
Test name
Test status
Simulation time 59653610 ps
CPU time 1.15 seconds
Started Jun 29 05:16:04 PM PDT 24
Finished Jun 29 05:16:06 PM PDT 24
Peak memory 196560 kb
Host smart-4014b22d-2e9e-43d5-997b-77fad7496d0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658819142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2658819142
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/32.gpio_stress_all.4149602755
Short name T589
Test name
Test status
Simulation time 38248774520 ps
CPU time 131.28 seconds
Started Jun 29 05:16:03 PM PDT 24
Finished Jun 29 05:18:15 PM PDT 24
Peak memory 198792 kb
Host smart-9c6c0a1e-519f-4657-a94f-e6171d7eff21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149602755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4149602755
Directory /workspace/32.gpio_stress_all/latest


Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.700286865
Short name T101
Test name
Test status
Simulation time 25405723268 ps
CPU time 720.89 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:28:04 PM PDT 24
Peak memory 198932 kb
Host smart-0949fcda-7cfe-4cd0-abbc-b2bd25ae1b63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=700286865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.700286865
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/33.gpio_alert_test.769436642
Short name T614
Test name
Test status
Simulation time 79444089 ps
CPU time 0.58 seconds
Started Jun 29 05:16:13 PM PDT 24
Finished Jun 29 05:16:14 PM PDT 24
Peak memory 194692 kb
Host smart-a5cf4446-7c8b-4bf2-b279-e97c2b9604db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769436642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.769436642
Directory /workspace/33.gpio_alert_test/latest


Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.141535939
Short name T526
Test name
Test status
Simulation time 87307455 ps
CPU time 0.94 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:20 PM PDT 24
Peak memory 197172 kb
Host smart-e008f34d-e5f5-473d-8757-5248e64fc02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141535939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.141535939
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/33.gpio_filter_stress.1811760333
Short name T666
Test name
Test status
Simulation time 15328821622 ps
CPU time 26.01 seconds
Started Jun 29 05:16:11 PM PDT 24
Finished Jun 29 05:16:37 PM PDT 24
Peak memory 197452 kb
Host smart-d8eb8572-0d2c-4de2-8227-3315af87224c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811760333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1811760333
Directory /workspace/33.gpio_filter_stress/latest


Test location /workspace/coverage/default/33.gpio_full_random.3623022401
Short name T193
Test name
Test status
Simulation time 227998421 ps
CPU time 0.82 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:20 PM PDT 24
Peak memory 196220 kb
Host smart-505bac5c-0195-40c8-913f-a4cd699d6e9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623022401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3623022401
Directory /workspace/33.gpio_full_random/latest


Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1459573261
Short name T560
Test name
Test status
Simulation time 17650171 ps
CPU time 0.71 seconds
Started Jun 29 05:16:17 PM PDT 24
Finished Jun 29 05:16:19 PM PDT 24
Peak memory 195700 kb
Host smart-238a1220-5cd0-47b5-9985-ec2f2251859f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459573261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1459573261
Directory /workspace/33.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3596210747
Short name T649
Test name
Test status
Simulation time 53530877 ps
CPU time 2.14 seconds
Started Jun 29 05:16:10 PM PDT 24
Finished Jun 29 05:16:13 PM PDT 24
Peak memory 198568 kb
Host smart-3dae14d5-c991-429a-b92f-5aa581bff3b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596210747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3596210747
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.197404685
Short name T421
Test name
Test status
Simulation time 131429260 ps
CPU time 1.04 seconds
Started Jun 29 05:16:19 PM PDT 24
Finished Jun 29 05:16:21 PM PDT 24
Peak memory 196772 kb
Host smart-ce6b22ff-3ed3-42b4-9582-c78bddfe2fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197404685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
197404685
Directory /workspace/33.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/33.gpio_random_dout_din.2667052057
Short name T689
Test name
Test status
Simulation time 16605290 ps
CPU time 0.65 seconds
Started Jun 29 05:16:11 PM PDT 24
Finished Jun 29 05:16:12 PM PDT 24
Peak memory 194924 kb
Host smart-1a556225-92ff-457f-8267-79c6cafeff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667052057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2667052057
Directory /workspace/33.gpio_random_dout_din/latest


Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3879656334
Short name T15
Test name
Test status
Simulation time 32545119 ps
CPU time 1.19 seconds
Started Jun 29 05:16:15 PM PDT 24
Finished Jun 29 05:16:17 PM PDT 24
Peak memory 196560 kb
Host smart-ed77e8e9-cce6-40f5-8927-d2841f9a60a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879656334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3879656334
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.438249121
Short name T501
Test name
Test status
Simulation time 246699369 ps
CPU time 4.33 seconds
Started Jun 29 05:16:13 PM PDT 24
Finished Jun 29 05:16:18 PM PDT 24
Peak memory 198684 kb
Host smart-747e90b5-1ed9-48a2-9639-fd7bb71fbb22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438249121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.438249121
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/33.gpio_smoke.2437634445
Short name T75
Test name
Test status
Simulation time 190859267 ps
CPU time 1.47 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 196252 kb
Host smart-64a29812-9647-4cae-a45b-4534292ef4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437634445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2437634445
Directory /workspace/33.gpio_smoke/latest


Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.517069660
Short name T225
Test name
Test status
Simulation time 30145212 ps
CPU time 0.98 seconds
Started Jun 29 05:16:02 PM PDT 24
Finished Jun 29 05:16:04 PM PDT 24
Peak memory 196124 kb
Host smart-661e9793-8f4b-4bb0-a8be-83779251c5ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517069660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.517069660
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/33.gpio_stress_all.3179755469
Short name T540
Test name
Test status
Simulation time 2370570332 ps
CPU time 60.82 seconds
Started Jun 29 05:16:12 PM PDT 24
Finished Jun 29 05:17:14 PM PDT 24
Peak memory 198760 kb
Host smart-15338cbe-acc2-401e-9bfe-57f71de80142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179755469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3179755469
Directory /workspace/33.gpio_stress_all/latest


Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2223140277
Short name T73
Test name
Test status
Simulation time 179397201252 ps
CPU time 488.57 seconds
Started Jun 29 05:16:19 PM PDT 24
Finished Jun 29 05:24:28 PM PDT 24
Peak memory 207076 kb
Host smart-183fb8eb-0ccb-49d6-ad1f-6ae84adf2828
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2223140277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2223140277
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/34.gpio_alert_test.2876708938
Short name T372
Test name
Test status
Simulation time 46916141 ps
CPU time 0.58 seconds
Started Jun 29 05:16:15 PM PDT 24
Finished Jun 29 05:16:16 PM PDT 24
Peak memory 194864 kb
Host smart-5c7092af-148d-4272-a543-0ed4421e57e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876708938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2876708938
Directory /workspace/34.gpio_alert_test/latest


Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4286412929
Short name T481
Test name
Test status
Simulation time 225634353 ps
CPU time 0.92 seconds
Started Jun 29 05:16:14 PM PDT 24
Finished Jun 29 05:16:16 PM PDT 24
Peak memory 197140 kb
Host smart-0c9590bf-b6fe-46b9-8c73-2f058299c949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286412929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4286412929
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/34.gpio_filter_stress.1936080016
Short name T11
Test name
Test status
Simulation time 467920124 ps
CPU time 24.21 seconds
Started Jun 29 05:16:12 PM PDT 24
Finished Jun 29 05:16:37 PM PDT 24
Peak memory 197696 kb
Host smart-c8b1d465-8368-4318-88ad-8e094370f26f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936080016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1936080016
Directory /workspace/34.gpio_filter_stress/latest


Test location /workspace/coverage/default/34.gpio_full_random.2949631294
Short name T240
Test name
Test status
Simulation time 68787155 ps
CPU time 0.96 seconds
Started Jun 29 05:16:13 PM PDT 24
Finished Jun 29 05:16:14 PM PDT 24
Peak memory 197868 kb
Host smart-dd882812-5984-4c51-94df-774d716ed4c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949631294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2949631294
Directory /workspace/34.gpio_full_random/latest


Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3737799588
Short name T301
Test name
Test status
Simulation time 92035175 ps
CPU time 1.28 seconds
Started Jun 29 05:16:14 PM PDT 24
Finished Jun 29 05:16:15 PM PDT 24
Peak memory 197356 kb
Host smart-136964eb-f020-47a9-aff2-1f10d2521bd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737799588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3737799588
Directory /workspace/34.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1331120473
Short name T480
Test name
Test status
Simulation time 111163811 ps
CPU time 1.31 seconds
Started Jun 29 05:16:14 PM PDT 24
Finished Jun 29 05:16:16 PM PDT 24
Peak memory 197344 kb
Host smart-832fcc26-60cc-45a2-a3a4-1fae053499dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331120473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1331120473
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.4249405333
Short name T178
Test name
Test status
Simulation time 119918110 ps
CPU time 1.54 seconds
Started Jun 29 05:16:11 PM PDT 24
Finished Jun 29 05:16:13 PM PDT 24
Peak memory 196504 kb
Host smart-c3ddbd3a-f70c-4570-857b-f9f06e6393fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249405333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.4249405333
Directory /workspace/34.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/34.gpio_random_dout_din.424017147
Short name T312
Test name
Test status
Simulation time 61649565 ps
CPU time 0.84 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:20 PM PDT 24
Peak memory 196588 kb
Host smart-d9bb83a4-58c6-460a-98db-6f5ba4342c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424017147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.424017147
Directory /workspace/34.gpio_random_dout_din/latest


Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4157831611
Short name T292
Test name
Test status
Simulation time 108270006 ps
CPU time 0.98 seconds
Started Jun 29 05:16:13 PM PDT 24
Finished Jun 29 05:16:15 PM PDT 24
Peak memory 197336 kb
Host smart-a6ea749d-a136-44d6-89a3-7c2139ddfd4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157831611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4157831611
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3731166800
Short name T474
Test name
Test status
Simulation time 443842169 ps
CPU time 5.36 seconds
Started Jun 29 05:16:09 PM PDT 24
Finished Jun 29 05:16:15 PM PDT 24
Peak memory 198720 kb
Host smart-50af0392-0883-4abe-a798-d33bc24d8ba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731166800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3731166800
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/34.gpio_smoke.530432318
Short name T487
Test name
Test status
Simulation time 61105792 ps
CPU time 1.17 seconds
Started Jun 29 05:16:12 PM PDT 24
Finished Jun 29 05:16:14 PM PDT 24
Peak memory 196316 kb
Host smart-2263968d-6022-4501-b884-bd4bacf8d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530432318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.530432318
Directory /workspace/34.gpio_smoke/latest


Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2814953477
Short name T414
Test name
Test status
Simulation time 149549413 ps
CPU time 1.29 seconds
Started Jun 29 05:16:12 PM PDT 24
Finished Jun 29 05:16:15 PM PDT 24
Peak memory 197552 kb
Host smart-52f3db15-3962-4a3f-b86b-7327e40a378e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814953477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2814953477
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/34.gpio_stress_all.2741777698
Short name T633
Test name
Test status
Simulation time 31451149496 ps
CPU time 86.28 seconds
Started Jun 29 05:16:15 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 198708 kb
Host smart-04d21ad1-a454-47e2-b056-78c1a987d316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741777698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2741777698
Directory /workspace/34.gpio_stress_all/latest


Test location /workspace/coverage/default/35.gpio_alert_test.1036836014
Short name T672
Test name
Test status
Simulation time 62309791 ps
CPU time 0.57 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:19 PM PDT 24
Peak memory 194608 kb
Host smart-dfe2de28-3116-4720-bd64-284e659583cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036836014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1036836014
Directory /workspace/35.gpio_alert_test/latest


Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3082521038
Short name T196
Test name
Test status
Simulation time 26929176 ps
CPU time 0.69 seconds
Started Jun 29 05:16:17 PM PDT 24
Finished Jun 29 05:16:19 PM PDT 24
Peak memory 194772 kb
Host smart-7c3af4b1-846d-4218-89ed-f99994431bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082521038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3082521038
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/35.gpio_filter_stress.715448528
Short name T204
Test name
Test status
Simulation time 455118191 ps
CPU time 14.24 seconds
Started Jun 29 05:16:12 PM PDT 24
Finished Jun 29 05:16:27 PM PDT 24
Peak memory 198696 kb
Host smart-e00e52cf-a6e9-4e64-b8de-0f60f02dac54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715448528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.715448528
Directory /workspace/35.gpio_filter_stress/latest


Test location /workspace/coverage/default/35.gpio_full_random.3965544454
Short name T673
Test name
Test status
Simulation time 286433621 ps
CPU time 1.07 seconds
Started Jun 29 05:16:16 PM PDT 24
Finished Jun 29 05:16:17 PM PDT 24
Peak memory 197312 kb
Host smart-1f7bfc7f-43e9-47ce-9314-f90d6e1dc629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965544454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3965544454
Directory /workspace/35.gpio_full_random/latest


Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2089198846
Short name T296
Test name
Test status
Simulation time 71331348 ps
CPU time 1.33 seconds
Started Jun 29 05:16:12 PM PDT 24
Finished Jun 29 05:16:15 PM PDT 24
Peak memory 198756 kb
Host smart-aae431f1-8e1e-46a9-a448-fa7459bcb36c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089198846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2089198846
Directory /workspace/35.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1709386025
Short name T432
Test name
Test status
Simulation time 477018834 ps
CPU time 3.8 seconds
Started Jun 29 05:16:12 PM PDT 24
Finished Jun 29 05:16:17 PM PDT 24
Peak memory 198708 kb
Host smart-e720a70d-3ea8-4d04-91ad-6e302f3e5430
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709386025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1709386025
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2432752724
Short name T125
Test name
Test status
Simulation time 35044272 ps
CPU time 0.94 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:19 PM PDT 24
Peak memory 196728 kb
Host smart-f42f020b-d66a-4036-8d45-9062d9730e6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432752724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2432752724
Directory /workspace/35.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/35.gpio_random_dout_din.146628955
Short name T505
Test name
Test status
Simulation time 139858479 ps
CPU time 0.9 seconds
Started Jun 29 05:16:15 PM PDT 24
Finished Jun 29 05:16:16 PM PDT 24
Peak memory 197864 kb
Host smart-8810928e-44d2-4277-a07b-803f605bc7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146628955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.146628955
Directory /workspace/35.gpio_random_dout_din/latest


Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2737737919
Short name T322
Test name
Test status
Simulation time 80716476 ps
CPU time 0.89 seconds
Started Jun 29 05:16:13 PM PDT 24
Finished Jun 29 05:16:15 PM PDT 24
Peak memory 197396 kb
Host smart-3303d94b-2ecf-4c67-88e2-ba88fb35c6d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737737919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2737737919
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1349366922
Short name T363
Test name
Test status
Simulation time 272017734 ps
CPU time 4.3 seconds
Started Jun 29 05:16:17 PM PDT 24
Finished Jun 29 05:16:22 PM PDT 24
Peak memory 198716 kb
Host smart-5f76f5f7-34d3-45e6-a7ec-576a33b18aa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349366922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1349366922
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/35.gpio_smoke.3694655451
Short name T33
Test name
Test status
Simulation time 576635348 ps
CPU time 1.36 seconds
Started Jun 29 05:16:17 PM PDT 24
Finished Jun 29 05:16:19 PM PDT 24
Peak memory 197456 kb
Host smart-5cd41563-02dd-4fc8-9b42-93445b6231e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694655451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3694655451
Directory /workspace/35.gpio_smoke/latest


Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3133360206
Short name T36
Test name
Test status
Simulation time 52408775 ps
CPU time 1.15 seconds
Started Jun 29 05:16:13 PM PDT 24
Finished Jun 29 05:16:15 PM PDT 24
Peak memory 196208 kb
Host smart-492f4b89-0376-429a-bdd5-7561d63905f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133360206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3133360206
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/35.gpio_stress_all.3917066428
Short name T438
Test name
Test status
Simulation time 20354158880 ps
CPU time 149.51 seconds
Started Jun 29 05:16:19 PM PDT 24
Finished Jun 29 05:18:49 PM PDT 24
Peak memory 198740 kb
Host smart-ac275ca7-3dd8-48c5-92ee-e489a782457c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917066428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3917066428
Directory /workspace/35.gpio_stress_all/latest


Test location /workspace/coverage/default/36.gpio_alert_test.3684597290
Short name T709
Test name
Test status
Simulation time 89022180 ps
CPU time 0.57 seconds
Started Jun 29 05:16:22 PM PDT 24
Finished Jun 29 05:16:23 PM PDT 24
Peak memory 195272 kb
Host smart-1f755026-a868-431b-925b-a3e47aa8939c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684597290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3684597290
Directory /workspace/36.gpio_alert_test/latest


Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4025584279
Short name T108
Test name
Test status
Simulation time 49504626 ps
CPU time 0.71 seconds
Started Jun 29 05:16:12 PM PDT 24
Finished Jun 29 05:16:13 PM PDT 24
Peak memory 195936 kb
Host smart-6ffe8fef-618a-4bce-be6a-b2c48adc5c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025584279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4025584279
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/36.gpio_filter_stress.3473900396
Short name T445
Test name
Test status
Simulation time 545213858 ps
CPU time 7.19 seconds
Started Jun 29 05:16:21 PM PDT 24
Finished Jun 29 05:16:28 PM PDT 24
Peak memory 197524 kb
Host smart-0e6745d5-3665-44f8-bc78-26e2adb8411c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473900396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3473900396
Directory /workspace/36.gpio_filter_stress/latest


Test location /workspace/coverage/default/36.gpio_full_random.1633021571
Short name T47
Test name
Test status
Simulation time 111982760 ps
CPU time 0.76 seconds
Started Jun 29 05:16:21 PM PDT 24
Finished Jun 29 05:16:22 PM PDT 24
Peak memory 196536 kb
Host smart-4eebf7aa-4216-4a94-84f4-b9624ac1d345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633021571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1633021571
Directory /workspace/36.gpio_full_random/latest


Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.722460872
Short name T138
Test name
Test status
Simulation time 104424016 ps
CPU time 1.5 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:20 PM PDT 24
Peak memory 197820 kb
Host smart-557cb735-67b7-4da9-9f64-8455dca0dfc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722460872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.722460872
Directory /workspace/36.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.944926052
Short name T652
Test name
Test status
Simulation time 87524125 ps
CPU time 3.55 seconds
Started Jun 29 05:16:13 PM PDT 24
Finished Jun 29 05:16:17 PM PDT 24
Peak memory 198748 kb
Host smart-2a720816-e7b1-44db-9826-bc23bc7d89e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944926052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.944926052
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1776090190
Short name T321
Test name
Test status
Simulation time 68444268 ps
CPU time 1.67 seconds
Started Jun 29 05:16:14 PM PDT 24
Finished Jun 29 05:16:16 PM PDT 24
Peak memory 197548 kb
Host smart-921144b8-9365-4c4b-8428-cda4c2c7dd5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776090190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1776090190
Directory /workspace/36.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/36.gpio_random_dout_din.3510686631
Short name T702
Test name
Test status
Simulation time 23568895 ps
CPU time 1.02 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:20 PM PDT 24
Peak memory 197480 kb
Host smart-93cf992d-a9bc-4456-83c8-5c75465c097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510686631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3510686631
Directory /workspace/36.gpio_random_dout_din/latest


Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3856225891
Short name T359
Test name
Test status
Simulation time 1117239566 ps
CPU time 1.32 seconds
Started Jun 29 05:16:11 PM PDT 24
Finished Jun 29 05:16:13 PM PDT 24
Peak memory 197816 kb
Host smart-94957e14-3f60-4ab3-905d-abb8c748e38d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856225891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3856225891
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.980633778
Short name T533
Test name
Test status
Simulation time 1054992882 ps
CPU time 4.51 seconds
Started Jun 29 05:16:20 PM PDT 24
Finished Jun 29 05:16:25 PM PDT 24
Peak memory 197956 kb
Host smart-da6e240b-d6ce-46ef-82b9-e7cca1d6a83a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980633778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.980633778
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/36.gpio_smoke.2084029151
Short name T391
Test name
Test status
Simulation time 62889077 ps
CPU time 0.75 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:20 PM PDT 24
Peak memory 195888 kb
Host smart-22e0c1a6-daf8-49db-80c2-1ee542f6a891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084029151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2084029151
Directory /workspace/36.gpio_smoke/latest


Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2612348435
Short name T244
Test name
Test status
Simulation time 66133205 ps
CPU time 1.2 seconds
Started Jun 29 05:16:16 PM PDT 24
Finished Jun 29 05:16:18 PM PDT 24
Peak memory 197232 kb
Host smart-0e5ab488-305b-42c4-ab49-fb7f8012751e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612348435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2612348435
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/36.gpio_stress_all.1938599000
Short name T439
Test name
Test status
Simulation time 8018372738 ps
CPU time 145.12 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:18:44 PM PDT 24
Peak memory 198804 kb
Host smart-85f39814-d35b-42d3-9b1f-9fc50e32edab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938599000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1938599000
Directory /workspace/36.gpio_stress_all/latest


Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3859727110
Short name T667
Test name
Test status
Simulation time 25219517026 ps
CPU time 455.03 seconds
Started Jun 29 05:16:20 PM PDT 24
Finished Jun 29 05:23:56 PM PDT 24
Peak memory 198872 kb
Host smart-69ebb2cd-4ff9-4f56-b66e-9ec8fdbb5f59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3859727110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3859727110
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/37.gpio_alert_test.1403025753
Short name T588
Test name
Test status
Simulation time 15139842 ps
CPU time 0.56 seconds
Started Jun 29 05:16:27 PM PDT 24
Finished Jun 29 05:16:27 PM PDT 24
Peak memory 194628 kb
Host smart-9c90c478-4cb1-4ca9-9207-bfc284a71ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403025753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1403025753
Directory /workspace/37.gpio_alert_test/latest


Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1804381565
Short name T522
Test name
Test status
Simulation time 18242906 ps
CPU time 0.73 seconds
Started Jun 29 05:16:20 PM PDT 24
Finished Jun 29 05:16:21 PM PDT 24
Peak memory 194876 kb
Host smart-43167be8-0068-4960-8097-639b3b192d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804381565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1804381565
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/37.gpio_filter_stress.3308867209
Short name T534
Test name
Test status
Simulation time 627867411 ps
CPU time 23.06 seconds
Started Jun 29 05:16:30 PM PDT 24
Finished Jun 29 05:16:54 PM PDT 24
Peak memory 197332 kb
Host smart-7a401ac4-233e-4ded-97e1-bfed7df76699
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308867209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3308867209
Directory /workspace/37.gpio_filter_stress/latest


Test location /workspace/coverage/default/37.gpio_full_random.2795734953
Short name T675
Test name
Test status
Simulation time 33229547 ps
CPU time 0.7 seconds
Started Jun 29 05:16:18 PM PDT 24
Finished Jun 29 05:16:19 PM PDT 24
Peak memory 195272 kb
Host smart-ba467a2f-3c2d-4592-8bc6-a6a390c8bb25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795734953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2795734953
Directory /workspace/37.gpio_full_random/latest


Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1119186213
Short name T187
Test name
Test status
Simulation time 48264043 ps
CPU time 0.65 seconds
Started Jun 29 05:16:19 PM PDT 24
Finished Jun 29 05:16:20 PM PDT 24
Peak memory 194984 kb
Host smart-f0aa5913-2fd9-4605-bc77-7d1c15c11472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119186213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1119186213
Directory /workspace/37.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1431011758
Short name T326
Test name
Test status
Simulation time 243139235 ps
CPU time 2.52 seconds
Started Jun 29 05:16:19 PM PDT 24
Finished Jun 29 05:16:22 PM PDT 24
Peak memory 197028 kb
Host smart-8a068efc-9b17-421f-a761-3e357f5a50e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431011758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1431011758
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1040675683
Short name T539
Test name
Test status
Simulation time 119112308 ps
CPU time 3.57 seconds
Started Jun 29 05:16:20 PM PDT 24
Finished Jun 29 05:16:24 PM PDT 24
Peak memory 198680 kb
Host smart-1c435613-8bbd-4940-ae8a-4a92292d78b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040675683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1040675683
Directory /workspace/37.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/37.gpio_random_dout_din.1459381486
Short name T515
Test name
Test status
Simulation time 223873664 ps
CPU time 0.92 seconds
Started Jun 29 05:16:21 PM PDT 24
Finished Jun 29 05:16:22 PM PDT 24
Peak memory 197132 kb
Host smart-4e6911ba-849f-4680-a32e-ea7b2b1deb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459381486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1459381486
Directory /workspace/37.gpio_random_dout_din/latest


Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2463515806
Short name T44
Test name
Test status
Simulation time 108392850 ps
CPU time 0.84 seconds
Started Jun 29 05:16:20 PM PDT 24
Finished Jun 29 05:16:21 PM PDT 24
Peak memory 197288 kb
Host smart-afca4cb9-8800-4973-bea7-50094056383a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463515806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2463515806
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1854433757
Short name T679
Test name
Test status
Simulation time 248837910 ps
CPU time 3.13 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:33 PM PDT 24
Peak memory 198660 kb
Host smart-59439de3-d135-4ff4-aecc-e10e7e8d2b49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854433757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1854433757
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/37.gpio_smoke.258110113
Short name T659
Test name
Test status
Simulation time 175645724 ps
CPU time 0.76 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 195920 kb
Host smart-ac66798b-5dd0-4a8c-b73f-5b1d8150d26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258110113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.258110113
Directory /workspace/37.gpio_smoke/latest


Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3236788986
Short name T705
Test name
Test status
Simulation time 58615917 ps
CPU time 0.91 seconds
Started Jun 29 05:16:21 PM PDT 24
Finished Jun 29 05:16:22 PM PDT 24
Peak memory 196124 kb
Host smart-28337839-93cd-4fc9-80d4-b78c1b10ac96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236788986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3236788986
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/37.gpio_stress_all.1688326930
Short name T203
Test name
Test status
Simulation time 21374758463 ps
CPU time 154.56 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:19:04 PM PDT 24
Peak memory 198816 kb
Host smart-a1a2d3a6-b034-4f91-bb9e-1a027d49a527
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688326930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1688326930
Directory /workspace/37.gpio_stress_all/latest


Test location /workspace/coverage/default/38.gpio_alert_test.1639151767
Short name T382
Test name
Test status
Simulation time 19572693 ps
CPU time 0.57 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 194660 kb
Host smart-815e9e7e-6701-432b-a884-a4d97e2d527a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639151767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1639151767
Directory /workspace/38.gpio_alert_test/latest


Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.940680430
Short name T121
Test name
Test status
Simulation time 154233639 ps
CPU time 0.78 seconds
Started Jun 29 05:16:27 PM PDT 24
Finished Jun 29 05:16:28 PM PDT 24
Peak memory 196012 kb
Host smart-797beb0e-e573-4b7f-bb4f-c3ed3aa5211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940680430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.940680430
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/38.gpio_filter_stress.3254179996
Short name T222
Test name
Test status
Simulation time 90514288 ps
CPU time 4.9 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:34 PM PDT 24
Peak memory 196964 kb
Host smart-13d225a6-886b-4c4a-8683-e2dd7ef4cb10
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254179996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3254179996
Directory /workspace/38.gpio_filter_stress/latest


Test location /workspace/coverage/default/38.gpio_full_random.3397066168
Short name T612
Test name
Test status
Simulation time 300152311 ps
CPU time 0.98 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 198584 kb
Host smart-9df32eb5-3d44-4cba-ac74-5dd26da38578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397066168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3397066168
Directory /workspace/38.gpio_full_random/latest


Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.489804751
Short name T686
Test name
Test status
Simulation time 61984327 ps
CPU time 1.07 seconds
Started Jun 29 05:16:30 PM PDT 24
Finished Jun 29 05:16:32 PM PDT 24
Peak memory 196892 kb
Host smart-c3f3652d-e6c5-4343-a275-94c69c6942e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489804751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.489804751
Directory /workspace/38.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3076702957
Short name T338
Test name
Test status
Simulation time 43640222 ps
CPU time 1.95 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:32 PM PDT 24
Peak memory 198800 kb
Host smart-61e0c3da-673a-4584-9086-b7063507b2fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076702957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3076702957
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2200892206
Short name T102
Test name
Test status
Simulation time 41469474 ps
CPU time 1.4 seconds
Started Jun 29 05:16:32 PM PDT 24
Finished Jun 29 05:16:34 PM PDT 24
Peak memory 196636 kb
Host smart-cdb96619-dd2f-49a7-bec5-e852ce1c8745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200892206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2200892206
Directory /workspace/38.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/38.gpio_random_dout_din.2614636621
Short name T172
Test name
Test status
Simulation time 79342073 ps
CPU time 0.86 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:31 PM PDT 24
Peak memory 198252 kb
Host smart-cf05227f-f182-442e-bf82-30193e6f087c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614636621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2614636621
Directory /workspace/38.gpio_random_dout_din/latest


Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1107976508
Short name T570
Test name
Test status
Simulation time 21623544 ps
CPU time 0.76 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:38 PM PDT 24
Peak memory 194908 kb
Host smart-f1dc88c7-5326-480d-9545-641c271c3aa8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107976508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1107976508
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1344181467
Short name T152
Test name
Test status
Simulation time 121204107 ps
CPU time 3.58 seconds
Started Jun 29 05:16:31 PM PDT 24
Finished Jun 29 05:16:35 PM PDT 24
Peak memory 198636 kb
Host smart-3f54aea0-e337-48db-a72a-904e442d670e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344181467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1344181467
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/38.gpio_smoke.3325033904
Short name T394
Test name
Test status
Simulation time 30429726 ps
CPU time 0.83 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:29 PM PDT 24
Peak memory 195904 kb
Host smart-4b42bf23-a09f-4a73-a0c0-1fa5f81bbd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325033904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3325033904
Directory /workspace/38.gpio_smoke/latest


Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3520358881
Short name T283
Test name
Test status
Simulation time 104057882 ps
CPU time 1.1 seconds
Started Jun 29 05:16:32 PM PDT 24
Finished Jun 29 05:16:33 PM PDT 24
Peak memory 196484 kb
Host smart-e8943dd6-53a1-495c-b557-60e08ce45aeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520358881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3520358881
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/38.gpio_stress_all.1204666947
Short name T572
Test name
Test status
Simulation time 20317829207 ps
CPU time 229.09 seconds
Started Jun 29 05:16:30 PM PDT 24
Finished Jun 29 05:20:20 PM PDT 24
Peak memory 198848 kb
Host smart-5dd16852-4c86-4d01-8ab1-d296af636a2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204666947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1204666947
Directory /workspace/38.gpio_stress_all/latest


Test location /workspace/coverage/default/39.gpio_alert_test.1968079926
Short name T231
Test name
Test status
Simulation time 39099223 ps
CPU time 0.56 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:38 PM PDT 24
Peak memory 194676 kb
Host smart-c84986fe-b5bd-4171-ae36-ddf9986622f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968079926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1968079926
Directory /workspace/39.gpio_alert_test/latest


Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2548284582
Short name T34
Test name
Test status
Simulation time 46702607 ps
CPU time 0.87 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 195956 kb
Host smart-896c7145-23eb-48f8-b4ef-a9a86db3e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548284582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2548284582
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/39.gpio_filter_stress.3987895309
Short name T277
Test name
Test status
Simulation time 677493093 ps
CPU time 24.47 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:55 PM PDT 24
Peak memory 198600 kb
Host smart-6633da4b-6aa8-4450-b3e3-b3d207ce8080
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987895309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3987895309
Directory /workspace/39.gpio_filter_stress/latest


Test location /workspace/coverage/default/39.gpio_full_random.1469741567
Short name T339
Test name
Test status
Simulation time 32169090 ps
CPU time 0.7 seconds
Started Jun 29 05:16:32 PM PDT 24
Finished Jun 29 05:16:33 PM PDT 24
Peak memory 195152 kb
Host smart-d1895dd1-6f35-4941-b842-6e65ca46010b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469741567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1469741567
Directory /workspace/39.gpio_full_random/latest


Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2537802405
Short name T430
Test name
Test status
Simulation time 331517570 ps
CPU time 1.13 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 196808 kb
Host smart-3e64f66d-e7e9-400d-8437-6a0f21b32837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537802405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2537802405
Directory /workspace/39.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1226695332
Short name T379
Test name
Test status
Simulation time 147486891 ps
CPU time 1.93 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 198772 kb
Host smart-b47d4a68-bd4f-468f-8571-0388e057e7db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226695332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1226695332
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2742412527
Short name T665
Test name
Test status
Simulation time 118375834 ps
CPU time 1.06 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 196132 kb
Host smart-3bfdf0d3-f09d-4423-adcd-ae6c935b66ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742412527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2742412527
Directory /workspace/39.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/39.gpio_random_dout_din.2481600061
Short name T710
Test name
Test status
Simulation time 38347652 ps
CPU time 0.9 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:29 PM PDT 24
Peak memory 197292 kb
Host smart-cb56f5be-782b-49eb-ae3f-a53ba929e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481600061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2481600061
Directory /workspace/39.gpio_random_dout_din/latest


Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2190916059
Short name T177
Test name
Test status
Simulation time 194894871 ps
CPU time 1.2 seconds
Started Jun 29 05:16:27 PM PDT 24
Finished Jun 29 05:16:29 PM PDT 24
Peak memory 196808 kb
Host smart-6b45f787-2ce8-4162-a59c-84f3e6272ab8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190916059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2190916059
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3789639903
Short name T357
Test name
Test status
Simulation time 48386966 ps
CPU time 1.26 seconds
Started Jun 29 05:16:30 PM PDT 24
Finished Jun 29 05:16:32 PM PDT 24
Peak memory 198684 kb
Host smart-1b850769-c93a-4dde-853d-c6c29ec12469
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789639903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3789639903
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/39.gpio_smoke.2185260787
Short name T646
Test name
Test status
Simulation time 35369906 ps
CPU time 0.86 seconds
Started Jun 29 05:16:31 PM PDT 24
Finished Jun 29 05:16:32 PM PDT 24
Peak memory 196688 kb
Host smart-0eb56634-f783-48b7-827a-cb84c3a8b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185260787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2185260787
Directory /workspace/39.gpio_smoke/latest


Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3713800953
Short name T545
Test name
Test status
Simulation time 323363314 ps
CPU time 1.46 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:39 PM PDT 24
Peak memory 196952 kb
Host smart-f185befb-99af-4eb7-8fb2-c933c4c23800
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713800953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3713800953
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/39.gpio_stress_all.2864317736
Short name T8
Test name
Test status
Simulation time 26498519515 ps
CPU time 70.82 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 198780 kb
Host smart-0b06ecc1-a806-4b65-8b36-e1da9dee533c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864317736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2864317736
Directory /workspace/39.gpio_stress_all/latest


Test location /workspace/coverage/default/4.gpio_alert_test.615819278
Short name T493
Test name
Test status
Simulation time 29888503 ps
CPU time 0.62 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:27 PM PDT 24
Peak memory 194908 kb
Host smart-ccf7e3cd-f5d3-45ab-9597-6681d872badc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615819278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.615819278
Directory /workspace/4.gpio_alert_test/latest


Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1600096497
Short name T600
Test name
Test status
Simulation time 33274614 ps
CPU time 0.82 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 196088 kb
Host smart-4a7fcf2f-2374-4ae6-91dd-f549754b91dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600096497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1600096497
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/4.gpio_filter_stress.1573007741
Short name T324
Test name
Test status
Simulation time 9704859328 ps
CPU time 21.04 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:47 PM PDT 24
Peak memory 197308 kb
Host smart-53174d06-6f13-4fc3-b235-69c64c29eb46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573007741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1573007741
Directory /workspace/4.gpio_filter_stress/latest


Test location /workspace/coverage/default/4.gpio_full_random.1991400762
Short name T489
Test name
Test status
Simulation time 21932534 ps
CPU time 0.68 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:27 PM PDT 24
Peak memory 195272 kb
Host smart-830d56df-ee98-473f-bb10-5d871651f65e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991400762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1991400762
Directory /workspace/4.gpio_full_random/latest


Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2605409036
Short name T436
Test name
Test status
Simulation time 68662834 ps
CPU time 1.05 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 196496 kb
Host smart-d14bff5e-ec0a-4c6c-8c79-3f2168bb4f81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605409036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2605409036
Directory /workspace/4.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1656807002
Short name T462
Test name
Test status
Simulation time 55500704 ps
CPU time 2.34 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 198568 kb
Host smart-db1db7f2-d186-47ec-9e0f-aeb2f9386bb1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656807002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1656807002
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3703154944
Short name T234
Test name
Test status
Simulation time 466691769 ps
CPU time 3.05 seconds
Started Jun 29 05:14:22 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 197776 kb
Host smart-f779cbb3-800d-4da9-a520-2b63fc97c53b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703154944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3703154944
Directory /workspace/4.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/4.gpio_random_dout_din.382571501
Short name T305
Test name
Test status
Simulation time 25031619 ps
CPU time 0.99 seconds
Started Jun 29 05:14:23 PM PDT 24
Finished Jun 29 05:14:25 PM PDT 24
Peak memory 197236 kb
Host smart-d7726e1f-3e75-4a76-9561-aa81e596a5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382571501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.382571501
Directory /workspace/4.gpio_random_dout_din/latest


Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3606112212
Short name T155
Test name
Test status
Simulation time 172025397 ps
CPU time 0.85 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:27 PM PDT 24
Peak memory 197192 kb
Host smart-905f2827-46b8-4621-b618-eb95331bc383
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606112212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3606112212
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3265295392
Short name T238
Test name
Test status
Simulation time 3899683128 ps
CPU time 4.4 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:31 PM PDT 24
Peak memory 198744 kb
Host smart-629cf35f-14bd-49a6-9ca7-2e14b6ff6e1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265295392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3265295392
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/4.gpio_sec_cm.357104763
Short name T54
Test name
Test status
Simulation time 339584895 ps
CPU time 0.96 seconds
Started Jun 29 05:14:21 PM PDT 24
Finished Jun 29 05:14:22 PM PDT 24
Peak memory 215452 kb
Host smart-78416dc8-5820-4358-a29b-462763af7cd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357104763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.357104763
Directory /workspace/4.gpio_sec_cm/latest


Test location /workspace/coverage/default/4.gpio_smoke.95590720
Short name T66
Test name
Test status
Simulation time 44740803 ps
CPU time 1.28 seconds
Started Jun 29 05:14:25 PM PDT 24
Finished Jun 29 05:14:27 PM PDT 24
Peak memory 197596 kb
Host smart-48f21cb7-cfc2-49e3-9455-daab43b0b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95590720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.95590720
Directory /workspace/4.gpio_smoke/latest


Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.810625426
Short name T124
Test name
Test status
Simulation time 157914195 ps
CPU time 1.02 seconds
Started Jun 29 05:14:24 PM PDT 24
Finished Jun 29 05:14:26 PM PDT 24
Peak memory 196468 kb
Host smart-96b2ed58-7b07-439b-948e-c0d91bbec376
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810625426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.810625426
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/4.gpio_stress_all.3755626805
Short name T360
Test name
Test status
Simulation time 9804513231 ps
CPU time 29.85 seconds
Started Jun 29 05:14:22 PM PDT 24
Finished Jun 29 05:14:52 PM PDT 24
Peak memory 198744 kb
Host smart-6ddb9982-9993-4e82-b84d-727e9edefd4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755626805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3755626805
Directory /workspace/4.gpio_stress_all/latest


Test location /workspace/coverage/default/40.gpio_alert_test.2383738783
Short name T261
Test name
Test status
Simulation time 44091292 ps
CPU time 0.57 seconds
Started Jun 29 05:16:38 PM PDT 24
Finished Jun 29 05:16:40 PM PDT 24
Peak memory 194676 kb
Host smart-a9b94c22-f3b0-46da-90b7-fdd7f7f3fe25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383738783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2383738783
Directory /workspace/40.gpio_alert_test/latest


Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1125895029
Short name T713
Test name
Test status
Simulation time 49958148 ps
CPU time 0.65 seconds
Started Jun 29 05:16:31 PM PDT 24
Finished Jun 29 05:16:32 PM PDT 24
Peak memory 194648 kb
Host smart-9dd439ee-c45a-4bff-b094-f2e7f4bb8b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125895029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1125895029
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/40.gpio_filter_stress.3782004640
Short name T692
Test name
Test status
Simulation time 277732308 ps
CPU time 9.64 seconds
Started Jun 29 05:16:34 PM PDT 24
Finished Jun 29 05:16:44 PM PDT 24
Peak memory 197628 kb
Host smart-4af4182a-c987-4554-a8c1-93bdb0c9e9d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782004640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3782004640
Directory /workspace/40.gpio_filter_stress/latest


Test location /workspace/coverage/default/40.gpio_full_random.343147296
Short name T132
Test name
Test status
Simulation time 88184223 ps
CPU time 0.64 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:37 PM PDT 24
Peak memory 194884 kb
Host smart-353f8dee-a9e0-4328-97d4-881c9c9cdde9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343147296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.343147296
Directory /workspace/40.gpio_full_random/latest


Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1775118874
Short name T566
Test name
Test status
Simulation time 196625285 ps
CPU time 1.27 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:31 PM PDT 24
Peak memory 197940 kb
Host smart-501f11e7-530a-4002-80f9-c98e6a31510e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775118874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1775118874
Directory /workspace/40.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3995412439
Short name T239
Test name
Test status
Simulation time 221339132 ps
CPU time 2.36 seconds
Started Jun 29 05:16:38 PM PDT 24
Finished Jun 29 05:16:41 PM PDT 24
Peak memory 198680 kb
Host smart-26742439-163f-486e-ad4d-e7010d71f708
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995412439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3995412439
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.964678022
Short name T596
Test name
Test status
Simulation time 375645346 ps
CPU time 2.21 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:31 PM PDT 24
Peak memory 198748 kb
Host smart-9fc53bd2-0c82-465d-b715-f6939b3f900c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964678022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
964678022
Directory /workspace/40.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/40.gpio_random_dout_din.3390414582
Short name T458
Test name
Test status
Simulation time 64931220 ps
CPU time 1.17 seconds
Started Jun 29 05:16:27 PM PDT 24
Finished Jun 29 05:16:28 PM PDT 24
Peak memory 197788 kb
Host smart-c6d8f217-6ba6-4d85-ae60-de2d40cfdb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390414582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3390414582
Directory /workspace/40.gpio_random_dout_din/latest


Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4176958331
Short name T431
Test name
Test status
Simulation time 13850112 ps
CPU time 0.63 seconds
Started Jun 29 05:16:29 PM PDT 24
Finished Jun 29 05:16:31 PM PDT 24
Peak memory 194928 kb
Host smart-5c17ccfd-bf7e-410f-9cc9-8982d860f3f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176958331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4176958331
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.4095484649
Short name T248
Test name
Test status
Simulation time 36771361 ps
CPU time 1.67 seconds
Started Jun 29 05:16:34 PM PDT 24
Finished Jun 29 05:16:36 PM PDT 24
Peak memory 198664 kb
Host smart-6e481eef-1a91-434c-96f3-55876b07f42f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095484649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.4095484649
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/40.gpio_smoke.2013854919
Short name T611
Test name
Test status
Simulation time 37505000 ps
CPU time 1.13 seconds
Started Jun 29 05:16:27 PM PDT 24
Finished Jun 29 05:16:28 PM PDT 24
Peak memory 196180 kb
Host smart-6bec9eaf-c42d-4c37-8120-24fa34897aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013854919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2013854919
Directory /workspace/40.gpio_smoke/latest


Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2474434990
Short name T205
Test name
Test status
Simulation time 141557844 ps
CPU time 1.28 seconds
Started Jun 29 05:16:28 PM PDT 24
Finished Jun 29 05:16:30 PM PDT 24
Peak memory 197468 kb
Host smart-b25cf6d6-4f76-4aae-9b90-db42abe51250
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474434990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2474434990
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/40.gpio_stress_all.1215564848
Short name T4
Test name
Test status
Simulation time 9162855249 ps
CPU time 98.47 seconds
Started Jun 29 05:16:37 PM PDT 24
Finished Jun 29 05:18:17 PM PDT 24
Peak memory 198768 kb
Host smart-9a4fcef4-a334-4bfa-b2f2-08401b0a83da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215564848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1215564848
Directory /workspace/40.gpio_stress_all/latest


Test location /workspace/coverage/default/41.gpio_alert_test.2624595536
Short name T63
Test name
Test status
Simulation time 14101597 ps
CPU time 0.62 seconds
Started Jun 29 05:16:39 PM PDT 24
Finished Jun 29 05:16:41 PM PDT 24
Peak memory 195600 kb
Host smart-81157c02-f6c5-42e0-9251-1b9155291298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624595536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2624595536
Directory /workspace/41.gpio_alert_test/latest


Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2729545211
Short name T308
Test name
Test status
Simulation time 39554379 ps
CPU time 0.82 seconds
Started Jun 29 05:16:39 PM PDT 24
Finished Jun 29 05:16:41 PM PDT 24
Peak memory 196080 kb
Host smart-0dd722e0-c5f2-48cb-a343-57a410c18e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729545211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2729545211
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/41.gpio_filter_stress.693189808
Short name T139
Test name
Test status
Simulation time 1431410514 ps
CPU time 18.83 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:57 PM PDT 24
Peak memory 196972 kb
Host smart-19a130df-873a-4141-aaca-2bbe9641497c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693189808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.693189808
Directory /workspace/41.gpio_filter_stress/latest


Test location /workspace/coverage/default/41.gpio_full_random.1876780098
Short name T23
Test name
Test status
Simulation time 71019524 ps
CPU time 0.93 seconds
Started Jun 29 05:16:35 PM PDT 24
Finished Jun 29 05:16:37 PM PDT 24
Peak memory 196672 kb
Host smart-f3e60cd2-80c6-4aa5-8f40-89afb407c1b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876780098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1876780098
Directory /workspace/41.gpio_full_random/latest


Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1938090697
Short name T236
Test name
Test status
Simulation time 140399124 ps
CPU time 1.13 seconds
Started Jun 29 05:16:38 PM PDT 24
Finished Jun 29 05:16:41 PM PDT 24
Peak memory 196788 kb
Host smart-ca97c733-ff91-4320-b4a4-5211b7e5addd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938090697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1938090697
Directory /workspace/41.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3831866074
Short name T676
Test name
Test status
Simulation time 283027374 ps
CPU time 2.9 seconds
Started Jun 29 05:16:35 PM PDT 24
Finished Jun 29 05:16:39 PM PDT 24
Peak memory 197016 kb
Host smart-ca1eb444-178a-44a2-8921-d4d12be211c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831866074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3831866074
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1944100008
Short name T650
Test name
Test status
Simulation time 41008398 ps
CPU time 1.24 seconds
Started Jun 29 05:16:35 PM PDT 24
Finished Jun 29 05:16:36 PM PDT 24
Peak memory 196348 kb
Host smart-47982d3a-ce64-486a-8baf-ca99d5a7fbba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944100008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1944100008
Directory /workspace/41.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/41.gpio_random_dout_din.2023793887
Short name T285
Test name
Test status
Simulation time 202310821 ps
CPU time 1.04 seconds
Started Jun 29 05:16:38 PM PDT 24
Finished Jun 29 05:16:40 PM PDT 24
Peak memory 196680 kb
Host smart-5c5ef2a6-ede5-47a7-8960-275dc0f88e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023793887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2023793887
Directory /workspace/41.gpio_random_dout_din/latest


Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.275508075
Short name T279
Test name
Test status
Simulation time 244773374 ps
CPU time 1.31 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:39 PM PDT 24
Peak memory 198708 kb
Host smart-779c3174-600c-4f65-857b-b686eb31a986
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275508075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.275508075
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.132072627
Short name T538
Test name
Test status
Simulation time 1696653668 ps
CPU time 5.8 seconds
Started Jun 29 05:16:34 PM PDT 24
Finished Jun 29 05:16:41 PM PDT 24
Peak memory 198544 kb
Host smart-36185544-90e5-4a06-93ad-9934cdb54d78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132072627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.132072627
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/41.gpio_smoke.3319769197
Short name T552
Test name
Test status
Simulation time 149048633 ps
CPU time 1.35 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:38 PM PDT 24
Peak memory 196608 kb
Host smart-2fd35734-8511-48db-ba87-106b961fbb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319769197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3319769197
Directory /workspace/41.gpio_smoke/latest


Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.516359497
Short name T495
Test name
Test status
Simulation time 191071648 ps
CPU time 0.91 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:39 PM PDT 24
Peak memory 196048 kb
Host smart-6317636c-61da-4452-8245-41e62b577427
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516359497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.516359497
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/41.gpio_stress_all.3832770113
Short name T677
Test name
Test status
Simulation time 6711946709 ps
CPU time 36.43 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:17:13 PM PDT 24
Peak memory 198744 kb
Host smart-204d1f29-29c1-411a-86a6-c09af0e20dbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832770113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3832770113
Directory /workspace/41.gpio_stress_all/latest


Test location /workspace/coverage/default/42.gpio_alert_test.786379261
Short name T714
Test name
Test status
Simulation time 12195838 ps
CPU time 0.6 seconds
Started Jun 29 05:16:39 PM PDT 24
Finished Jun 29 05:16:41 PM PDT 24
Peak memory 195372 kb
Host smart-d7978415-c021-41ec-a800-f39070a02d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786379261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.786379261
Directory /workspace/42.gpio_alert_test/latest


Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3348879582
Short name T351
Test name
Test status
Simulation time 23950536 ps
CPU time 0.75 seconds
Started Jun 29 05:16:37 PM PDT 24
Finished Jun 29 05:16:39 PM PDT 24
Peak memory 196068 kb
Host smart-4afc385d-cf53-458a-bba7-52aadaebeba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348879582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3348879582
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/42.gpio_filter_stress.2252106955
Short name T567
Test name
Test status
Simulation time 324571277 ps
CPU time 11.46 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:49 PM PDT 24
Peak memory 197580 kb
Host smart-1035e82b-e698-459c-996f-8cbecfb9a12e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252106955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2252106955
Directory /workspace/42.gpio_filter_stress/latest


Test location /workspace/coverage/default/42.gpio_full_random.2950084631
Short name T389
Test name
Test status
Simulation time 64003468 ps
CPU time 1.03 seconds
Started Jun 29 05:16:38 PM PDT 24
Finished Jun 29 05:16:41 PM PDT 24
Peak memory 197104 kb
Host smart-490f6bb0-124a-46a8-af22-c314a11effad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950084631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2950084631
Directory /workspace/42.gpio_full_random/latest


Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2033344369
Short name T472
Test name
Test status
Simulation time 76604294 ps
CPU time 1.19 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:38 PM PDT 24
Peak memory 196716 kb
Host smart-acb637f3-3efd-4d23-887c-f104ab432d98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033344369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2033344369
Directory /workspace/42.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3765215278
Short name T320
Test name
Test status
Simulation time 398699578 ps
CPU time 2.71 seconds
Started Jun 29 05:16:38 PM PDT 24
Finished Jun 29 05:16:42 PM PDT 24
Peak memory 198652 kb
Host smart-f43d3718-185a-43a4-b56d-70ca58800209
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765215278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3765215278
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.781708387
Short name T143
Test name
Test status
Simulation time 99346330 ps
CPU time 2.86 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:40 PM PDT 24
Peak memory 197840 kb
Host smart-dc2abe55-d5fe-4fd1-87ce-bfef8065cb02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781708387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
781708387
Directory /workspace/42.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/42.gpio_random_dout_din.2650985900
Short name T131
Test name
Test status
Simulation time 43349710 ps
CPU time 1.08 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:39 PM PDT 24
Peak memory 197444 kb
Host smart-33b66811-d28c-454b-81ea-6158d13db6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650985900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2650985900
Directory /workspace/42.gpio_random_dout_din/latest


Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.209617942
Short name T616
Test name
Test status
Simulation time 62904581 ps
CPU time 1.18 seconds
Started Jun 29 05:16:35 PM PDT 24
Finished Jun 29 05:16:36 PM PDT 24
Peak memory 198016 kb
Host smart-afd7d8dc-937a-469f-b3c3-c4eb4d84a49e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209617942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.209617942
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.771046548
Short name T20
Test name
Test status
Simulation time 815347274 ps
CPU time 5.36 seconds
Started Jun 29 05:16:38 PM PDT 24
Finished Jun 29 05:16:45 PM PDT 24
Peak memory 198676 kb
Host smart-8169a52e-b5ff-49c9-b84e-1839c5379a55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771046548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.771046548
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/42.gpio_smoke.2671777276
Short name T681
Test name
Test status
Simulation time 67015774 ps
CPU time 0.87 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:37 PM PDT 24
Peak memory 196064 kb
Host smart-0dd95c3c-4bd5-4765-81a3-0f81c4e3cdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671777276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2671777276
Directory /workspace/42.gpio_smoke/latest


Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2942128010
Short name T275
Test name
Test status
Simulation time 35581605 ps
CPU time 1.09 seconds
Started Jun 29 05:16:37 PM PDT 24
Finished Jun 29 05:16:40 PM PDT 24
Peak memory 196504 kb
Host smart-aeb5bb01-22d2-4151-a84d-66f52be05928
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942128010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2942128010
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/42.gpio_stress_all.404769267
Short name T249
Test name
Test status
Simulation time 13133080635 ps
CPU time 145.8 seconds
Started Jun 29 05:16:35 PM PDT 24
Finished Jun 29 05:19:01 PM PDT 24
Peak memory 198824 kb
Host smart-c4fd4926-2772-439d-8078-eee96fef8738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404769267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.404769267
Directory /workspace/42.gpio_stress_all/latest


Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.4066089142
Short name T644
Test name
Test status
Simulation time 83656546719 ps
CPU time 833.53 seconds
Started Jun 29 05:16:37 PM PDT 24
Finished Jun 29 05:30:32 PM PDT 24
Peak memory 198932 kb
Host smart-f3de23dc-edff-471e-af31-b754a94bfbef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4066089142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.4066089142
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/43.gpio_alert_test.1453471208
Short name T348
Test name
Test status
Simulation time 110721448 ps
CPU time 0.56 seconds
Started Jun 29 05:16:45 PM PDT 24
Finished Jun 29 05:16:46 PM PDT 24
Peak memory 195380 kb
Host smart-775d4698-3891-4f32-8513-f41be90adc02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453471208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1453471208
Directory /workspace/43.gpio_alert_test/latest


Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2918187909
Short name T678
Test name
Test status
Simulation time 81522631 ps
CPU time 0.87 seconds
Started Jun 29 05:16:47 PM PDT 24
Finished Jun 29 05:16:48 PM PDT 24
Peak memory 196128 kb
Host smart-7c8b228b-7408-4593-9e8e-cc8387a92274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918187909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2918187909
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/43.gpio_filter_stress.1205402134
Short name T617
Test name
Test status
Simulation time 591778656 ps
CPU time 20.59 seconds
Started Jun 29 05:16:46 PM PDT 24
Finished Jun 29 05:17:07 PM PDT 24
Peak memory 196188 kb
Host smart-3710fe82-ea92-4c58-8b94-12559a80b9ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205402134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1205402134
Directory /workspace/43.gpio_filter_stress/latest


Test location /workspace/coverage/default/43.gpio_full_random.2395988683
Short name T640
Test name
Test status
Simulation time 77375896 ps
CPU time 0.64 seconds
Started Jun 29 05:16:46 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 195644 kb
Host smart-0aec25c9-b4fb-4ac6-b40c-c5ada918d8b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395988683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2395988683
Directory /workspace/43.gpio_full_random/latest


Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3437697405
Short name T30
Test name
Test status
Simulation time 22294101 ps
CPU time 0.7 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:46 PM PDT 24
Peak memory 195436 kb
Host smart-4f3ff3ac-48ce-4903-873d-23f277d54aa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437697405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3437697405
Directory /workspace/43.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3200470547
Short name T460
Test name
Test status
Simulation time 151888944 ps
CPU time 1.67 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 198672 kb
Host smart-43d39615-c4f6-4d20-9beb-8b92266be799
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200470547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3200470547
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3827576645
Short name T585
Test name
Test status
Simulation time 57119541 ps
CPU time 1.89 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 196440 kb
Host smart-d32e26b5-a9ad-40de-b375-0ad172d8b286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827576645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3827576645
Directory /workspace/43.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/43.gpio_random_dout_din.3235410522
Short name T669
Test name
Test status
Simulation time 53501125 ps
CPU time 1.08 seconds
Started Jun 29 05:16:45 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 196572 kb
Host smart-bb887ff4-6133-4645-a8c0-d462a46bd06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235410522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3235410522
Directory /workspace/43.gpio_random_dout_din/latest


Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1439570978
Short name T506
Test name
Test status
Simulation time 44667191 ps
CPU time 0.93 seconds
Started Jun 29 05:16:46 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 196772 kb
Host smart-351b40d1-633d-41ba-b58b-0b1b0fd1567b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439570978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1439570978
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2929528908
Short name T18
Test name
Test status
Simulation time 493601666 ps
CPU time 3.75 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:49 PM PDT 24
Peak memory 198680 kb
Host smart-8be34c2f-bac7-4d5d-bd80-b20f19c164bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929528908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2929528908
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/43.gpio_smoke.886769218
Short name T683
Test name
Test status
Simulation time 59340005 ps
CPU time 1.21 seconds
Started Jun 29 05:16:38 PM PDT 24
Finished Jun 29 05:16:40 PM PDT 24
Peak memory 197260 kb
Host smart-775f1cd4-ab6a-4f89-a1ee-1967ac79033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886769218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.886769218
Directory /workspace/43.gpio_smoke/latest


Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1238740238
Short name T333
Test name
Test status
Simulation time 29820798 ps
CPU time 0.76 seconds
Started Jun 29 05:16:36 PM PDT 24
Finished Jun 29 05:16:38 PM PDT 24
Peak memory 195908 kb
Host smart-25fef709-d525-4a8e-9af7-a4c869560276
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238740238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1238740238
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/43.gpio_stress_all.1525961322
Short name T670
Test name
Test status
Simulation time 5797429780 ps
CPU time 157.98 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:19:23 PM PDT 24
Peak memory 198816 kb
Host smart-54bbcb19-a1a3-4c9b-bd89-1af40f1d75cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525961322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1525961322
Directory /workspace/43.gpio_stress_all/latest


Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3723239805
Short name T694
Test name
Test status
Simulation time 51220204201 ps
CPU time 1162.02 seconds
Started Jun 29 05:16:47 PM PDT 24
Finished Jun 29 05:36:09 PM PDT 24
Peak memory 198980 kb
Host smart-5f329435-ed56-4413-8850-ea6b35ebf79a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3723239805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3723239805
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/44.gpio_alert_test.553112826
Short name T55
Test name
Test status
Simulation time 12384300 ps
CPU time 0.61 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:46 PM PDT 24
Peak memory 194676 kb
Host smart-22faf743-d13d-4605-9c41-03943f19b8e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553112826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.553112826
Directory /workspace/44.gpio_alert_test/latest


Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2946544511
Short name T503
Test name
Test status
Simulation time 40110199 ps
CPU time 0.84 seconds
Started Jun 29 05:16:47 PM PDT 24
Finished Jun 29 05:16:48 PM PDT 24
Peak memory 197048 kb
Host smart-14a2c2d1-c579-45c8-b38b-52494335f502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946544511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2946544511
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/44.gpio_filter_stress.1560693078
Short name T173
Test name
Test status
Simulation time 1266132643 ps
CPU time 16.4 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:17:01 PM PDT 24
Peak memory 197508 kb
Host smart-3adb3949-c0a7-4ae5-a49d-cb454d2bc61b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560693078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1560693078
Directory /workspace/44.gpio_filter_stress/latest


Test location /workspace/coverage/default/44.gpio_full_random.1331280086
Short name T268
Test name
Test status
Simulation time 429775662 ps
CPU time 0.8 seconds
Started Jun 29 05:16:46 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 195436 kb
Host smart-6ceca3ee-4dad-4182-b6a3-deb266b8fbcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331280086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1331280086
Directory /workspace/44.gpio_full_random/latest


Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.68171959
Short name T12
Test name
Test status
Simulation time 47879253 ps
CPU time 1.02 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 197420 kb
Host smart-700db7af-40c5-413b-881c-8950e1a1de16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68171959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.68171959
Directory /workspace/44.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2778447407
Short name T684
Test name
Test status
Simulation time 183214847 ps
CPU time 3.47 seconds
Started Jun 29 05:16:43 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 198744 kb
Host smart-db3c1452-0eca-4e6f-b1db-d462f61b45ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778447407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2778447407
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2070656313
Short name T627
Test name
Test status
Simulation time 359747948 ps
CPU time 3.09 seconds
Started Jun 29 05:16:46 PM PDT 24
Finished Jun 29 05:16:50 PM PDT 24
Peak memory 198740 kb
Host smart-e8691e93-3584-418a-9e67-0f732c21e781
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070656313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2070656313
Directory /workspace/44.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/44.gpio_random_dout_din.2438747514
Short name T664
Test name
Test status
Simulation time 58622587 ps
CPU time 1.19 seconds
Started Jun 29 05:16:46 PM PDT 24
Finished Jun 29 05:16:48 PM PDT 24
Peak memory 197784 kb
Host smart-da7e496d-7107-4fc1-b3f1-988b48f311f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438747514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2438747514
Directory /workspace/44.gpio_random_dout_din/latest


Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1324803010
Short name T408
Test name
Test status
Simulation time 177647060 ps
CPU time 1.15 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 196808 kb
Host smart-e6ac980a-c279-4a0c-920e-8fee7eb3883d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324803010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1324803010
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2841080492
Short name T466
Test name
Test status
Simulation time 46107192 ps
CPU time 1.94 seconds
Started Jun 29 05:16:43 PM PDT 24
Finished Jun 29 05:16:45 PM PDT 24
Peak memory 198684 kb
Host smart-791594f5-eee7-4563-bfe9-2543a93a346d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841080492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2841080492
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/44.gpio_smoke.3896880102
Short name T551
Test name
Test status
Simulation time 153953366 ps
CPU time 1.09 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 196444 kb
Host smart-ea5178ce-8699-4630-a837-354b7e872ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896880102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3896880102
Directory /workspace/44.gpio_smoke/latest


Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.4246305151
Short name T284
Test name
Test status
Simulation time 86801569 ps
CPU time 1.28 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 196576 kb
Host smart-5155b62b-87c4-459a-a9c6-488955180c46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246305151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.4246305151
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/44.gpio_stress_all.4255605671
Short name T443
Test name
Test status
Simulation time 13266012255 ps
CPU time 81.04 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:18:06 PM PDT 24
Peak memory 198660 kb
Host smart-8598ef62-82da-405b-823c-5968811932f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255605671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4255605671
Directory /workspace/44.gpio_stress_all/latest


Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3694247553
Short name T68
Test name
Test status
Simulation time 423196411987 ps
CPU time 1598.15 seconds
Started Jun 29 05:16:45 PM PDT 24
Finished Jun 29 05:43:24 PM PDT 24
Peak memory 198980 kb
Host smart-0d4d84ea-1124-4bc1-a695-275148952b06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3694247553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3694247553
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/45.gpio_alert_test.2062020950
Short name T524
Test name
Test status
Simulation time 13717547 ps
CPU time 0.58 seconds
Started Jun 29 05:16:53 PM PDT 24
Finished Jun 29 05:16:53 PM PDT 24
Peak memory 194680 kb
Host smart-10a7207b-738e-4ae1-8ebc-1835a1311798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062020950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2062020950
Directory /workspace/45.gpio_alert_test/latest


Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.251046640
Short name T224
Test name
Test status
Simulation time 46148242 ps
CPU time 0.63 seconds
Started Jun 29 05:16:45 PM PDT 24
Finished Jun 29 05:16:47 PM PDT 24
Peak memory 195268 kb
Host smart-f5f429d3-53fa-4398-82be-68242f7c98be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251046640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.251046640
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/45.gpio_filter_stress.1380987255
Short name T608
Test name
Test status
Simulation time 796844959 ps
CPU time 21.2 seconds
Started Jun 29 05:16:53 PM PDT 24
Finished Jun 29 05:17:15 PM PDT 24
Peak memory 197424 kb
Host smart-ad3250b0-f45e-4d62-8a27-b8675f647277
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380987255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1380987255
Directory /workspace/45.gpio_filter_stress/latest


Test location /workspace/coverage/default/45.gpio_full_random.1556163875
Short name T19
Test name
Test status
Simulation time 385720977 ps
CPU time 0.99 seconds
Started Jun 29 05:16:53 PM PDT 24
Finished Jun 29 05:16:54 PM PDT 24
Peak memory 197152 kb
Host smart-25d5187f-5579-4ab5-8b82-8494fb30d056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556163875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1556163875
Directory /workspace/45.gpio_full_random/latest


Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4101062329
Short name T509
Test name
Test status
Simulation time 307773264 ps
CPU time 1.42 seconds
Started Jun 29 05:16:41 PM PDT 24
Finished Jun 29 05:16:43 PM PDT 24
Peak memory 197232 kb
Host smart-59faab18-5554-498f-a1b8-82da47101f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101062329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4101062329
Directory /workspace/45.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.37555882
Short name T398
Test name
Test status
Simulation time 19348632 ps
CPU time 0.94 seconds
Started Jun 29 05:16:51 PM PDT 24
Finished Jun 29 05:16:53 PM PDT 24
Peak memory 196812 kb
Host smart-d88cc4e6-41bc-4e1f-8ebe-5af5efcc9b3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.gpio_intr_with_filter_rand_intr_event.37555882
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.701717457
Short name T186
Test name
Test status
Simulation time 151005853 ps
CPU time 3.15 seconds
Started Jun 29 05:16:54 PM PDT 24
Finished Jun 29 05:16:58 PM PDT 24
Peak memory 198740 kb
Host smart-49efef39-272b-4132-8533-7d74a9d3b700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701717457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
701717457
Directory /workspace/45.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/45.gpio_random_dout_din.3353122537
Short name T516
Test name
Test status
Simulation time 22265536 ps
CPU time 0.78 seconds
Started Jun 29 05:16:42 PM PDT 24
Finished Jun 29 05:16:44 PM PDT 24
Peak memory 197856 kb
Host smart-45a62442-4f9c-4d00-8eac-330a696f5716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353122537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3353122537
Directory /workspace/45.gpio_random_dout_din/latest


Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2381687009
Short name T634
Test name
Test status
Simulation time 43125385 ps
CPU time 0.67 seconds
Started Jun 29 05:16:44 PM PDT 24
Finished Jun 29 05:16:46 PM PDT 24
Peak memory 194944 kb
Host smart-a51a9cb4-a73e-4553-876f-008e8ca042c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381687009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2381687009
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2936459788
Short name T226
Test name
Test status
Simulation time 84168335 ps
CPU time 3.97 seconds
Started Jun 29 05:16:51 PM PDT 24
Finished Jun 29 05:16:56 PM PDT 24
Peak memory 198652 kb
Host smart-23fc6beb-78df-445b-a496-90337060bb0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936459788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2936459788
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/45.gpio_smoke.1716663314
Short name T286
Test name
Test status
Simulation time 35258367 ps
CPU time 1.01 seconds
Started Jun 29 05:16:42 PM PDT 24
Finished Jun 29 05:16:44 PM PDT 24
Peak memory 197164 kb
Host smart-6c223081-48d9-4873-a858-518837b7bbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716663314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1716663314
Directory /workspace/45.gpio_smoke/latest


Test location /workspace/coverage/default/45.gpio_stress_all.2983235278
Short name T610
Test name
Test status
Simulation time 7791196812 ps
CPU time 87.12 seconds
Started Jun 29 05:16:53 PM PDT 24
Finished Jun 29 05:18:20 PM PDT 24
Peak memory 198736 kb
Host smart-e5694ca9-f553-4d72-85fd-d7792a207a1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983235278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2983235278
Directory /workspace/45.gpio_stress_all/latest


Test location /workspace/coverage/default/46.gpio_alert_test.4067430223
Short name T183
Test name
Test status
Simulation time 24509071 ps
CPU time 0.59 seconds
Started Jun 29 05:16:54 PM PDT 24
Finished Jun 29 05:16:55 PM PDT 24
Peak memory 195344 kb
Host smart-bcf6d944-5403-44a4-96e2-fdffecd26d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067430223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.4067430223
Directory /workspace/46.gpio_alert_test/latest


Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1303254484
Short name T270
Test name
Test status
Simulation time 18353544 ps
CPU time 0.65 seconds
Started Jun 29 05:16:56 PM PDT 24
Finished Jun 29 05:16:57 PM PDT 24
Peak memory 194808 kb
Host smart-7ce3cc0e-76cb-44e2-84ea-78b42eb60e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303254484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1303254484
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/46.gpio_filter_stress.4281645143
Short name T507
Test name
Test status
Simulation time 586576675 ps
CPU time 16.89 seconds
Started Jun 29 05:16:52 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 197652 kb
Host smart-6fad8887-fbbc-428a-a95f-6a16670ed0ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281645143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4281645143
Directory /workspace/46.gpio_filter_stress/latest


Test location /workspace/coverage/default/46.gpio_full_random.4029038557
Short name T397
Test name
Test status
Simulation time 103874336 ps
CPU time 0.97 seconds
Started Jun 29 05:16:49 PM PDT 24
Finished Jun 29 05:16:51 PM PDT 24
Peak memory 198584 kb
Host smart-268e6d41-a129-495f-a43c-9a9f68643420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029038557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.4029038557
Directory /workspace/46.gpio_full_random/latest


Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3478400126
Short name T577
Test name
Test status
Simulation time 33746088 ps
CPU time 1.01 seconds
Started Jun 29 05:16:54 PM PDT 24
Finished Jun 29 05:16:56 PM PDT 24
Peak memory 197424 kb
Host smart-46311cdd-c2c6-4bb2-847a-eaa19b309c2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478400126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3478400126
Directory /workspace/46.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1327146553
Short name T250
Test name
Test status
Simulation time 198956798 ps
CPU time 2.12 seconds
Started Jun 29 05:16:51 PM PDT 24
Finished Jun 29 05:16:54 PM PDT 24
Peak memory 198752 kb
Host smart-e613cb33-e775-4f89-bf53-306fd1342fa2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327146553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1327146553
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.4112224238
Short name T328
Test name
Test status
Simulation time 785010789 ps
CPU time 1.9 seconds
Started Jun 29 05:16:53 PM PDT 24
Finished Jun 29 05:16:55 PM PDT 24
Peak memory 196788 kb
Host smart-08900c3e-8bb5-4682-aa32-14d1d8956cfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112224238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.4112224238
Directory /workspace/46.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/46.gpio_random_dout_din.3819717337
Short name T202
Test name
Test status
Simulation time 31593086 ps
CPU time 0.79 seconds
Started Jun 29 05:16:55 PM PDT 24
Finished Jun 29 05:16:57 PM PDT 24
Peak memory 196244 kb
Host smart-dc167edf-f51a-4090-aa9b-7e8ee6731532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819717337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3819717337
Directory /workspace/46.gpio_random_dout_din/latest


Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2017870425
Short name T712
Test name
Test status
Simulation time 60534087 ps
CPU time 0.93 seconds
Started Jun 29 05:16:53 PM PDT 24
Finished Jun 29 05:16:55 PM PDT 24
Peak memory 196660 kb
Host smart-bf9baaae-9de6-4ffd-8df3-8541ee2008b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017870425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2017870425
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.148147503
Short name T10
Test name
Test status
Simulation time 374032161 ps
CPU time 2.74 seconds
Started Jun 29 05:16:51 PM PDT 24
Finished Jun 29 05:16:55 PM PDT 24
Peak memory 198576 kb
Host smart-e3f88f92-4faa-43e3-b700-e59edada151e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148147503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.148147503
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/46.gpio_smoke.1167030137
Short name T393
Test name
Test status
Simulation time 138104456 ps
CPU time 1.27 seconds
Started Jun 29 05:16:53 PM PDT 24
Finished Jun 29 05:16:55 PM PDT 24
Peak memory 197548 kb
Host smart-2fc2e26f-b4a0-4564-87b3-3c6185451e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167030137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1167030137
Directory /workspace/46.gpio_smoke/latest


Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3112447061
Short name T105
Test name
Test status
Simulation time 40921018 ps
CPU time 0.83 seconds
Started Jun 29 05:16:53 PM PDT 24
Finished Jun 29 05:16:55 PM PDT 24
Peak memory 195840 kb
Host smart-0f92f712-15b4-4d67-8e0d-eb598635f591
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112447061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3112447061
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/46.gpio_stress_all.484011489
Short name T433
Test name
Test status
Simulation time 3687657599 ps
CPU time 18.34 seconds
Started Jun 29 05:16:54 PM PDT 24
Finished Jun 29 05:17:13 PM PDT 24
Peak memory 198824 kb
Host smart-8e9372f2-cf56-4151-9de7-742dffa6549a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484011489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.484011489
Directory /workspace/46.gpio_stress_all/latest


Test location /workspace/coverage/default/47.gpio_alert_test.1210807755
Short name T340
Test name
Test status
Simulation time 18948729 ps
CPU time 0.62 seconds
Started Jun 29 05:17:06 PM PDT 24
Finished Jun 29 05:17:07 PM PDT 24
Peak memory 195400 kb
Host smart-b68e5c71-86b4-49cb-97fd-4cd723972ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210807755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1210807755
Directory /workspace/47.gpio_alert_test/latest


Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2813316138
Short name T151
Test name
Test status
Simulation time 19398353 ps
CPU time 0.68 seconds
Started Jun 29 05:17:02 PM PDT 24
Finished Jun 29 05:17:03 PM PDT 24
Peak memory 194920 kb
Host smart-b45e5ac5-336f-4c0f-a9ce-869b059d9343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813316138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2813316138
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/47.gpio_filter_stress.2795052725
Short name T45
Test name
Test status
Simulation time 1775431920 ps
CPU time 13.57 seconds
Started Jun 29 05:17:06 PM PDT 24
Finished Jun 29 05:17:20 PM PDT 24
Peak memory 197676 kb
Host smart-93c78d3d-1232-4de4-9c25-149639b3a375
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795052725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2795052725
Directory /workspace/47.gpio_filter_stress/latest


Test location /workspace/coverage/default/47.gpio_full_random.2934932193
Short name T353
Test name
Test status
Simulation time 98770990 ps
CPU time 0.9 seconds
Started Jun 29 05:17:00 PM PDT 24
Finished Jun 29 05:17:01 PM PDT 24
Peak memory 197796 kb
Host smart-0e88028b-386d-48a6-bf59-6b24b0faf0aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934932193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2934932193
Directory /workspace/47.gpio_full_random/latest


Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1738880438
Short name T716
Test name
Test status
Simulation time 601513147 ps
CPU time 1.45 seconds
Started Jun 29 05:17:01 PM PDT 24
Finished Jun 29 05:17:03 PM PDT 24
Peak memory 197284 kb
Host smart-f64fea56-584f-4c57-a78a-bfdd1fb7e25b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738880438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1738880438
Directory /workspace/47.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4162373608
Short name T554
Test name
Test status
Simulation time 109199978 ps
CPU time 2.37 seconds
Started Jun 29 05:17:00 PM PDT 24
Finished Jun 29 05:17:03 PM PDT 24
Peak memory 198664 kb
Host smart-fea6ddd7-a4a3-4939-970c-de537e3a4bd3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162373608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4162373608
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.4199625435
Short name T256
Test name
Test status
Simulation time 592643118 ps
CPU time 3.14 seconds
Started Jun 29 05:17:06 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 196420 kb
Host smart-87192857-b930-4b0d-a864-79bde2745128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199625435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.4199625435
Directory /workspace/47.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/47.gpio_random_dout_din.3268381580
Short name T366
Test name
Test status
Simulation time 199209181 ps
CPU time 1.18 seconds
Started Jun 29 05:16:56 PM PDT 24
Finished Jun 29 05:16:57 PM PDT 24
Peak memory 196812 kb
Host smart-2d08d957-0e46-48cb-aa27-f888048bb8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268381580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3268381580
Directory /workspace/47.gpio_random_dout_din/latest


Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2714274984
Short name T703
Test name
Test status
Simulation time 139647572 ps
CPU time 1.06 seconds
Started Jun 29 05:17:02 PM PDT 24
Finished Jun 29 05:17:04 PM PDT 24
Peak memory 196728 kb
Host smart-87bd092a-03c4-4a79-86a9-cb5c95df5eb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714274984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2714274984
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3412979042
Short name T154
Test name
Test status
Simulation time 26088623 ps
CPU time 1.07 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:07 PM PDT 24
Peak memory 198676 kb
Host smart-6ebd8526-0391-46f8-b27d-85393e472f63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412979042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3412979042
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/47.gpio_smoke.2295351123
Short name T655
Test name
Test status
Simulation time 113668490 ps
CPU time 0.76 seconds
Started Jun 29 05:16:54 PM PDT 24
Finished Jun 29 05:16:55 PM PDT 24
Peak memory 195896 kb
Host smart-1d2bcb4b-9b89-459c-8e5b-1350a480fab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295351123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2295351123
Directory /workspace/47.gpio_smoke/latest


Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3924368770
Short name T364
Test name
Test status
Simulation time 120077302 ps
CPU time 1.07 seconds
Started Jun 29 05:16:50 PM PDT 24
Finished Jun 29 05:16:52 PM PDT 24
Peak memory 197172 kb
Host smart-0f4a943c-7501-4cc0-9d23-8468a4083572
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924368770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3924368770
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/47.gpio_stress_all.1217713594
Short name T369
Test name
Test status
Simulation time 7585521857 ps
CPU time 189.9 seconds
Started Jun 29 05:17:06 PM PDT 24
Finished Jun 29 05:20:17 PM PDT 24
Peak memory 198688 kb
Host smart-475a6e4e-b945-487e-9bcb-6bd319f0fa69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217713594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1217713594
Directory /workspace/47.gpio_stress_all/latest


Test location /workspace/coverage/default/48.gpio_alert_test.3993964070
Short name T365
Test name
Test status
Simulation time 25999334 ps
CPU time 0.62 seconds
Started Jun 29 05:17:01 PM PDT 24
Finished Jun 29 05:17:02 PM PDT 24
Peak memory 194884 kb
Host smart-e7a6063e-8f27-4d2c-89aa-e36431009eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993964070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3993964070
Directory /workspace/48.gpio_alert_test/latest


Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.608545810
Short name T216
Test name
Test status
Simulation time 237864665 ps
CPU time 0.71 seconds
Started Jun 29 05:16:59 PM PDT 24
Finished Jun 29 05:17:00 PM PDT 24
Peak memory 196688 kb
Host smart-fb275121-a2e9-4844-a25d-fe29727d5db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608545810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.608545810
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/48.gpio_filter_stress.4212904940
Short name T603
Test name
Test status
Simulation time 516093162 ps
CPU time 6.53 seconds
Started Jun 29 05:17:06 PM PDT 24
Finished Jun 29 05:17:13 PM PDT 24
Peak memory 198576 kb
Host smart-2631058e-b768-4dc9-8da6-0f3581c7e4b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212904940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.4212904940
Directory /workspace/48.gpio_filter_stress/latest


Test location /workspace/coverage/default/48.gpio_full_random.1092690219
Short name T399
Test name
Test status
Simulation time 155499146 ps
CPU time 0.81 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:06 PM PDT 24
Peak memory 197276 kb
Host smart-6abbe682-77a1-43b4-959c-e1632bdbf20c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092690219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1092690219
Directory /workspace/48.gpio_full_random/latest


Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.718623747
Short name T195
Test name
Test status
Simulation time 604515339 ps
CPU time 1.32 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:06 PM PDT 24
Peak memory 196392 kb
Host smart-c9a2cc44-de00-4c47-a59c-ca4939a22300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718623747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.718623747
Directory /workspace/48.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.791834858
Short name T332
Test name
Test status
Simulation time 82558535 ps
CPU time 3.33 seconds
Started Jun 29 05:17:03 PM PDT 24
Finished Jun 29 05:17:07 PM PDT 24
Peak memory 198700 kb
Host smart-a7f6bd4e-b8bd-4102-98f9-9ff2129bd0d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791834858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.791834858
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.520559426
Short name T621
Test name
Test status
Simulation time 1822970615 ps
CPU time 3.45 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 198740 kb
Host smart-eaebe79f-dc00-4d9a-91b8-f5737b5fbcd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520559426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
520559426
Directory /workspace/48.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/48.gpio_random_dout_din.2331808327
Short name T16
Test name
Test status
Simulation time 62948014 ps
CPU time 0.85 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:06 PM PDT 24
Peak memory 196176 kb
Host smart-36b31f11-f10d-471e-b6d6-586f47c0ba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331808327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2331808327
Directory /workspace/48.gpio_random_dout_din/latest


Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1549921698
Short name T368
Test name
Test status
Simulation time 44308150 ps
CPU time 1.18 seconds
Started Jun 29 05:17:01 PM PDT 24
Finished Jun 29 05:17:03 PM PDT 24
Peak memory 196768 kb
Host smart-fcf22d4e-78d3-43f2-9629-e52187ee50ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549921698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1549921698
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3385201020
Short name T38
Test name
Test status
Simulation time 465610051 ps
CPU time 5.05 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 198672 kb
Host smart-5c97f7a1-f716-4745-9594-9817fcb62fa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385201020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3385201020
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/48.gpio_smoke.1476593969
Short name T553
Test name
Test status
Simulation time 68063451 ps
CPU time 1.32 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:07 PM PDT 24
Peak memory 197604 kb
Host smart-4e5bd68b-b595-43a8-b2be-bbefdf6bd3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476593969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1476593969
Directory /workspace/48.gpio_smoke/latest


Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.4193699752
Short name T156
Test name
Test status
Simulation time 55826917 ps
CPU time 0.99 seconds
Started Jun 29 05:17:03 PM PDT 24
Finished Jun 29 05:17:04 PM PDT 24
Peak memory 196228 kb
Host smart-177be0af-c8ae-47a3-aa04-d9c431f699b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193699752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.4193699752
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/48.gpio_stress_all.1385976090
Short name T362
Test name
Test status
Simulation time 26181632550 ps
CPU time 208.96 seconds
Started Jun 29 05:17:00 PM PDT 24
Finished Jun 29 05:20:29 PM PDT 24
Peak memory 198808 kb
Host smart-a145452f-3592-4212-9e44-a2253c566cb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385976090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1385976090
Directory /workspace/48.gpio_stress_all/latest


Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3014689098
Short name T71
Test name
Test status
Simulation time 96571699294 ps
CPU time 551.9 seconds
Started Jun 29 05:17:01 PM PDT 24
Finished Jun 29 05:26:14 PM PDT 24
Peak memory 198988 kb
Host smart-712493f7-5df3-4a85-88f8-debd16f7c3c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3014689098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3014689098
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/49.gpio_alert_test.2637318205
Short name T531
Test name
Test status
Simulation time 50660296 ps
CPU time 0.57 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 194692 kb
Host smart-bb0a2c7c-1469-4699-aeff-1518e2059f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637318205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2637318205
Directory /workspace/49.gpio_alert_test/latest


Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1459194990
Short name T599
Test name
Test status
Simulation time 23064048 ps
CPU time 0.87 seconds
Started Jun 29 05:17:02 PM PDT 24
Finished Jun 29 05:17:03 PM PDT 24
Peak memory 195892 kb
Host smart-e9e2283b-4d02-4ded-900e-c49a9f57a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459194990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1459194990
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/49.gpio_filter_stress.3050808306
Short name T491
Test name
Test status
Simulation time 2527322791 ps
CPU time 9.11 seconds
Started Jun 29 05:17:02 PM PDT 24
Finished Jun 29 05:17:11 PM PDT 24
Peak memory 198784 kb
Host smart-86bc2711-10d2-4d25-b4d3-0be7999ea1d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050808306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3050808306
Directory /workspace/49.gpio_filter_stress/latest


Test location /workspace/coverage/default/49.gpio_full_random.788455881
Short name T266
Test name
Test status
Simulation time 102730009 ps
CPU time 0.69 seconds
Started Jun 29 05:16:59 PM PDT 24
Finished Jun 29 05:17:00 PM PDT 24
Peak memory 195368 kb
Host smart-31a21adb-a6cf-4c36-84a5-8e1136befe28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788455881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.788455881
Directory /workspace/49.gpio_full_random/latest


Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2090562040
Short name T514
Test name
Test status
Simulation time 93660959 ps
CPU time 1.16 seconds
Started Jun 29 05:17:01 PM PDT 24
Finished Jun 29 05:17:03 PM PDT 24
Peak memory 196752 kb
Host smart-bfe76fdc-95f2-4418-9a93-1d702eed9426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090562040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2090562040
Directory /workspace/49.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.579120539
Short name T211
Test name
Test status
Simulation time 458008180 ps
CPU time 3.62 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 198352 kb
Host smart-c98107ce-0c9e-4bbe-a810-30fce4190b73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579120539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.579120539
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.230085522
Short name T468
Test name
Test status
Simulation time 159743523 ps
CPU time 2.92 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 197884 kb
Host smart-2c458c3b-2672-4a14-a49f-d29602d941fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230085522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
230085522
Directory /workspace/49.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/49.gpio_random_dout_din.866747136
Short name T192
Test name
Test status
Simulation time 27330863 ps
CPU time 0.81 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:06 PM PDT 24
Peak memory 196788 kb
Host smart-e4ffada6-bd94-4a9b-8d13-45f7eb856884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866747136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.866747136
Directory /workspace/49.gpio_random_dout_din/latest


Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2019978690
Short name T144
Test name
Test status
Simulation time 107269742 ps
CPU time 1.03 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:17:06 PM PDT 24
Peak memory 197444 kb
Host smart-1b313ca6-b438-4037-b259-14d17fa0d6e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019978690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2019978690
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2400366235
Short name T346
Test name
Test status
Simulation time 713364182 ps
CPU time 3.31 seconds
Started Jun 29 05:17:02 PM PDT 24
Finished Jun 29 05:17:06 PM PDT 24
Peak memory 198636 kb
Host smart-d3887791-2c78-4a35-906f-84c22b388539
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400366235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2400366235
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/49.gpio_smoke.1091209674
Short name T409
Test name
Test status
Simulation time 79923073 ps
CPU time 0.88 seconds
Started Jun 29 05:17:01 PM PDT 24
Finished Jun 29 05:17:02 PM PDT 24
Peak memory 196016 kb
Host smart-025df5c7-f8f7-4ae6-b6c7-9eabc8219c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091209674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1091209674
Directory /workspace/49.gpio_smoke/latest


Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.670179151
Short name T26
Test name
Test status
Simulation time 62802837 ps
CPU time 1.07 seconds
Started Jun 29 05:17:06 PM PDT 24
Finished Jun 29 05:17:08 PM PDT 24
Peak memory 197188 kb
Host smart-27c7e931-3121-4c21-835d-cb39e63e836c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670179151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.670179151
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/49.gpio_stress_all.1791074526
Short name T450
Test name
Test status
Simulation time 24118347455 ps
CPU time 63.56 seconds
Started Jun 29 05:17:05 PM PDT 24
Finished Jun 29 05:18:10 PM PDT 24
Peak memory 198808 kb
Host smart-a8585207-e040-4612-a6cd-1d85a758cb20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791074526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1791074526
Directory /workspace/49.gpio_stress_all/latest


Test location /workspace/coverage/default/5.gpio_alert_test.1932189943
Short name T512
Test name
Test status
Simulation time 22072259 ps
CPU time 0.55 seconds
Started Jun 29 05:14:39 PM PDT 24
Finished Jun 29 05:14:40 PM PDT 24
Peak memory 195384 kb
Host smart-062bf773-faef-4ed7-a992-e60e50e57685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932189943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1932189943
Directory /workspace/5.gpio_alert_test/latest


Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.777032732
Short name T618
Test name
Test status
Simulation time 58841433 ps
CPU time 0.65 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:33 PM PDT 24
Peak memory 194720 kb
Host smart-bd4b80f3-add9-41c3-9b2e-c4f363fd9d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777032732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.777032732
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/5.gpio_filter_stress.4272825831
Short name T632
Test name
Test status
Simulation time 1062357028 ps
CPU time 9.81 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:41 PM PDT 24
Peak memory 197552 kb
Host smart-fab09c00-ff14-4a56-b209-4fc23ee41f12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272825831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4272825831
Directory /workspace/5.gpio_filter_stress/latest


Test location /workspace/coverage/default/5.gpio_full_random.3045173479
Short name T291
Test name
Test status
Simulation time 173116160 ps
CPU time 1.08 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:34 PM PDT 24
Peak memory 198408 kb
Host smart-66a21bce-4272-42ae-ad2c-4ae959eb6cc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045173479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3045173479
Directory /workspace/5.gpio_full_random/latest


Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.4196042553
Short name T294
Test name
Test status
Simulation time 179277563 ps
CPU time 0.86 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:32 PM PDT 24
Peak memory 197168 kb
Host smart-aae6365f-f8d0-490e-be0a-ac09ecc82a08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196042553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.4196042553
Directory /workspace/5.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4012284907
Short name T276
Test name
Test status
Simulation time 231327430 ps
CPU time 2.6 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 198704 kb
Host smart-b8259af2-d422-47fa-8171-f30ff3eecd9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012284907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4012284907
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.512933195
Short name T145
Test name
Test status
Simulation time 104916414 ps
CPU time 1.48 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:33 PM PDT 24
Peak memory 196756 kb
Host smart-3c994162-2eb6-4c70-b8de-b54ab877bca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512933195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.512933195
Directory /workspace/5.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/5.gpio_random_dout_din.3912372645
Short name T463
Test name
Test status
Simulation time 91464692 ps
CPU time 1.25 seconds
Started Jun 29 05:14:22 PM PDT 24
Finished Jun 29 05:14:24 PM PDT 24
Peak memory 197344 kb
Host smart-2b7183ae-7af4-49e8-a8bb-eda366c6ee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912372645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3912372645
Directory /workspace/5.gpio_random_dout_din/latest


Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2606487552
Short name T264
Test name
Test status
Simulation time 116956336 ps
CPU time 0.92 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:36 PM PDT 24
Peak memory 197280 kb
Host smart-c51e8741-e1f0-44cc-b42a-de0012eec4ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606487552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2606487552
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1080515771
Short name T280
Test name
Test status
Simulation time 69069611 ps
CPU time 3.13 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:36 PM PDT 24
Peak memory 198544 kb
Host smart-fb3d7cb6-6a6b-494a-b71f-52c5021552cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080515771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1080515771
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/5.gpio_smoke.1597181987
Short name T437
Test name
Test status
Simulation time 100347634 ps
CPU time 0.89 seconds
Started Jun 29 05:14:22 PM PDT 24
Finished Jun 29 05:14:23 PM PDT 24
Peak memory 196116 kb
Host smart-627cfc36-9eb5-46f2-8fad-a28d2f6ccae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597181987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1597181987
Directory /workspace/5.gpio_smoke/latest


Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3271791269
Short name T319
Test name
Test status
Simulation time 257541327 ps
CPU time 1.14 seconds
Started Jun 29 05:14:21 PM PDT 24
Finished Jun 29 05:14:22 PM PDT 24
Peak memory 196244 kb
Host smart-92320551-a05c-4062-b300-99eda218ac5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271791269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3271791269
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/5.gpio_stress_all.1419296107
Short name T532
Test name
Test status
Simulation time 12814885540 ps
CPU time 61.17 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:15:33 PM PDT 24
Peak memory 198828 kb
Host smart-1c04044e-7360-4b36-866b-f9985351c068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419296107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1419296107
Directory /workspace/5.gpio_stress_all/latest


Test location /workspace/coverage/default/6.gpio_alert_test.3093379721
Short name T257
Test name
Test status
Simulation time 16749235 ps
CPU time 0.61 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:32 PM PDT 24
Peak memory 195572 kb
Host smart-1fc24ff5-8736-4525-8dc7-5086837da244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093379721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3093379721
Directory /workspace/6.gpio_alert_test/latest


Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.346652368
Short name T475
Test name
Test status
Simulation time 48996726 ps
CPU time 0.67 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 194760 kb
Host smart-83ea5a50-9a66-4796-ab55-721199dbbd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346652368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.346652368
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/6.gpio_filter_stress.3412797256
Short name T191
Test name
Test status
Simulation time 368068725 ps
CPU time 19.77 seconds
Started Jun 29 05:14:40 PM PDT 24
Finished Jun 29 05:15:00 PM PDT 24
Peak memory 196984 kb
Host smart-924f33e3-310b-4591-b125-e07f6b23dd44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412797256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3412797256
Directory /workspace/6.gpio_filter_stress/latest


Test location /workspace/coverage/default/6.gpio_full_random.2788457103
Short name T184
Test name
Test status
Simulation time 266804427 ps
CPU time 1 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 197308 kb
Host smart-d37e9a2d-f31e-436a-8378-01e4a2dce330
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788457103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2788457103
Directory /workspace/6.gpio_full_random/latest


Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.569390828
Short name T149
Test name
Test status
Simulation time 50742559 ps
CPU time 1.23 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 196580 kb
Host smart-5a2a7266-9e99-46ca-82d1-0d340b948e5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569390828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.569390828
Directory /workspace/6.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3379479324
Short name T488
Test name
Test status
Simulation time 121579151 ps
CPU time 2.5 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 198768 kb
Host smart-729a92a2-f085-4026-b763-323e869df874
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379479324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3379479324
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1356225999
Short name T590
Test name
Test status
Simulation time 136225073 ps
CPU time 3.25 seconds
Started Jun 29 05:14:33 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 197952 kb
Host smart-40ecda65-4b81-46dc-9769-cbb3d2dd96e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356225999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1356225999
Directory /workspace/6.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/6.gpio_random_dout_din.2152444943
Short name T565
Test name
Test status
Simulation time 217073922 ps
CPU time 1.01 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 197472 kb
Host smart-5f1aa069-b0ed-42f5-a104-a59d1b11def4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152444943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2152444943
Directory /workspace/6.gpio_random_dout_din/latest


Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2509659244
Short name T563
Test name
Test status
Simulation time 207588433 ps
CPU time 1.12 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 197376 kb
Host smart-68185a48-527f-44e1-b4bf-dcacc50ccb17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509659244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2509659244
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2444749311
Short name T544
Test name
Test status
Simulation time 84145486 ps
CPU time 2.07 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 198660 kb
Host smart-6689ca9b-39a1-4e7c-bb8d-f71831f18d9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444749311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2444749311
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/6.gpio_smoke.872673995
Short name T442
Test name
Test status
Simulation time 400689475 ps
CPU time 1.31 seconds
Started Jun 29 05:14:33 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 196524 kb
Host smart-305865e4-c37f-457b-b39c-37db20692dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872673995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.872673995
Directory /workspace/6.gpio_smoke/latest


Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.721451480
Short name T525
Test name
Test status
Simulation time 42985719 ps
CPU time 0.8 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:32 PM PDT 24
Peak memory 196532 kb
Host smart-11e8f392-ecaa-4fb6-a5a2-565cb41268b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721451480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.721451480
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/6.gpio_stress_all.3884056053
Short name T604
Test name
Test status
Simulation time 20247140014 ps
CPU time 134.51 seconds
Started Jun 29 05:14:36 PM PDT 24
Finished Jun 29 05:16:51 PM PDT 24
Peak memory 198760 kb
Host smart-6dbd2793-2b4e-4f2c-b830-96a0bf52d82b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884056053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3884056053
Directory /workspace/6.gpio_stress_all/latest


Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3251212511
Short name T48
Test name
Test status
Simulation time 102379814819 ps
CPU time 469.82 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:22:23 PM PDT 24
Peak memory 207092 kb
Host smart-db76f776-8fa2-437b-9970-f67db5ca65a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3251212511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3251212511
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/7.gpio_alert_test.3648216736
Short name T163
Test name
Test status
Simulation time 14469289 ps
CPU time 0.58 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 194864 kb
Host smart-7968f82f-9228-4971-9d7b-099c5a0627ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648216736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3648216736
Directory /workspace/7.gpio_alert_test/latest


Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.909317925
Short name T454
Test name
Test status
Simulation time 47737873 ps
CPU time 0.64 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:32 PM PDT 24
Peak memory 195408 kb
Host smart-cebac1d0-fcca-431b-aca3-bff20e68c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909317925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.909317925
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/7.gpio_filter_stress.3424623921
Short name T150
Test name
Test status
Simulation time 3395731463 ps
CPU time 15.6 seconds
Started Jun 29 05:14:39 PM PDT 24
Finished Jun 29 05:14:55 PM PDT 24
Peak memory 197536 kb
Host smart-a4c1878f-8057-40be-b59a-2bf87e3f3ea4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424623921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3424623921
Directory /workspace/7.gpio_filter_stress/latest


Test location /workspace/coverage/default/7.gpio_full_random.1016397907
Short name T680
Test name
Test status
Simulation time 242614410 ps
CPU time 0.96 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:34 PM PDT 24
Peak memory 197852 kb
Host smart-7308a33c-bee8-43f7-9690-d07b0db36311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016397907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1016397907
Directory /workspace/7.gpio_full_random/latest


Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2453508393
Short name T232
Test name
Test status
Simulation time 522333495 ps
CPU time 1.39 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:34 PM PDT 24
Peak memory 197356 kb
Host smart-7f5e9153-9454-4188-b28e-5a270b01639f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453508393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2453508393
Directory /workspace/7.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2932312703
Short name T361
Test name
Test status
Simulation time 59829006 ps
CPU time 2.32 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:38 PM PDT 24
Peak memory 197016 kb
Host smart-be087882-62bf-4e71-8c15-42a67df1066d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932312703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2932312703
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1973170970
Short name T682
Test name
Test status
Simulation time 135085857 ps
CPU time 2.78 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 196540 kb
Host smart-3f478269-1df6-459d-8bfa-f443be0ae511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973170970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1973170970
Directory /workspace/7.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/7.gpio_random_dout_din.3706920361
Short name T584
Test name
Test status
Simulation time 66519623 ps
CPU time 1.29 seconds
Started Jun 29 05:14:33 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 197652 kb
Host smart-07a98d52-d19d-42be-af1e-0c17c9ca635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706920361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3706920361
Directory /workspace/7.gpio_random_dout_din/latest


Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.913639088
Short name T510
Test name
Test status
Simulation time 119175085 ps
CPU time 0.97 seconds
Started Jun 29 05:14:33 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 196732 kb
Host smart-5c45f384-34d7-41c6-9d0c-41d6ca5e0855
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913639088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.913639088
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1085605492
Short name T547
Test name
Test status
Simulation time 776261608 ps
CPU time 3.41 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:36 PM PDT 24
Peak memory 198688 kb
Host smart-3613f17a-d55a-40de-9d51-ec664a80a343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085605492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1085605492
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/7.gpio_smoke.2398699658
Short name T242
Test name
Test status
Simulation time 39289503 ps
CPU time 0.94 seconds
Started Jun 29 05:14:40 PM PDT 24
Finished Jun 29 05:14:41 PM PDT 24
Peak memory 197660 kb
Host smart-11df77fc-a476-4ec2-b34e-05a121f79865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398699658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2398699658
Directory /workspace/7.gpio_smoke/latest


Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.868726151
Short name T188
Test name
Test status
Simulation time 126063490 ps
CPU time 1.03 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 197180 kb
Host smart-973b17ed-3999-45ad-ab4e-4e7c857b8c84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868726151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.868726151
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/7.gpio_stress_all.527156845
Short name T215
Test name
Test status
Simulation time 14884578008 ps
CPU time 191.15 seconds
Started Jun 29 05:14:39 PM PDT 24
Finished Jun 29 05:17:50 PM PDT 24
Peak memory 198764 kb
Host smart-71835911-948b-45cc-a032-d15d78789f1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527156845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.527156845
Directory /workspace/7.gpio_stress_all/latest


Test location /workspace/coverage/default/8.gpio_alert_test.54722821
Short name T307
Test name
Test status
Simulation time 12776137 ps
CPU time 0.55 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:36 PM PDT 24
Peak memory 193496 kb
Host smart-d250e621-adc4-45be-ac58-2b3156288aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54722821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.54722821
Directory /workspace/8.gpio_alert_test/latest


Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1880332302
Short name T230
Test name
Test status
Simulation time 186571888 ps
CPU time 0.62 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 194580 kb
Host smart-5b168864-1f36-441c-84ab-139bed7350d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880332302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1880332302
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/8.gpio_filter_stress.3012938917
Short name T375
Test name
Test status
Simulation time 919594542 ps
CPU time 23.54 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:15:00 PM PDT 24
Peak memory 198652 kb
Host smart-ec8e89d5-b6ee-42fe-9637-68dc28144aa4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012938917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3012938917
Directory /workspace/8.gpio_filter_stress/latest


Test location /workspace/coverage/default/8.gpio_full_random.1205959365
Short name T715
Test name
Test status
Simulation time 441620116 ps
CPU time 1.08 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:33 PM PDT 24
Peak memory 198588 kb
Host smart-ce73b200-ed1d-4e5a-a31e-deea53074826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205959365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1205959365
Directory /workspace/8.gpio_full_random/latest


Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1011793505
Short name T645
Test name
Test status
Simulation time 65157802 ps
CPU time 0.72 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 196700 kb
Host smart-6be073bb-9a5a-4bb9-9ad4-7b14e58af68c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011793505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1011793505
Directory /workspace/8.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2553249561
Short name T272
Test name
Test status
Simulation time 92953676 ps
CPU time 2 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:38 PM PDT 24
Peak memory 198748 kb
Host smart-0893f244-dec7-468a-bec7-65db813e32d1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553249561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2553249561
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1140635886
Short name T400
Test name
Test status
Simulation time 151875386 ps
CPU time 3.29 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:38 PM PDT 24
Peak memory 197668 kb
Host smart-290f0de7-4510-4000-8956-1643a6927cb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140635886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1140635886
Directory /workspace/8.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/8.gpio_random_dout_din.3258593052
Short name T569
Test name
Test status
Simulation time 78301891 ps
CPU time 1.07 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 196520 kb
Host smart-4461e556-1f36-4d9c-8f4e-3a8e4ac7a72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258593052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3258593052
Directory /workspace/8.gpio_random_dout_din/latest


Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.214266666
Short name T594
Test name
Test status
Simulation time 70247984 ps
CPU time 0.78 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 196096 kb
Host smart-427610e0-4e11-4e93-851f-a122da037301
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214266666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.214266666
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1420972432
Short name T508
Test name
Test status
Simulation time 104618330 ps
CPU time 4.48 seconds
Started Jun 29 05:14:33 PM PDT 24
Finished Jun 29 05:14:38 PM PDT 24
Peak memory 198676 kb
Host smart-46a89464-b17f-4ea1-ba4d-3e8a0e58118a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420972432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1420972432
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/8.gpio_smoke.2341799234
Short name T707
Test name
Test status
Simulation time 293335615 ps
CPU time 1.35 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 197136 kb
Host smart-31328e3a-2332-44fe-95e8-a24d28c8eabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341799234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2341799234
Directory /workspace/8.gpio_smoke/latest


Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3065011308
Short name T295
Test name
Test status
Simulation time 217329163 ps
CPU time 0.96 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:34 PM PDT 24
Peak memory 196244 kb
Host smart-d1735659-e8d8-4d03-9aa5-ac5c58a66012
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065011308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3065011308
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/8.gpio_stress_all.3273642948
Short name T229
Test name
Test status
Simulation time 1123173171 ps
CPU time 31.63 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:15:04 PM PDT 24
Peak memory 198484 kb
Host smart-4f06c70d-f06a-45f5-a14a-9ffa6c47273b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273642948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3273642948
Directory /workspace/8.gpio_stress_all/latest


Test location /workspace/coverage/default/9.gpio_alert_test.2146581765
Short name T405
Test name
Test status
Simulation time 17011612 ps
CPU time 0.57 seconds
Started Jun 29 05:14:41 PM PDT 24
Finished Jun 29 05:14:42 PM PDT 24
Peak memory 194620 kb
Host smart-b39760c4-8bd0-498e-87ff-3b3e2bd064ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146581765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2146581765
Directory /workspace/9.gpio_alert_test/latest


Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3950806725
Short name T396
Test name
Test status
Simulation time 29586298 ps
CPU time 0.84 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 196476 kb
Host smart-2c693f37-7ef7-410e-9292-e760b6299105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950806725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3950806725
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest


Test location /workspace/coverage/default/9.gpio_filter_stress.746270072
Short name T592
Test name
Test status
Simulation time 866214047 ps
CPU time 5.54 seconds
Started Jun 29 05:14:51 PM PDT 24
Finished Jun 29 05:14:57 PM PDT 24
Peak memory 197628 kb
Host smart-eafd38b4-bea2-49d4-9a9c-f1dc81299dc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746270072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.746270072
Directory /workspace/9.gpio_filter_stress/latest


Test location /workspace/coverage/default/9.gpio_full_random.1072430329
Short name T228
Test name
Test status
Simulation time 165521264 ps
CPU time 0.92 seconds
Started Jun 29 05:14:45 PM PDT 24
Finished Jun 29 05:14:47 PM PDT 24
Peak memory 197908 kb
Host smart-62208307-dc97-4d70-86a0-d8652af81ac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072430329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1072430329
Directory /workspace/9.gpio_full_random/latest


Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.354693940
Short name T162
Test name
Test status
Simulation time 110851148 ps
CPU time 1.06 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 196628 kb
Host smart-a811d65f-6426-412b-a470-fb06c2da3371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354693940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.354693940
Directory /workspace/9.gpio_intr_rand_pgm/latest


Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2160073976
Short name T117
Test name
Test status
Simulation time 28401227 ps
CPU time 1.23 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 197136 kb
Host smart-bdc35de6-a939-46af-906f-1c7a8b0e694a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160073976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2160073976
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest


Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.792093390
Short name T245
Test name
Test status
Simulation time 115185370 ps
CPU time 1.73 seconds
Started Jun 29 05:14:32 PM PDT 24
Finished Jun 29 05:14:35 PM PDT 24
Peak memory 196752 kb
Host smart-e3adb3b7-b122-49dd-a33a-3be655dc6b34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792093390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.792093390
Directory /workspace/9.gpio_rand_intr_trigger/latest


Test location /workspace/coverage/default/9.gpio_random_dout_din.967138789
Short name T428
Test name
Test status
Simulation time 114136157 ps
CPU time 1.12 seconds
Started Jun 29 05:14:35 PM PDT 24
Finished Jun 29 05:14:37 PM PDT 24
Peak memory 196692 kb
Host smart-c47943d9-eaba-4b0a-a3f2-97c00031b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967138789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.967138789
Directory /workspace/9.gpio_random_dout_din/latest


Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1963394524
Short name T370
Test name
Test status
Simulation time 67132174 ps
CPU time 1.23 seconds
Started Jun 29 05:14:34 PM PDT 24
Finished Jun 29 05:14:36 PM PDT 24
Peak memory 197716 kb
Host smart-c2f61c8f-6728-4348-84e7-206dbb1d33cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963394524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1963394524
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest


Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2317025538
Short name T511
Test name
Test status
Simulation time 310981874 ps
CPU time 3.71 seconds
Started Jun 29 05:14:45 PM PDT 24
Finished Jun 29 05:14:49 PM PDT 24
Peak memory 198688 kb
Host smart-ebe4a0fc-34cb-4425-a692-c91f487e120d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317025538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2317025538
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest


Test location /workspace/coverage/default/9.gpio_smoke.3359553114
Short name T165
Test name
Test status
Simulation time 64192724 ps
CPU time 1.07 seconds
Started Jun 29 05:14:36 PM PDT 24
Finished Jun 29 05:14:38 PM PDT 24
Peak memory 196384 kb
Host smart-923ebb64-ce6f-4cf1-a11e-290268e12c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359553114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3359553114
Directory /workspace/9.gpio_smoke/latest


Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4274842528
Short name T690
Test name
Test status
Simulation time 148684151 ps
CPU time 0.92 seconds
Started Jun 29 05:14:31 PM PDT 24
Finished Jun 29 05:14:33 PM PDT 24
Peak memory 196516 kb
Host smart-1cf9cd81-f2d3-4883-8492-dc437f8fcb62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274842528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4274842528
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest


Test location /workspace/coverage/default/9.gpio_stress_all.3189386907
Short name T605
Test name
Test status
Simulation time 5895749164 ps
CPU time 162.7 seconds
Started Jun 29 05:14:42 PM PDT 24
Finished Jun 29 05:17:25 PM PDT 24
Peak memory 198860 kb
Host smart-9e2e8582-5cf2-4303-bb61-8743ca8a76b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189386907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3189386907
Directory /workspace/9.gpio_stress_all/latest


Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3148962397
Short name T70
Test name
Test status
Simulation time 142142570029 ps
CPU time 975.31 seconds
Started Jun 29 05:14:50 PM PDT 24
Finished Jun 29 05:31:06 PM PDT 24
Peak memory 198980 kb
Host smart-da450f98-35e5-48a4-92ba-71830805b49d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3148962397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3148962397
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest


Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2944924388
Short name T911
Test name
Test status
Simulation time 81715870 ps
CPU time 1.55 seconds
Started Jun 29 06:24:50 PM PDT 24
Finished Jun 29 06:24:52 PM PDT 24
Peak memory 197160 kb
Host smart-b6ab73f1-d20e-4f5b-9584-cd76536d55fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2944924388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2944924388
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.589960394
Short name T913
Test name
Test status
Simulation time 589564963 ps
CPU time 1.02 seconds
Started Jun 29 06:24:51 PM PDT 24
Finished Jun 29 06:24:53 PM PDT 24
Peak memory 196976 kb
Host smart-4e9c9fd4-a95d-45f4-ad5c-730fdafb41f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589960394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.589960394
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3122124283
Short name T867
Test name
Test status
Simulation time 85529947 ps
CPU time 1.51 seconds
Started Jun 29 06:24:51 PM PDT 24
Finished Jun 29 06:24:53 PM PDT 24
Peak memory 197288 kb
Host smart-ea9b2b36-9556-41b6-875c-0255b8511906
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3122124283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3122124283
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.658592579
Short name T850
Test name
Test status
Simulation time 224341036 ps
CPU time 1.24 seconds
Started Jun 29 06:24:53 PM PDT 24
Finished Jun 29 06:24:54 PM PDT 24
Peak memory 198452 kb
Host smart-518079f8-7a14-457b-9bfd-a04d076d5457
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658592579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.658592579
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1531562127
Short name T921
Test name
Test status
Simulation time 96006254 ps
CPU time 1.08 seconds
Started Jun 29 06:24:58 PM PDT 24
Finished Jun 29 06:25:00 PM PDT 24
Peak memory 198392 kb
Host smart-fff3654c-3dd1-4281-a2b0-054943c0ef29
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1531562127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1531562127
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1735162753
Short name T886
Test name
Test status
Simulation time 54514185 ps
CPU time 1.12 seconds
Started Jun 29 06:25:00 PM PDT 24
Finished Jun 29 06:25:01 PM PDT 24
Peak memory 196352 kb
Host smart-e5f5ae21-d579-4a6e-91ba-09e32b57c4be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735162753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1735162753
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1875391373
Short name T939
Test name
Test status
Simulation time 285013547 ps
CPU time 1.12 seconds
Started Jun 29 06:24:58 PM PDT 24
Finished Jun 29 06:25:00 PM PDT 24
Peak memory 196920 kb
Host smart-29d9e892-9c6e-42e7-abdc-8104a7ed79b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1875391373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1875391373
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2056456088
Short name T901
Test name
Test status
Simulation time 33738958 ps
CPU time 0.78 seconds
Started Jun 29 06:24:59 PM PDT 24
Finished Jun 29 06:25:00 PM PDT 24
Peak memory 195740 kb
Host smart-be514154-d9e7-4f2e-a2cd-c2b62607d1a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056456088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2056456088
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3535915377
Short name T908
Test name
Test status
Simulation time 60604639 ps
CPU time 1.15 seconds
Started Jun 29 06:24:58 PM PDT 24
Finished Jun 29 06:24:59 PM PDT 24
Peak memory 196120 kb
Host smart-a7682aac-9ed1-40d8-a4d9-7349de02574f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3535915377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3535915377
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466599096
Short name T918
Test name
Test status
Simulation time 32284968 ps
CPU time 0.97 seconds
Started Jun 29 06:24:58 PM PDT 24
Finished Jun 29 06:25:00 PM PDT 24
Peak memory 196852 kb
Host smart-08e84980-88f7-41db-9bce-dd6777c6713e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466599096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2466599096
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.410072468
Short name T898
Test name
Test status
Simulation time 47077696 ps
CPU time 0.91 seconds
Started Jun 29 06:25:01 PM PDT 24
Finished Jun 29 06:25:03 PM PDT 24
Peak memory 195840 kb
Host smart-aa5c621d-c672-4bfa-85ef-82925dbb1e74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=410072468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.410072468
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.481595537
Short name T885
Test name
Test status
Simulation time 94730795 ps
CPU time 1.63 seconds
Started Jun 29 06:24:59 PM PDT 24
Finished Jun 29 06:25:01 PM PDT 24
Peak memory 198468 kb
Host smart-e6c2e93e-ace1-4ec2-ab08-20dcbd50ed93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481595537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.481595537
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.304110637
Short name T916
Test name
Test status
Simulation time 155658267 ps
CPU time 1.37 seconds
Started Jun 29 06:25:00 PM PDT 24
Finished Jun 29 06:25:01 PM PDT 24
Peak memory 196944 kb
Host smart-66b49ce8-f0a2-4cb3-93ed-26ff04bbd704
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=304110637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.304110637
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233686347
Short name T845
Test name
Test status
Simulation time 144442956 ps
CPU time 1.06 seconds
Started Jun 29 06:25:01 PM PDT 24
Finished Jun 29 06:25:03 PM PDT 24
Peak memory 198476 kb
Host smart-06d021bf-414e-4e05-8aa3-0238a4ef49b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233686347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.233686347
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4209114616
Short name T871
Test name
Test status
Simulation time 252394558 ps
CPU time 0.73 seconds
Started Jun 29 06:24:58 PM PDT 24
Finished Jun 29 06:25:00 PM PDT 24
Peak memory 195504 kb
Host smart-4165a9da-edca-4cb7-ba33-82713e973ec3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4209114616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.4209114616
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3605474285
Short name T858
Test name
Test status
Simulation time 46601618 ps
CPU time 1.42 seconds
Started Jun 29 06:25:01 PM PDT 24
Finished Jun 29 06:25:03 PM PDT 24
Peak memory 198476 kb
Host smart-a4563822-9398-4480-a85f-6778eee7c08b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605474285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3605474285
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4282345235
Short name T878
Test name
Test status
Simulation time 65447315 ps
CPU time 1.33 seconds
Started Jun 29 06:24:58 PM PDT 24
Finished Jun 29 06:24:59 PM PDT 24
Peak memory 197020 kb
Host smart-08cd7d36-ae31-409d-854c-7fec3bb67902
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4282345235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4282345235
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3977535999
Short name T866
Test name
Test status
Simulation time 57844643 ps
CPU time 1.07 seconds
Started Jun 29 06:24:57 PM PDT 24
Finished Jun 29 06:24:59 PM PDT 24
Peak memory 196820 kb
Host smart-fd84c5b0-32c5-42dc-822c-12bb240df3b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977535999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3977535999
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2143356071
Short name T903
Test name
Test status
Simulation time 602542989 ps
CPU time 1.02 seconds
Started Jun 29 06:24:59 PM PDT 24
Finished Jun 29 06:25:01 PM PDT 24
Peak memory 191932 kb
Host smart-b801d72a-937c-4a17-91de-432829c798b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2143356071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2143356071
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4237587500
Short name T875
Test name
Test status
Simulation time 98262346 ps
CPU time 0.87 seconds
Started Jun 29 06:24:58 PM PDT 24
Finished Jun 29 06:24:59 PM PDT 24
Peak memory 196788 kb
Host smart-39026f54-b952-49a2-85eb-f2152e64c812
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237587500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4237587500
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3601349803
Short name T942
Test name
Test status
Simulation time 49891715 ps
CPU time 0.94 seconds
Started Jun 29 06:25:01 PM PDT 24
Finished Jun 29 06:25:03 PM PDT 24
Peak memory 196852 kb
Host smart-136644c5-7c7c-4ed9-9744-c620350ab5c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3601349803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3601349803
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1832123866
Short name T891
Test name
Test status
Simulation time 72711406 ps
CPU time 1.42 seconds
Started Jun 29 06:24:57 PM PDT 24
Finished Jun 29 06:24:59 PM PDT 24
Peak memory 197080 kb
Host smart-6f89c08c-3708-4451-a7e1-d090bd62b8a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832123866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1832123866
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2696172146
Short name T893
Test name
Test status
Simulation time 1291651073 ps
CPU time 1.75 seconds
Started Jun 29 06:25:04 PM PDT 24
Finished Jun 29 06:25:06 PM PDT 24
Peak memory 197188 kb
Host smart-fcaee1ee-3da0-4769-9d5b-7872fb1a8bff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2696172146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2696172146
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2173226908
Short name T872
Test name
Test status
Simulation time 43448050 ps
CPU time 0.9 seconds
Started Jun 29 06:25:07 PM PDT 24
Finished Jun 29 06:25:08 PM PDT 24
Peak memory 197068 kb
Host smart-99bd9f1d-32ee-4ad5-b41c-c7701c4b024f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173226908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2173226908
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4006881874
Short name T910
Test name
Test status
Simulation time 558492536 ps
CPU time 1.24 seconds
Started Jun 29 06:24:51 PM PDT 24
Finished Jun 29 06:24:52 PM PDT 24
Peak memory 198488 kb
Host smart-58499a67-a2ca-43d6-ab84-00570758f5a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4006881874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.4006881874
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3217297436
Short name T930
Test name
Test status
Simulation time 53496117 ps
CPU time 1.46 seconds
Started Jun 29 06:24:51 PM PDT 24
Finished Jun 29 06:24:53 PM PDT 24
Peak memory 198440 kb
Host smart-b9c80e95-4910-4cf1-9356-061fdf8dfb7f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217297436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3217297436
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2386387876
Short name T938
Test name
Test status
Simulation time 50550371 ps
CPU time 1.14 seconds
Started Jun 29 06:25:06 PM PDT 24
Finished Jun 29 06:25:07 PM PDT 24
Peak memory 197156 kb
Host smart-748457a8-bdd1-4b71-bad0-170c3e9df557
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2386387876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2386387876
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1622977651
Short name T883
Test name
Test status
Simulation time 53705200 ps
CPU time 1.27 seconds
Started Jun 29 06:25:06 PM PDT 24
Finished Jun 29 06:25:08 PM PDT 24
Peak memory 196040 kb
Host smart-bf7ef5c6-01f2-46ed-8940-01f8494601c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622977651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1622977651
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.748076138
Short name T856
Test name
Test status
Simulation time 105599692 ps
CPU time 1.06 seconds
Started Jun 29 06:25:06 PM PDT 24
Finished Jun 29 06:25:07 PM PDT 24
Peak memory 198436 kb
Host smart-431716be-afbb-4718-87e2-3917fd50e97b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=748076138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.748076138
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2027867007
Short name T863
Test name
Test status
Simulation time 162997421 ps
CPU time 1.42 seconds
Started Jun 29 06:25:07 PM PDT 24
Finished Jun 29 06:25:09 PM PDT 24
Peak memory 198460 kb
Host smart-ffe47e69-bdb0-40c9-822f-1c678986a476
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027867007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2027867007
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1923782864
Short name T912
Test name
Test status
Simulation time 37962703 ps
CPU time 0.91 seconds
Started Jun 29 06:25:06 PM PDT 24
Finished Jun 29 06:25:08 PM PDT 24
Peak memory 196876 kb
Host smart-42feef06-1bcc-495e-971c-3197850b16fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1923782864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1923782864
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.398150382
Short name T933
Test name
Test status
Simulation time 331551117 ps
CPU time 1.25 seconds
Started Jun 29 06:25:05 PM PDT 24
Finished Jun 29 06:25:07 PM PDT 24
Peak memory 196368 kb
Host smart-cc27d407-959e-4fec-b077-9f704cc4aecb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398150382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.398150382
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3529286955
Short name T853
Test name
Test status
Simulation time 99564141 ps
CPU time 1.43 seconds
Started Jun 29 06:25:05 PM PDT 24
Finished Jun 29 06:25:07 PM PDT 24
Peak memory 197084 kb
Host smart-4e16f253-1cd2-4cad-bebb-061a534283a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3529286955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3529286955
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.229298347
Short name T879
Test name
Test status
Simulation time 84365418 ps
CPU time 0.94 seconds
Started Jun 29 06:25:07 PM PDT 24
Finished Jun 29 06:25:08 PM PDT 24
Peak memory 195912 kb
Host smart-0f1cc77e-555a-43b7-ab68-72a4372088fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229298347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.229298347
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1969480070
Short name T937
Test name
Test status
Simulation time 139594046 ps
CPU time 1.46 seconds
Started Jun 29 06:25:05 PM PDT 24
Finished Jun 29 06:25:07 PM PDT 24
Peak memory 198456 kb
Host smart-62488438-a002-4370-a198-991e62ee5f62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1969480070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1969480070
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1347435445
Short name T870
Test name
Test status
Simulation time 295406488 ps
CPU time 1.36 seconds
Started Jun 29 06:25:05 PM PDT 24
Finished Jun 29 06:25:07 PM PDT 24
Peak memory 197148 kb
Host smart-75957baa-66ad-4302-94fc-4244acf85a1e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347435445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1347435445
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3603361390
Short name T932
Test name
Test status
Simulation time 202750979 ps
CPU time 0.9 seconds
Started Jun 29 06:25:08 PM PDT 24
Finished Jun 29 06:25:09 PM PDT 24
Peak memory 195728 kb
Host smart-b44d469d-951a-4a1d-bfc1-a4251c2c0230
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3603361390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3603361390
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2802374801
Short name T881
Test name
Test status
Simulation time 68412159 ps
CPU time 0.91 seconds
Started Jun 29 06:25:08 PM PDT 24
Finished Jun 29 06:25:10 PM PDT 24
Peak memory 196916 kb
Host smart-1457cf61-93bd-4347-bacf-e3d1ad629233
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802374801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2802374801
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.123451864
Short name T905
Test name
Test status
Simulation time 92814461 ps
CPU time 0.93 seconds
Started Jun 29 06:25:06 PM PDT 24
Finished Jun 29 06:25:07 PM PDT 24
Peak memory 196872 kb
Host smart-0d0ee4db-f782-482e-836d-67c83bc143f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=123451864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.123451864
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1522929958
Short name T924
Test name
Test status
Simulation time 177094401 ps
CPU time 1.07 seconds
Started Jun 29 06:25:04 PM PDT 24
Finished Jun 29 06:25:06 PM PDT 24
Peak memory 196132 kb
Host smart-b1505f2c-18fb-4a50-a75d-4d2e7919c268
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522929958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1522929958
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4190577404
Short name T882
Test name
Test status
Simulation time 62983687 ps
CPU time 1.04 seconds
Started Jun 29 06:25:11 PM PDT 24
Finished Jun 29 06:25:12 PM PDT 24
Peak memory 198460 kb
Host smart-9dac4f5c-65cf-4102-9c2e-81164598475e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4190577404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4190577404
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.423997207
Short name T864
Test name
Test status
Simulation time 50803972 ps
CPU time 1.7 seconds
Started Jun 29 06:25:13 PM PDT 24
Finished Jun 29 06:25:15 PM PDT 24
Peak memory 197220 kb
Host smart-7397581f-26b5-48cb-aef6-7e3ab6e6dda3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423997207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.423997207
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2574558729
Short name T929
Test name
Test status
Simulation time 66404870 ps
CPU time 1.27 seconds
Started Jun 29 06:25:12 PM PDT 24
Finished Jun 29 06:25:14 PM PDT 24
Peak memory 197040 kb
Host smart-ab361d71-f569-4c15-a3d5-eba05dccc5ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2574558729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2574558729
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3399563937
Short name T859
Test name
Test status
Simulation time 54365504 ps
CPU time 1.6 seconds
Started Jun 29 06:25:11 PM PDT 24
Finished Jun 29 06:25:13 PM PDT 24
Peak memory 198436 kb
Host smart-a476b964-e145-4ebf-8dd1-c4d88e5cfd3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399563937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3399563937
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1392334283
Short name T890
Test name
Test status
Simulation time 157452934 ps
CPU time 1.34 seconds
Started Jun 29 06:25:13 PM PDT 24
Finished Jun 29 06:25:15 PM PDT 24
Peak memory 196320 kb
Host smart-a4f81436-b134-4c79-94cc-3001b9d061b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1392334283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1392334283
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3951389649
Short name T941
Test name
Test status
Simulation time 184642404 ps
CPU time 1.05 seconds
Started Jun 29 06:25:13 PM PDT 24
Finished Jun 29 06:25:15 PM PDT 24
Peak memory 196916 kb
Host smart-54ffe15a-b75d-4622-8979-63240da62b47
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951389649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3951389649
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4290751848
Short name T907
Test name
Test status
Simulation time 295723229 ps
CPU time 1.69 seconds
Started Jun 29 06:24:51 PM PDT 24
Finished Jun 29 06:24:53 PM PDT 24
Peak memory 197220 kb
Host smart-9c920f61-0266-4ae1-8043-2404ccd888eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4290751848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.4290751848
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1070905028
Short name T897
Test name
Test status
Simulation time 43138793 ps
CPU time 0.96 seconds
Started Jun 29 06:24:51 PM PDT 24
Finished Jun 29 06:24:52 PM PDT 24
Peak memory 196628 kb
Host smart-adb9b737-7b5c-41b0-9819-0c11db76262d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070905028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1070905028
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3560898156
Short name T923
Test name
Test status
Simulation time 84194088 ps
CPU time 1.28 seconds
Started Jun 29 06:25:12 PM PDT 24
Finished Jun 29 06:25:13 PM PDT 24
Peak memory 196092 kb
Host smart-b606690f-3596-4db2-8c29-17b507375827
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3560898156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3560898156
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730268056
Short name T934
Test name
Test status
Simulation time 179067462 ps
CPU time 1.06 seconds
Started Jun 29 06:25:17 PM PDT 24
Finished Jun 29 06:25:19 PM PDT 24
Peak memory 196904 kb
Host smart-efb90644-3277-4b69-aa79-835eab865461
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730268056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.730268056
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3250353053
Short name T846
Test name
Test status
Simulation time 25584575 ps
CPU time 0.81 seconds
Started Jun 29 06:25:13 PM PDT 24
Finished Jun 29 06:25:14 PM PDT 24
Peak memory 195772 kb
Host smart-3aa14a28-9824-4ca9-bce9-7ff33cb9a2bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3250353053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3250353053
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.650978704
Short name T894
Test name
Test status
Simulation time 213673595 ps
CPU time 1.18 seconds
Started Jun 29 06:25:12 PM PDT 24
Finished Jun 29 06:25:13 PM PDT 24
Peak memory 196988 kb
Host smart-4d6a0184-2a46-4495-b0a5-66f0423ce9d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650978704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.650978704
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.642056691
Short name T868
Test name
Test status
Simulation time 157289409 ps
CPU time 1.38 seconds
Started Jun 29 06:25:12 PM PDT 24
Finished Jun 29 06:25:14 PM PDT 24
Peak memory 196956 kb
Host smart-de206ab9-3309-40d5-adf9-18888a53d6c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=642056691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.642056691
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2267729802
Short name T917
Test name
Test status
Simulation time 48888372 ps
CPU time 1.59 seconds
Started Jun 29 06:25:13 PM PDT 24
Finished Jun 29 06:25:15 PM PDT 24
Peak memory 197228 kb
Host smart-ce808402-a589-4976-b3d6-47b7a37a1375
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267729802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2267729802
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.384114593
Short name T884
Test name
Test status
Simulation time 141959232 ps
CPU time 1.21 seconds
Started Jun 29 06:25:14 PM PDT 24
Finished Jun 29 06:25:16 PM PDT 24
Peak memory 196984 kb
Host smart-f494cc74-8e3e-4612-a9ca-8ad80d56bdec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=384114593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.384114593
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1708150751
Short name T928
Test name
Test status
Simulation time 109590770 ps
CPU time 1.16 seconds
Started Jun 29 06:25:14 PM PDT 24
Finished Jun 29 06:25:16 PM PDT 24
Peak memory 196828 kb
Host smart-8a39ecac-6cf0-43b8-92ef-5d443d5bb0d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708150751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1708150751
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2327227388
Short name T852
Test name
Test status
Simulation time 221651960 ps
CPU time 1.3 seconds
Started Jun 29 06:25:13 PM PDT 24
Finished Jun 29 06:25:14 PM PDT 24
Peak memory 196976 kb
Host smart-41e73fa4-9459-4a6d-9ec5-a1c9afd88768
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2327227388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2327227388
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2192043892
Short name T935
Test name
Test status
Simulation time 47660037 ps
CPU time 0.98 seconds
Started Jun 29 06:25:13 PM PDT 24
Finished Jun 29 06:25:14 PM PDT 24
Peak memory 197036 kb
Host smart-4d1b1023-a303-4475-8042-cfffc3651e8d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192043892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2192043892
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1198265410
Short name T851
Test name
Test status
Simulation time 117035816 ps
CPU time 0.94 seconds
Started Jun 29 06:25:12 PM PDT 24
Finished Jun 29 06:25:13 PM PDT 24
Peak memory 198292 kb
Host smart-ab4a4351-1834-4e18-a5d3-11a7e4c3c6e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1198265410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1198265410
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.654798801
Short name T892
Test name
Test status
Simulation time 263113597 ps
CPU time 1.37 seconds
Started Jun 29 06:25:14 PM PDT 24
Finished Jun 29 06:25:16 PM PDT 24
Peak memory 197108 kb
Host smart-3b83864b-f2bd-4cfa-91dc-e833e521e2a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654798801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.654798801
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2254530404
Short name T844
Test name
Test status
Simulation time 96701282 ps
CPU time 1.64 seconds
Started Jun 29 06:25:14 PM PDT 24
Finished Jun 29 06:25:16 PM PDT 24
Peak memory 197220 kb
Host smart-3f248a64-a8bd-4097-b986-853fbd4f4348
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2254530404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2254530404
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2274742688
Short name T896
Test name
Test status
Simulation time 64074114 ps
CPU time 1.15 seconds
Started Jun 29 06:25:15 PM PDT 24
Finished Jun 29 06:25:16 PM PDT 24
Peak memory 197160 kb
Host smart-66bb42e6-64af-4864-b02d-94544e6a8554
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274742688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2274742688
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1815704646
Short name T854
Test name
Test status
Simulation time 70171360 ps
CPU time 1.34 seconds
Started Jun 29 06:25:15 PM PDT 24
Finished Jun 29 06:25:17 PM PDT 24
Peak memory 196996 kb
Host smart-ac462cf8-c76f-49e6-a833-0b6b6fbaad95
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1815704646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1815704646
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.430257307
Short name T936
Test name
Test status
Simulation time 30827365 ps
CPU time 0.84 seconds
Started Jun 29 06:25:11 PM PDT 24
Finished Jun 29 06:25:13 PM PDT 24
Peak memory 196468 kb
Host smart-8c45c661-1186-4fc1-b034-6a519492752e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430257307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.430257307
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1018534409
Short name T877
Test name
Test status
Simulation time 64302524 ps
CPU time 1.29 seconds
Started Jun 29 06:25:14 PM PDT 24
Finished Jun 29 06:25:16 PM PDT 24
Peak memory 196360 kb
Host smart-b252d4e3-ab9c-4dbc-9eda-b61f57a96ce6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1018534409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1018534409
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.850696866
Short name T888
Test name
Test status
Simulation time 61247231 ps
CPU time 1.25 seconds
Started Jun 29 06:25:14 PM PDT 24
Finished Jun 29 06:25:15 PM PDT 24
Peak memory 196800 kb
Host smart-05e86a85-df32-4f49-b60d-b859c60eded7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850696866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.850696866
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2474479480
Short name T922
Test name
Test status
Simulation time 295892532 ps
CPU time 1.51 seconds
Started Jun 29 06:25:14 PM PDT 24
Finished Jun 29 06:25:16 PM PDT 24
Peak memory 197208 kb
Host smart-4d626a31-6e0b-4d3b-8293-862f9cf9ee93
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2474479480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2474479480
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.778076788
Short name T889
Test name
Test status
Simulation time 497543522 ps
CPU time 0.98 seconds
Started Jun 29 06:25:16 PM PDT 24
Finished Jun 29 06:25:17 PM PDT 24
Peak memory 198284 kb
Host smart-26a0a13d-e3ba-46fc-8f39-83690a7f5a46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778076788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.778076788
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1343651067
Short name T900
Test name
Test status
Simulation time 50974494 ps
CPU time 1.13 seconds
Started Jun 29 06:24:52 PM PDT 24
Finished Jun 29 06:24:54 PM PDT 24
Peak memory 198468 kb
Host smart-e5fa98c3-5d85-46dd-ab18-c9aff5c99e22
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1343651067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1343651067
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2235971087
Short name T873
Test name
Test status
Simulation time 46356640 ps
CPU time 1.36 seconds
Started Jun 29 06:24:55 PM PDT 24
Finished Jun 29 06:24:57 PM PDT 24
Peak memory 197588 kb
Host smart-b1f3c5e3-5c45-4e24-8318-d771b9f22426
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235971087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2235971087
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2001558456
Short name T925
Test name
Test status
Simulation time 29663067 ps
CPU time 0.97 seconds
Started Jun 29 06:25:18 PM PDT 24
Finished Jun 29 06:25:19 PM PDT 24
Peak memory 197036 kb
Host smart-38fcebea-2b02-4f68-9b2f-997ce901cad6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2001558456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2001558456
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3093453388
Short name T931
Test name
Test status
Simulation time 62814847 ps
CPU time 1.25 seconds
Started Jun 29 06:25:25 PM PDT 24
Finished Jun 29 06:25:26 PM PDT 24
Peak memory 196296 kb
Host smart-36e3e788-7fbc-4838-82d4-f8bf7bd891ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093453388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3093453388
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3842356295
Short name T909
Test name
Test status
Simulation time 41365202 ps
CPU time 1.32 seconds
Started Jun 29 06:25:20 PM PDT 24
Finished Jun 29 06:25:22 PM PDT 24
Peak memory 197320 kb
Host smart-bfdda618-1549-4f21-aab0-a30f8004045d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3842356295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3842356295
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.650980680
Short name T902
Test name
Test status
Simulation time 354806799 ps
CPU time 1.38 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:23 PM PDT 24
Peak memory 196100 kb
Host smart-91f477a5-ccf6-4dec-a788-0c2b071b13b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650980680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.650980680
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1926868452
Short name T860
Test name
Test status
Simulation time 239372864 ps
CPU time 1.33 seconds
Started Jun 29 06:25:23 PM PDT 24
Finished Jun 29 06:25:24 PM PDT 24
Peak memory 197352 kb
Host smart-e0cad057-d7a7-4d14-a795-e6ec3304895f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1926868452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1926868452
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3537299204
Short name T895
Test name
Test status
Simulation time 184200376 ps
CPU time 1.06 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:23 PM PDT 24
Peak memory 196268 kb
Host smart-51a92301-32ac-4e90-ad0d-eb99adee0fbe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537299204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3537299204
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3854572670
Short name T848
Test name
Test status
Simulation time 146113585 ps
CPU time 1.43 seconds
Started Jun 29 06:25:40 PM PDT 24
Finished Jun 29 06:25:42 PM PDT 24
Peak memory 196092 kb
Host smart-9b3be715-5815-4c81-98b3-ca1465d66f9a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3854572670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3854572670
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2017224338
Short name T847
Test name
Test status
Simulation time 68385016 ps
CPU time 1.25 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:23 PM PDT 24
Peak memory 197000 kb
Host smart-0539961d-f934-46f7-b64c-0e1ea5db5463
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017224338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2017224338
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2678515684
Short name T919
Test name
Test status
Simulation time 149647056 ps
CPU time 1.04 seconds
Started Jun 29 06:25:24 PM PDT 24
Finished Jun 29 06:25:25 PM PDT 24
Peak memory 196316 kb
Host smart-67339c70-32d4-44ae-88cc-c2df9b94e139
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2678515684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2678515684
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1667320874
Short name T906
Test name
Test status
Simulation time 105455053 ps
CPU time 1.01 seconds
Started Jun 29 06:25:22 PM PDT 24
Finished Jun 29 06:25:23 PM PDT 24
Peak memory 196916 kb
Host smart-77270849-569a-4c8a-ba6c-881d2c89426d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667320874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1667320874
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3789928419
Short name T843
Test name
Test status
Simulation time 215896233 ps
CPU time 1.17 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:23 PM PDT 24
Peak memory 197008 kb
Host smart-713f8df9-1147-4c77-af14-b94d3db87865
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3789928419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3789928419
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3378058262
Short name T874
Test name
Test status
Simulation time 162682616 ps
CPU time 1.15 seconds
Started Jun 29 06:25:22 PM PDT 24
Finished Jun 29 06:25:23 PM PDT 24
Peak memory 196360 kb
Host smart-dbc435c6-7162-44e8-97c3-d6fd412b6401
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378058262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3378058262
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3339386719
Short name T904
Test name
Test status
Simulation time 62486027 ps
CPU time 0.97 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:22 PM PDT 24
Peak memory 196532 kb
Host smart-e8a15f3c-4fbc-4cd5-9e5f-9574f5f632f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3339386719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3339386719
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.122648117
Short name T861
Test name
Test status
Simulation time 88150372 ps
CPU time 1.56 seconds
Started Jun 29 06:25:26 PM PDT 24
Finished Jun 29 06:25:28 PM PDT 24
Peak memory 198452 kb
Host smart-2508baad-120b-4ff9-9273-422b6045743a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122648117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.122648117
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.459727106
Short name T865
Test name
Test status
Simulation time 83653305 ps
CPU time 1.43 seconds
Started Jun 29 06:25:26 PM PDT 24
Finished Jun 29 06:25:27 PM PDT 24
Peak memory 197444 kb
Host smart-565afbfb-ac3b-42c9-96fd-11e26f2d9322
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=459727106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.459727106
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.952395560
Short name T940
Test name
Test status
Simulation time 398551353 ps
CPU time 1.53 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:22 PM PDT 24
Peak memory 197084 kb
Host smart-477102a2-cd4c-4f43-90f9-2f2db43231c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952395560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.952395560
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3721116952
Short name T915
Test name
Test status
Simulation time 168608193 ps
CPU time 1.05 seconds
Started Jun 29 06:25:26 PM PDT 24
Finished Jun 29 06:25:27 PM PDT 24
Peak memory 198500 kb
Host smart-f606d8b6-bd99-43b8-99ab-404a6b079a39
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3721116952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3721116952
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3246712212
Short name T926
Test name
Test status
Simulation time 200323697 ps
CPU time 1.23 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:23 PM PDT 24
Peak memory 196100 kb
Host smart-b3c7a216-3755-4b73-846c-88381e6fbe26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246712212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3246712212
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2071444712
Short name T920
Test name
Test status
Simulation time 79088514 ps
CPU time 0.88 seconds
Started Jun 29 06:25:20 PM PDT 24
Finished Jun 29 06:25:22 PM PDT 24
Peak memory 195876 kb
Host smart-6c01270e-c3f1-4ffc-8ea6-659f2b3c3497
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2071444712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2071444712
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3482423198
Short name T914
Test name
Test status
Simulation time 321518883 ps
CPU time 1.34 seconds
Started Jun 29 06:25:21 PM PDT 24
Finished Jun 29 06:25:22 PM PDT 24
Peak memory 197008 kb
Host smart-9d5430aa-0fcd-4413-a751-5d0881d823e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482423198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3482423198
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.447174233
Short name T899
Test name
Test status
Simulation time 208711171 ps
CPU time 1.26 seconds
Started Jun 29 06:24:50 PM PDT 24
Finished Jun 29 06:24:52 PM PDT 24
Peak memory 197200 kb
Host smart-587d76d1-fcf1-4b75-82a3-c9fe2fefb6b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=447174233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.447174233
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1986514354
Short name T855
Test name
Test status
Simulation time 52787806 ps
CPU time 1.43 seconds
Started Jun 29 06:24:50 PM PDT 24
Finished Jun 29 06:24:52 PM PDT 24
Peak memory 197160 kb
Host smart-0ee36dfa-848f-4857-b387-5462a8af80ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986514354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1986514354
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.877590996
Short name T869
Test name
Test status
Simulation time 134143369 ps
CPU time 1.28 seconds
Started Jun 29 06:24:50 PM PDT 24
Finished Jun 29 06:24:52 PM PDT 24
Peak memory 197016 kb
Host smart-d4fbdb9d-87c6-4505-bb59-b78bd3f98f72
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=877590996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.877590996
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.911365001
Short name T927
Test name
Test status
Simulation time 68879975 ps
CPU time 1.4 seconds
Started Jun 29 06:24:54 PM PDT 24
Finished Jun 29 06:24:55 PM PDT 24
Peak memory 197504 kb
Host smart-ef0bb9e1-78e9-4106-a0a3-080f82b0c1a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911365001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.911365001
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.946372002
Short name T876
Test name
Test status
Simulation time 239637663 ps
CPU time 1.47 seconds
Started Jun 29 06:24:52 PM PDT 24
Finished Jun 29 06:24:54 PM PDT 24
Peak memory 197804 kb
Host smart-eb7ed284-fe99-4a43-a541-8f6225b5f424
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=946372002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.946372002
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.143243087
Short name T880
Test name
Test status
Simulation time 19581035 ps
CPU time 0.83 seconds
Started Jun 29 06:24:53 PM PDT 24
Finished Jun 29 06:24:54 PM PDT 24
Peak memory 194708 kb
Host smart-9d9f7839-33ce-4097-af59-c83e86d06025
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143243087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.143243087
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.608670529
Short name T862
Test name
Test status
Simulation time 33273212 ps
CPU time 0.89 seconds
Started Jun 29 06:24:50 PM PDT 24
Finished Jun 29 06:24:51 PM PDT 24
Peak memory 196564 kb
Host smart-dfe05682-1841-43fa-a394-3168722d6310
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=608670529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.608670529
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4271396070
Short name T849
Test name
Test status
Simulation time 154637378 ps
CPU time 1.43 seconds
Started Jun 29 06:24:52 PM PDT 24
Finished Jun 29 06:24:54 PM PDT 24
Peak memory 197048 kb
Host smart-c1e4bdea-35e7-4a53-a4c1-5ab4d88141b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271396070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4271396070
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2759161779
Short name T887
Test name
Test status
Simulation time 88130537 ps
CPU time 1.07 seconds
Started Jun 29 06:24:51 PM PDT 24
Finished Jun 29 06:24:52 PM PDT 24
Peak memory 198372 kb
Host smart-b00de158-cc29-481a-bbd8-7b81e5d19a11
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2759161779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2759161779
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest


Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2696624864
Short name T857
Test name
Test status
Simulation time 71717921 ps
CPU time 1.07 seconds
Started Jun 29 06:24:59 PM PDT 24
Finished Jun 29 06:25:01 PM PDT 24
Peak memory 192132 kb
Host smart-5875f49a-ca82-4aba-9ff2-4558d6ee0e7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696624864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2696624864
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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