Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4439551	1			T22	50		T23	879		T24	1
all_pins[1]	4439551	1			T22	50		T23	879		T24	1
all_pins[2]	4439551	1			T22	50		T23	879		T24	1
all_pins[3]	4439551	1			T22	50		T23	879		T24	1
all_pins[4]	4439551	1			T22	50		T23	879		T24	1
all_pins[5]	4439551	1			T22	50		T23	879		T24	1
all_pins[6]	4439551	1			T22	50		T23	879		T24	1
all_pins[7]	4439551	1			T22	50		T23	879		T24	1
all_pins[8]	4439551	1			T22	50		T23	879		T24	1
all_pins[9]	4439551	1			T22	50		T23	879		T24	1
all_pins[10]	4439551	1			T22	50		T23	879		T24	1
all_pins[11]	4439551	1			T22	50		T23	879		T24	1
all_pins[12]	4439551	1			T22	50		T23	879		T24	1
all_pins[13]	4439551	1			T22	50		T23	879		T24	1
all_pins[14]	4439551	1			T22	50		T23	879		T24	1
all_pins[15]	4439551	1			T22	50		T23	879		T24	1
all_pins[16]	4439551	1			T22	50		T23	879		T24	1
all_pins[17]	4439551	1			T22	50		T23	879		T24	1
all_pins[18]	4439551	1			T22	50		T23	879		T24	1
all_pins[19]	4439551	1			T22	50		T23	879		T24	1
all_pins[20]	4439551	1			T22	50		T23	879		T24	1
all_pins[21]	4439551	1			T22	50		T23	879		T24	1
all_pins[22]	4439551	1			T22	50		T23	879		T24	1
all_pins[23]	4439551	1			T22	50		T23	879		T24	1
all_pins[24]	4439551	1			T22	50		T23	879		T24	1
all_pins[25]	4439551	1			T22	50		T23	879		T24	1
all_pins[26]	4439551	1			T22	50		T23	879		T24	1
all_pins[27]	4439551	1			T22	50		T23	879		T24	1
all_pins[28]	4439551	1			T22	50		T23	879		T24	1
all_pins[29]	4439551	1			T22	50		T23	879		T24	1
all_pins[30]	4439551	1			T22	50		T23	879		T24	1
all_pins[31]	4439551	1			T22	50		T23	879		T24	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	88250616	1			T22	1385		T23	17030		T24	32
values[0x1]	53815016	1			T22	215		T23	11098		T29	2802
transitions[0x0=>0x1]	32245189	1			T22	164		T23	6611		T29	1704
transitions[0x1=>0x0]	32245041	1			T22	163		T23	6611		T29	1704

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2761527	1			T22	37		T23	586		T24	1
all_pins[0]	values[0x1]	1678024	1			T22	13		T23	293		T29	91
all_pins[0]	transitions[0x0=>0x1]	1035802	1			T22	13		T23	193		T29	44
all_pins[0]	transitions[0x1=>0x0]	1041714	1			T22	2		T23	189		T29	65
all_pins[1]	values[0x0]	2759877	1			T22	39		T23	571		T24	1
all_pins[1]	values[0x1]	1679674	1			T22	11		T23	308		T29	80
all_pins[1]	transitions[0x0=>0x1]	1005470	1			T22	3		T23	175		T29	39
all_pins[1]	transitions[0x1=>0x0]	1003820	1			T22	5		T23	160		T29	50
all_pins[2]	values[0x0]	2752991	1			T22	49		T23	512		T24	1
all_pins[2]	values[0x1]	1686560	1			T22	1		T23	367		T29	97
all_pins[2]	transitions[0x0=>0x1]	1009762	1			T22	1		T23	217		T29	71
all_pins[2]	transitions[0x1=>0x0]	1002876	1			T22	11		T23	158		T29	54
all_pins[3]	values[0x0]	2757324	1			T22	47		T23	482		T24	1
all_pins[3]	values[0x1]	1682227	1			T22	3		T23	397		T29	87
all_pins[3]	transitions[0x0=>0x1]	1005265	1			T22	3		T23	249		T29	58
all_pins[3]	transitions[0x1=>0x0]	1009598	1			T22	1		T23	219		T29	68
all_pins[4]	values[0x0]	2755900	1			T22	40		T23	539		T24	1
all_pins[4]	values[0x1]	1683651	1			T22	10		T23	340		T29	70
all_pins[4]	transitions[0x0=>0x1]	1007586	1			T22	10		T23	193		T29	50
all_pins[4]	transitions[0x1=>0x0]	1006162	1			T22	3		T23	250		T29	67
all_pins[5]	values[0x0]	2759783	1			T22	39		T23	574		T24	1
all_pins[5]	values[0x1]	1679768	1			T22	11		T23	305		T29	123
all_pins[5]	transitions[0x0=>0x1]	1003485	1			T22	6		T23	159		T29	85
all_pins[5]	transitions[0x1=>0x0]	1007368	1			T22	5		T23	194		T29	32
all_pins[6]	values[0x0]	2752795	1			T22	50		T23	573		T24	1
all_pins[6]	values[0x1]	1686756	1			T23	306		T29	97		T30	49
all_pins[6]	transitions[0x0=>0x1]	1010513	1			T23	204		T29	30		T30	23
all_pins[6]	transitions[0x1=>0x0]	1003525	1			T22	11		T23	203		T29	56
all_pins[7]	values[0x0]	2758344	1			T22	46		T23	502		T24	1
all_pins[7]	values[0x1]	1681207	1			T22	4		T23	377		T29	113
all_pins[7]	transitions[0x0=>0x1]	1004903	1			T22	4		T23	250		T29	76
all_pins[7]	transitions[0x1=>0x0]	1010452	1			T23	179		T29	60		T30	46
all_pins[8]	values[0x0]	2760724	1			T22	47		T23	502		T24	1
all_pins[8]	values[0x1]	1678827	1			T22	3		T23	377		T29	78
all_pins[8]	transitions[0x0=>0x1]	1006637	1			T22	3		T23	205		T29	31
all_pins[8]	transitions[0x1=>0x0]	1009017	1			T22	4		T23	205		T29	66
all_pins[9]	values[0x0]	2760675	1			T22	42		T23	516		T24	1
all_pins[9]	values[0x1]	1678876	1			T22	8		T23	363		T29	85
all_pins[9]	transitions[0x0=>0x1]	1007280	1			T22	7		T23	212		T29	43
all_pins[9]	transitions[0x1=>0x0]	1007231	1			T22	2		T23	226		T29	36
all_pins[10]	values[0x0]	2758006	1			T22	40		T23	508		T24	1
all_pins[10]	values[0x1]	1681545	1			T22	10		T23	371		T29	90
all_pins[10]	transitions[0x0=>0x1]	1008624	1			T22	8		T23	191		T29	60
all_pins[10]	transitions[0x1=>0x0]	1005955	1			T22	6		T23	183		T29	55
all_pins[11]	values[0x0]	2757645	1			T22	38		T23	511		T24	1
all_pins[11]	values[0x1]	1681906	1			T22	12		T23	368		T29	103
all_pins[11]	transitions[0x0=>0x1]	1007003	1			T22	10		T23	201		T29	59
all_pins[11]	transitions[0x1=>0x0]	1006642	1			T22	8		T23	204		T29	46
all_pins[12]	values[0x0]	2763580	1			T22	38		T23	540		T24	1
all_pins[12]	values[0x1]	1675971	1			T22	12		T23	339		T29	122
all_pins[12]	transitions[0x0=>0x1]	1002852	1			T22	10		T23	202		T29	66
all_pins[12]	transitions[0x1=>0x0]	1008787	1			T22	10		T23	231		T29	47
all_pins[13]	values[0x0]	2755750	1			T22	48		T23	440		T24	1
all_pins[13]	values[0x1]	1683801	1			T22	2		T23	439		T29	89
all_pins[13]	transitions[0x0=>0x1]	1009918	1			T22	2		T23	285		T29	39
all_pins[13]	transitions[0x1=>0x0]	1002088	1			T22	12		T23	185		T29	72
all_pins[14]	values[0x0]	2760128	1			T22	45		T23	565		T24	1
all_pins[14]	values[0x1]	1679423	1			T22	5		T23	314		T29	80
all_pins[14]	transitions[0x0=>0x1]	1005411	1			T22	5		T23	137		T29	49
all_pins[14]	transitions[0x1=>0x0]	1009789	1			T22	2		T23	262		T29	58
all_pins[15]	values[0x0]	2751426	1			T22	45		T23	596		T24	1
all_pins[15]	values[0x1]	1688125	1			T22	5		T23	283		T29	51
all_pins[15]	transitions[0x0=>0x1]	1011204	1			T23	219		T29	37		T30	22
all_pins[15]	transitions[0x1=>0x0]	1002502	1			T23	250		T29	66		T30	17
all_pins[16]	values[0x0]	2759452	1			T22	40		T23	469		T24	1
all_pins[16]	values[0x1]	1680099	1			T22	10		T23	410		T29	92
all_pins[16]	transitions[0x0=>0x1]	1004037	1			T22	8		T23	268		T29	61
all_pins[16]	transitions[0x1=>0x0]	1012063	1			T22	3		T23	141		T29	20
all_pins[17]	values[0x0]	2756998	1			T22	41		T23	486		T24	1
all_pins[17]	values[0x1]	1682553	1			T22	9		T23	393		T29	115
all_pins[17]	transitions[0x0=>0x1]	1007723	1			T22	6		T23	219		T29	61
all_pins[17]	transitions[0x1=>0x0]	1005269	1			T22	7		T23	236		T29	38
all_pins[18]	values[0x0]	2752550	1			T22	49		T23	491		T24	1
all_pins[18]	values[0x1]	1687001	1			T22	1		T23	388		T29	85
all_pins[18]	transitions[0x0=>0x1]	1009200	1			T22	1		T23	186		T29	40
all_pins[18]	transitions[0x1=>0x0]	1004752	1			T22	9		T23	191		T29	70
all_pins[19]	values[0x0]	2755279	1			T22	42		T23	541		T24	1
all_pins[19]	values[0x1]	1684272	1			T22	8		T23	338		T29	98
all_pins[19]	transitions[0x0=>0x1]	1004889	1			T22	7		T23	158		T29	68
all_pins[19]	transitions[0x1=>0x0]	1007618	1			T23	208		T29	55		T30	19
all_pins[20]	values[0x0]	2758183	1			T22	37		T23	488		T24	1
all_pins[20]	values[0x1]	1681368	1			T22	13		T23	391		T29	61
all_pins[20]	transitions[0x0=>0x1]	1003414	1			T22	6		T23	251		T29	47
all_pins[20]	transitions[0x1=>0x0]	1006318	1			T22	1		T23	198		T29	84
all_pins[21]	values[0x0]	2760383	1			T22	42		T23	530		T24	1
all_pins[21]	values[0x1]	1679168	1			T22	8		T23	349		T29	91
all_pins[21]	transitions[0x0=>0x1]	1005930	1			T22	4		T23	194		T29	70
all_pins[21]	transitions[0x1=>0x0]	1008130	1			T22	9		T23	236		T29	40
all_pins[22]	values[0x0]	2757003	1			T22	46		T23	549		T24	1
all_pins[22]	values[0x1]	1682548	1			T22	4		T23	330		T29	72
all_pins[22]	transitions[0x0=>0x1]	1008338	1			T22	3		T23	206		T29	44
all_pins[22]	transitions[0x1=>0x0]	1004958	1			T22	7		T23	225		T29	63
all_pins[23]	values[0x0]	2756075	1			T22	41		T23	569		T24	1
all_pins[23]	values[0x1]	1683476	1			T22	9		T23	310		T29	83
all_pins[23]	transitions[0x0=>0x1]	1008147	1			T22	9		T23	205		T29	61
all_pins[23]	transitions[0x1=>0x0]	1007219	1			T22	4		T23	225		T29	50
all_pins[24]	values[0x0]	2756941	1			T22	48		T23	532		T24	1
all_pins[24]	values[0x1]	1682610	1			T22	2		T23	347		T29	109
all_pins[24]	transitions[0x0=>0x1]	1006484	1			T23	223		T29	77		T30	7
all_pins[24]	transitions[0x1=>0x0]	1007350	1			T22	7		T23	186		T29	51
all_pins[25]	values[0x0]	2756917	1			T22	46		T23	544		T24	1
all_pins[25]	values[0x1]	1682634	1			T22	4		T23	335		T29	61
all_pins[25]	transitions[0x0=>0x1]	1006087	1			T22	4		T23	208		T29	28
all_pins[25]	transitions[0x1=>0x0]	1006063	1			T22	2		T23	220		T29	76
all_pins[26]	values[0x0]	2763447	1			T22	43		T23	533		T24	1
all_pins[26]	values[0x1]	1676104	1			T22	7		T23	346		T29	66
all_pins[26]	transitions[0x0=>0x1]	1002964	1			T22	7		T23	224		T29	46
all_pins[26]	transitions[0x1=>0x0]	1009494	1			T22	4		T23	213		T29	41
all_pins[27]	values[0x0]	2758129	1			T22	39		T23	555		T24	1
all_pins[27]	values[0x1]	1681422	1			T22	11		T23	324		T29	57
all_pins[27]	transitions[0x0=>0x1]	1009264	1			T22	11		T23	220		T29	43
all_pins[27]	transitions[0x1=>0x0]	1003946	1			T22	7		T23	242		T29	52
all_pins[28]	values[0x0]	2757711	1			T22	46		T23	495		T24	1
all_pins[28]	values[0x1]	1681840	1			T22	4		T23	384		T29	96
all_pins[28]	transitions[0x0=>0x1]	1005740	1			T22	1		T23	231		T29	63
all_pins[28]	transitions[0x1=>0x0]	1005322	1			T22	8		T23	171		T29	24
all_pins[29]	values[0x0]	2757658	1			T22	41		T23	607		T24	1
all_pins[29]	values[0x1]	1681893	1			T22	9		T23	272		T29	90
all_pins[29]	transitions[0x0=>0x1]	1005639	1			T22	8		T23	133		T29	43
all_pins[29]	transitions[0x1=>0x0]	1005586	1			T22	3		T23	245		T29	49
all_pins[30]	values[0x0]	2761948	1			T22	47		T23	534		T24	1
all_pins[30]	values[0x1]	1677603	1			T22	3		T23	345		T29	58
all_pins[30]	transitions[0x0=>0x1]	1003821	1			T22	3		T23	224		T29	40
all_pins[30]	transitions[0x1=>0x0]	1008111	1			T22	9		T23	151		T29	72
all_pins[31]	values[0x0]	2755467	1			T22	47		T23	590		T24	1
all_pins[31]	values[0x1]	1684084	1			T22	3		T23	289		T29	112
all_pins[31]	transitions[0x0=>0x1]	1011797	1			T22	1		T23	169		T29	75
all_pins[31]	transitions[0x1=>0x0]	1005316	1			T22	1		T23	225		T29	21