Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14631726	1			T22	76		T23	2723		T24	403
all_values[1]	14631726	1			T22	76		T23	2723		T24	403
all_values[2]	14631726	1			T22	76		T23	2723		T24	403
all_values[3]	14631726	1			T22	76		T23	2723		T24	403
all_values[4]	14631726	1			T22	76		T23	2723		T24	403
all_values[5]	14631726	1			T22	76		T23	2723		T24	403
all_values[6]	14631726	1			T22	76		T23	2723		T24	403
all_values[7]	14631726	1			T22	76		T23	2723		T24	403
all_values[8]	14631726	1			T22	76		T23	2723		T24	403
all_values[9]	14631726	1			T22	76		T23	2723		T24	403
all_values[10]	14631726	1			T22	76		T23	2723		T24	403
all_values[11]	14631726	1			T22	76		T23	2723		T24	403
all_values[12]	14631726	1			T22	76		T23	2723		T24	403
all_values[13]	14631726	1			T22	76		T23	2723		T24	403
all_values[14]	14631726	1			T22	76		T23	2723		T24	403
all_values[15]	14631726	1			T22	76		T23	2723		T24	403
all_values[16]	14631726	1			T22	76		T23	2723		T24	403
all_values[17]	14631726	1			T22	76		T23	2723		T24	403
all_values[18]	14631726	1			T22	76		T23	2723		T24	403
all_values[19]	14631726	1			T22	76		T23	2723		T24	403
all_values[20]	14631726	1			T22	76		T23	2723		T24	403
all_values[21]	14631726	1			T22	76		T23	2723		T24	403
all_values[22]	14631726	1			T22	76		T23	2723		T24	403
all_values[23]	14631726	1			T22	76		T23	2723		T24	403
all_values[24]	14631726	1			T22	76		T23	2723		T24	403
all_values[25]	14631726	1			T22	76		T23	2723		T24	403
all_values[26]	14631726	1			T22	76		T23	2723		T24	403
all_values[27]	14631726	1			T22	76		T23	2723		T24	403
all_values[28]	14631726	1			T22	76		T23	2723		T24	403
all_values[29]	14631726	1			T22	76		T23	2723		T24	403
all_values[30]	14631726	1			T22	76		T23	2723		T24	403
all_values[31]	14631726	1			T22	76		T23	2723		T24	403

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266030588

1

T22

1728

T23

42752

T24

12896

auto[1]

202184644

1

T22

704

T23

44384

T29

6425

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102256779

1

T22

1699

T23

6766

T24

12896

auto[1]

365958453

1

T22

733

T23

80370

T29

10539

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

462867449

1

T22

2292

T23

87136

T24

12896

auto[1]

5347783

1

T22

140

T30

379

T32

178

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2587010	1			T22	27		T23	72		T24	403
all_values[0]	auto[0]	auto[0]	auto[1]	5651972	1			T22	12		T23	1397		T29	166
all_values[0]	auto[0]	auto[1]	auto[0]	611226	1			T22	19		T23	102		T29	11
all_values[0]	auto[0]	auto[1]	auto[1]	5614252	1			T22	12		T23	1152		T29	177
all_values[0]	auto[1]	auto[0]	auto[1]	84148	1			T22	2		T30	5		T32	1
all_values[0]	auto[1]	auto[1]	auto[1]	83118	1			T22	4		T30	7		T32	6
all_values[1]	auto[0]	auto[0]	auto[0]	2587586	1			T22	37		T23	126		T24	403
all_values[1]	auto[0]	auto[0]	auto[1]	5670300	1			T22	15		T23	1134		T29	174
all_values[1]	auto[0]	auto[1]	auto[0]	602941	1			T22	10		T23	173		T29	23
all_values[1]	auto[0]	auto[1]	auto[1]	5604166	1			T22	9		T23	1290		T29	161
all_values[1]	auto[1]	auto[0]	auto[1]	83800	1			T22	1		T30	3		T32	8
all_values[1]	auto[1]	auto[1]	auto[1]	82933	1			T22	4		T30	4		T32	2
all_values[2]	auto[0]	auto[0]	auto[0]	2574409	1			T22	38		T23	151		T24	403
all_values[2]	auto[0]	auto[0]	auto[1]	5612076	1			T22	12		T23	1127		T29	165
all_values[2]	auto[0]	auto[1]	auto[0]	618668	1			T22	22		T23	81		T29	37
all_values[2]	auto[0]	auto[1]	auto[1]	5659763	1			T23	1364		T29	174		T30	23
all_values[2]	auto[1]	auto[0]	auto[1]	83171	1			T22	3		T30	11		T32	2
all_values[2]	auto[1]	auto[1]	auto[1]	83639	1			T22	1		T30	1		T32	4
all_values[3]	auto[0]	auto[0]	auto[0]	2581130	1			T22	39		T23	76		T24	403
all_values[3]	auto[0]	auto[0]	auto[1]	5639351	1			T22	25		T23	929		T29	128
all_values[3]	auto[0]	auto[1]	auto[0]	608220	1			T22	6		T23	168		T29	44
all_values[3]	auto[0]	auto[1]	auto[1]	5636188	1			T22	2		T23	1550		T29	153
all_values[3]	auto[1]	auto[0]	auto[1]	84261	1			T22	3		T30	4		T32	3
all_values[3]	auto[1]	auto[1]	auto[1]	82576	1			T22	1		T30	5		T32	1
all_values[4]	auto[0]	auto[0]	auto[0]	2584587	1			T22	44		T23	73		T24	403
all_values[4]	auto[0]	auto[0]	auto[1]	5647295	1			T22	13		T23	1393		T29	201
all_values[4]	auto[0]	auto[1]	auto[0]	609341	1			T22	3		T23	47		T29	25
all_values[4]	auto[0]	auto[1]	auto[1]	5623398	1			T22	12		T23	1210		T29	136
all_values[4]	auto[1]	auto[0]	auto[1]	84057	1			T22	4		T30	5		T32	4
all_values[4]	auto[1]	auto[1]	auto[1]	83048	1			T30	4		T32	1		T1	10
all_values[5]	auto[0]	auto[0]	auto[0]	2591679	1			T22	44		T23	64		T24	403
all_values[5]	auto[0]	auto[0]	auto[1]	5644473	1			T22	7		T23	1422		T29	94
all_values[5]	auto[0]	auto[1]	auto[0]	609245	1			T22	11		T23	45		T29	18
all_values[5]	auto[0]	auto[1]	auto[1]	5619367	1			T22	10		T23	1192		T29	250
all_values[5]	auto[1]	auto[0]	auto[1]	83703	1			T22	1		T30	5		T32	3
all_values[5]	auto[1]	auto[1]	auto[1]	83259	1			T22	3		T30	6		T32	1
all_values[6]	auto[0]	auto[0]	auto[0]	2577842	1			T22	39		T23	126		T24	403
all_values[6]	auto[0]	auto[0]	auto[1]	5652104	1			T22	11		T23	1222		T29	188
all_values[6]	auto[0]	auto[1]	auto[0]	608148	1			T22	23		T23	147		T29	17
all_values[6]	auto[0]	auto[1]	auto[1]	5626577	1			T23	1228		T29	176		T30	55
all_values[6]	auto[1]	auto[0]	auto[1]	83487	1			T22	3		T30	5		T32	3
all_values[6]	auto[1]	auto[1]	auto[1]	83568	1			T30	10		T32	5		T1	8
all_values[7]	auto[0]	auto[0]	auto[0]	2588923	1			T22	37		T23	72		T24	403
all_values[7]	auto[0]	auto[0]	auto[1]	5655276	1			T22	14		T23	1244		T29	135
all_values[7]	auto[0]	auto[1]	auto[0]	604759	1			T22	18		T23	68		T29	40
all_values[7]	auto[0]	auto[1]	auto[1]	5615459	1			T22	2		T23	1339		T29	215
all_values[7]	auto[1]	auto[0]	auto[1]	84039	1			T22	2		T30	11		T32	5
all_values[7]	auto[1]	auto[1]	auto[1]	83270	1			T22	3		T30	3		T32	1
all_values[8]	auto[0]	auto[0]	auto[0]	2593948	1			T22	34		T23	94		T24	403
all_values[8]	auto[0]	auto[0]	auto[1]	5668619	1			T22	5		T23	1282		T29	196
all_values[8]	auto[0]	auto[1]	auto[0]	604552	1			T22	34		T23	55		T29	35
all_values[8]	auto[0]	auto[1]	auto[1]	5597067	1			T22	1		T23	1292		T29	125
all_values[8]	auto[1]	auto[0]	auto[1]	83880	1			T30	9		T32	1		T1	12
all_values[8]	auto[1]	auto[1]	auto[1]	83660	1			T22	2		T30	3		T32	1
all_values[9]	auto[0]	auto[0]	auto[0]	2582836	1			T22	36		T23	93		T24	403
all_values[9]	auto[0]	auto[0]	auto[1]	5659643	1			T22	19		T23	1084		T29	188
all_values[9]	auto[0]	auto[1]	auto[0]	606271	1			T22	7		T23	118		T29	22
all_values[9]	auto[0]	auto[1]	auto[1]	5615860	1			T22	7		T23	1428		T29	157
all_values[9]	auto[1]	auto[0]	auto[1]	83928	1			T22	4		T30	6		T32	5
all_values[9]	auto[1]	auto[1]	auto[1]	83188	1			T22	3		T30	4		T32	1
all_values[10]	auto[0]	auto[0]	auto[0]	2585455	1			T22	37		T23	110		T24	403
all_values[10]	auto[0]	auto[0]	auto[1]	5635488	1			T22	8		T23	1127		T29	145
all_values[10]	auto[0]	auto[1]	auto[0]	612426	1			T22	21		T23	132		T29	52
all_values[10]	auto[0]	auto[1]	auto[1]	5630901	1			T22	8		T23	1354		T29	171
all_values[10]	auto[1]	auto[0]	auto[1]	83983	1			T30	7		T32	2		T1	12
all_values[10]	auto[1]	auto[1]	auto[1]	83473	1			T22	2		T30	5		T32	4
all_values[11]	auto[0]	auto[0]	auto[0]	2582046	1			T22	39		T23	145		T24	403
all_values[11]	auto[0]	auto[0]	auto[1]	5633543	1			T22	16		T23	1252		T29	122
all_values[11]	auto[0]	auto[1]	auto[0]	620087	1			T22	5		T23	82		T29	22
all_values[11]	auto[0]	auto[1]	auto[1]	5628959	1			T22	11		T23	1244		T29	203
all_values[11]	auto[1]	auto[0]	auto[1]	84030	1			T22	1		T30	6		T32	4
all_values[11]	auto[1]	auto[1]	auto[1]	83061	1			T22	4		T30	7		T32	3
all_values[12]	auto[0]	auto[0]	auto[0]	2589523	1			T22	38		T23	134		T24	403
all_values[12]	auto[0]	auto[0]	auto[1]	5691883	1			T22	16		T23	1217		T29	90
all_values[12]	auto[0]	auto[1]	auto[0]	605889	1			T22	8		T23	91		T29	28
all_values[12]	auto[0]	auto[1]	auto[1]	5577051	1			T22	9		T23	1281		T29	243
all_values[12]	auto[1]	auto[0]	auto[1]	84132	1			T22	2		T30	9		T32	2
all_values[12]	auto[1]	auto[1]	auto[1]	83248	1			T22	3		T30	9		T32	5
all_values[13]	auto[0]	auto[0]	auto[0]	2571605	1			T22	38		T23	52		T24	403
all_values[13]	auto[0]	auto[0]	auto[1]	5624704	1			T22	18		T23	904		T29	160
all_values[13]	auto[0]	auto[1]	auto[0]	611017	1			T22	14		T23	146		T29	19
all_values[13]	auto[0]	auto[1]	auto[1]	5657042	1			T22	2		T23	1621		T29	185
all_values[13]	auto[1]	auto[0]	auto[1]	83458	1			T22	4		T30	4		T32	4
all_values[13]	auto[1]	auto[1]	auto[1]	83900	1			T30	7		T32	2		T1	13
all_values[14]	auto[0]	auto[0]	auto[0]	2582774	1			T22	42		T23	131		T24	403
all_values[14]	auto[0]	auto[0]	auto[1]	5637594	1			T22	14		T23	1200		T29	216
all_values[14]	auto[0]	auto[1]	auto[0]	605410	1			T22	10		T23	214		T29	17
all_values[14]	auto[0]	auto[1]	auto[1]	5638572	1			T22	4		T23	1178		T29	154
all_values[14]	auto[1]	auto[0]	auto[1]	84040	1			T22	5		T30	7		T32	1
all_values[14]	auto[1]	auto[1]	auto[1]	83336	1			T22	1		T30	3		T32	3
all_values[15]	auto[0]	auto[0]	auto[0]	2585145	1			T22	44		T23	158		T24	403
all_values[15]	auto[0]	auto[0]	auto[1]	5628011	1			T22	11		T23	1428		T29	193
all_values[15]	auto[0]	auto[1]	auto[0]	604511	1			T22	14		T23	70		T29	49
all_values[15]	auto[0]	auto[1]	auto[1]	5646573	1			T22	3		T23	1067		T29	85
all_values[15]	auto[1]	auto[0]	auto[1]	83491	1			T22	2		T30	9		T32	4
all_values[15]	auto[1]	auto[1]	auto[1]	83995	1			T22	2		T30	3		T1	11
all_values[16]	auto[0]	auto[0]	auto[0]	2591563	1			T22	39		T23	110		T24	403
all_values[16]	auto[0]	auto[0]	auto[1]	5627117	1			T22	13		T23	1046		T29	110
all_values[16]	auto[0]	auto[1]	auto[0]	608489	1			T22	10		T23	121		T29	59
all_values[16]	auto[0]	auto[1]	auto[1]	5637641	1			T22	6		T23	1446		T29	182
all_values[16]	auto[1]	auto[0]	auto[1]	83689	1			T22	3		T30	7		T1	11
all_values[16]	auto[1]	auto[1]	auto[1]	83227	1			T22	5		T30	2		T32	3
all_values[17]	auto[0]	auto[0]	auto[0]	2589294	1			T22	33		T23	132		T24	403
all_values[17]	auto[0]	auto[0]	auto[1]	5626722	1			T22	15		T23	1018		T29	135
all_values[17]	auto[0]	auto[1]	auto[0]	608855	1			T22	15		T23	90		T29	18
all_values[17]	auto[0]	auto[1]	auto[1]	5639648	1			T22	9		T23	1483		T29	217
all_values[17]	auto[1]	auto[0]	auto[1]	83545	1			T22	1		T30	6		T32	4
all_values[17]	auto[1]	auto[1]	auto[1]	83662	1			T22	3		T30	6		T32	1
all_values[18]	auto[0]	auto[0]	auto[0]	2582340	1			T22	54		T23	96		T24	403
all_values[18]	auto[0]	auto[0]	auto[1]	5651660	1			T22	5		T23	1082		T29	172
all_values[18]	auto[0]	auto[1]	auto[0]	606669	1			T22	15		T23	131		T29	44
all_values[18]	auto[0]	auto[1]	auto[1]	5623856	1			T23	1414		T29	152		T30	27
all_values[18]	auto[1]	auto[0]	auto[1]	83357	1			T22	1		T30	4		T32	2
all_values[18]	auto[1]	auto[1]	auto[1]	83844	1			T22	1		T30	8		T32	3
all_values[19]	auto[0]	auto[0]	auto[0]	2598363	1			T22	32		T23	77		T24	403
all_values[19]	auto[0]	auto[0]	auto[1]	5612990	1			T22	16		T23	1353		T29	134
all_values[19]	auto[0]	auto[1]	auto[0]	617612	1			T22	12		T23	71		T29	33
all_values[19]	auto[0]	auto[1]	auto[1]	5635553	1			T22	10		T23	1222		T29	176
all_values[19]	auto[1]	auto[0]	auto[1]	83872	1			T22	4		T30	4		T32	4
all_values[19]	auto[1]	auto[1]	auto[1]	83336	1			T22	2		T30	6		T32	2
all_values[20]	auto[0]	auto[0]	auto[0]	2589819	1			T22	29		T23	106		T24	403
all_values[20]	auto[0]	auto[0]	auto[1]	5651978	1			T22	9		T23	1168		T29	206
all_values[20]	auto[0]	auto[1]	auto[0]	608085	1			T22	19		T23	48		T29	20
all_values[20]	auto[0]	auto[1]	auto[1]	5614941	1			T22	12		T23	1401		T29	130
all_values[20]	auto[1]	auto[0]	auto[1]	83827	1			T22	2		T30	8		T32	2
all_values[20]	auto[1]	auto[1]	auto[1]	83076	1			T22	5		T30	3		T32	4
all_values[21]	auto[0]	auto[0]	auto[0]	2596057	1			T22	32		T23	107		T24	403
all_values[21]	auto[0]	auto[0]	auto[1]	5651742	1			T22	13		T23	1401		T29	156
all_values[21]	auto[0]	auto[1]	auto[0]	613948	1			T22	23		T23	72		T29	38
all_values[21]	auto[0]	auto[1]	auto[1]	5602755	1			T22	4		T23	1143		T29	169
all_values[21]	auto[1]	auto[0]	auto[1]	84018	1			T30	10		T32	1		T1	13
all_values[21]	auto[1]	auto[1]	auto[1]	83206	1			T22	4		T30	6		T32	2
all_values[22]	auto[0]	auto[0]	auto[0]	2594602	1			T22	33		T23	91		T24	403
all_values[22]	auto[0]	auto[0]	auto[1]	5616092	1			T22	19		T23	1465		T29	203
all_values[22]	auto[0]	auto[1]	auto[0]	607348	1			T22	20		T23	56		T29	6
all_values[22]	auto[0]	auto[1]	auto[1]	5646272	1			T22	3		T23	1111		T29	152
all_values[22]	auto[1]	auto[0]	auto[1]	84210	1			T30	6		T32	4		T1	14
all_values[22]	auto[1]	auto[1]	auto[1]	83202	1			T22	1		T30	3		T1	10
all_values[23]	auto[0]	auto[0]	auto[0]	2584276	1			T22	51		T23	51		T24	403
all_values[23]	auto[0]	auto[0]	auto[1]	5659395	1			T22	3		T23	1449		T29	160
all_values[23]	auto[0]	auto[1]	auto[0]	609616	1			T22	10		T23	57		T29	22
all_values[23]	auto[0]	auto[1]	auto[1]	5611664	1			T22	9		T23	1166		T29	166
all_values[23]	auto[1]	auto[0]	auto[1]	83280	1			T22	2		T30	7		T32	5
all_values[23]	auto[1]	auto[1]	auto[1]	83495	1			T22	1		T30	2		T32	2
all_values[24]	auto[0]	auto[0]	auto[0]	2581425	1			T22	51		T23	77		T24	403
all_values[24]	auto[0]	auto[0]	auto[1]	5630478	1			T22	7		T23	1232		T29	147
all_values[24]	auto[0]	auto[1]	auto[0]	614198	1			T22	15		T23	78		T29	30
all_values[24]	auto[0]	auto[1]	auto[1]	5638686	1			T22	2		T23	1336		T29	212
all_values[24]	auto[1]	auto[0]	auto[1]	83076	1			T22	1		T30	10		T32	1
all_values[24]	auto[1]	auto[1]	auto[1]	83863	1			T30	4		T32	4		T1	7
all_values[25]	auto[0]	auto[0]	auto[0]	2585411	1			T22	39		T23	82		T24	403
all_values[25]	auto[0]	auto[0]	auto[1]	5633350	1			T22	17		T23	1243		T29	179
all_values[25]	auto[0]	auto[1]	auto[0]	609124	1			T22	12		T23	125		T29	44
all_values[25]	auto[0]	auto[1]	auto[1]	5637127	1			T22	3		T23	1273		T29	129
all_values[25]	auto[1]	auto[0]	auto[1]	83676	1			T22	4		T30	7		T32	2
all_values[25]	auto[1]	auto[1]	auto[1]	83038	1			T22	1		T30	4		T32	1
all_values[26]	auto[0]	auto[0]	auto[0]	2593726	1			T22	41		T23	170		T24	403
all_values[26]	auto[0]	auto[0]	auto[1]	5649081	1			T22	11		T23	1089		T29	190
all_values[26]	auto[0]	auto[1]	auto[0]	607593	1			T22	10		T23	208		T29	63
all_values[26]	auto[0]	auto[1]	auto[1]	5614630	1			T22	8		T23	1256		T29	125
all_values[26]	auto[1]	auto[0]	auto[1]	83214	1			T22	4		T30	8		T32	7
all_values[26]	auto[1]	auto[1]	auto[1]	83482	1			T22	2		T30	4		T1	5
all_values[27]	auto[0]	auto[0]	auto[0]	2594618	1			T22	33		T23	82		T24	403
all_values[27]	auto[0]	auto[0]	auto[1]	5632644	1			T22	11		T23	1332		T29	173
all_values[27]	auto[0]	auto[1]	auto[0]	612898	1			T22	20		T23	127		T29	41
all_values[27]	auto[0]	auto[1]	auto[1]	5624217	1			T22	8		T23	1182		T29	147
all_values[27]	auto[1]	auto[0]	auto[1]	84181	1			T22	2		T30	6		T32	2
all_values[27]	auto[1]	auto[1]	auto[1]	83168	1			T22	2		T30	8		T1	11
all_values[28]	auto[0]	auto[0]	auto[0]	2579909	1			T22	35		T23	160		T24	403
all_values[28]	auto[0]	auto[0]	auto[1]	5620629	1			T22	17		T23	974		T29	111
all_values[28]	auto[0]	auto[1]	auto[0]	604078	1			T22	17		T23	181		T29	40
all_values[28]	auto[0]	auto[1]	auto[1]	5660366	1			T22	2		T23	1408		T29	194
all_values[28]	auto[1]	auto[0]	auto[1]	83278	1			T22	3		T30	6		T32	6
all_values[28]	auto[1]	auto[1]	auto[1]	83466	1			T22	2		T30	6		T32	3
all_values[29]	auto[0]	auto[0]	auto[0]	2587458	1			T22	43		T23	116		T24	403
all_values[29]	auto[0]	auto[0]	auto[1]	5664278	1			T22	4		T23	1426		T29	154
all_values[29]	auto[0]	auto[1]	auto[0]	616621	1			T22	16		T23	113		T29	32
all_values[29]	auto[0]	auto[1]	auto[1]	5596153	1			T22	8		T23	1068		T29	173
all_values[29]	auto[1]	auto[0]	auto[1]	84390	1			T22	3		T30	7		T32	5
all_values[29]	auto[1]	auto[1]	auto[1]	82826	1			T22	2		T30	3		T32	3
all_values[30]	auto[0]	auto[0]	auto[0]	2581987	1			T22	47		T23	97		T24	403
all_values[30]	auto[0]	auto[0]	auto[1]	5660665	1			T22	11		T23	1280		T29	210
all_values[30]	auto[0]	auto[1]	auto[0]	606916	1			T22	10		T23	83		T29	19
all_values[30]	auto[0]	auto[1]	auto[1]	5615224	1			T22	4		T23	1263		T29	124
all_values[30]	auto[1]	auto[0]	auto[1]	84090	1			T22	4		T30	6		T32	3
all_values[30]	auto[1]	auto[1]	auto[1]	82844	1			T30	8		T32	3		T1	19
all_values[31]	auto[0]	auto[0]	auto[0]	2583358	1			T22	38		T23	169		T24	403
all_values[31]	auto[0]	auto[0]	auto[1]	5646927	1			T22	23		T23	1432		T29	117
all_values[31]	auto[0]	auto[1]	auto[0]	601314	1			T22	7		T23	66		T29	36
all_values[31]	auto[0]	auto[1]	auto[1]	5632662	1			T22	3		T23	1056		T29	208
all_values[31]	auto[1]	auto[0]	auto[1]	84493	1			T22	4		T30	13		T32	5
all_values[31]	auto[1]	auto[1]	auto[1]	82972	1			T22	1		T30	4		T32	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal