Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[1]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[2]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[3]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[4]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[5]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[6]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[7]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[8]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[9]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[10]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[11]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[12]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[13]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[14]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[15]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[16]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[17]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[18]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[19]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[20]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[21]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[22]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[23]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[24]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[25]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[26]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[27]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[28]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[29]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[30]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[31]	14447776	1			T22	98		T23	2084		T24	755

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281416952

1

T22

1780

T23

33356

T24

17883

auto[1]

180911880

1

T22

1356

T23

33332

T24

6277

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

367978562

1

T22

3002

T23

66688

T24

12896

auto[1]

94350270

1

T22

134

T24

11264

T25

1652

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

340394146

1

T22

2193

T23

66688

T24

13177

auto[1]

121934686

1

T22

943

T24

10983

T25

1711

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5367301	1			T22	43		T23	1038		T24	208
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3778313	1			T22	10		T23	1046		T24	24
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1480012	1			T24	180		T25	24		T27	40
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1946463	1			T22	43		T24	167		T25	40
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	398921	1			T22	2		T27	19		T30	25
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1476766	1			T24	176		T25	8		T27	34
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5359987	1			T22	34		T23	1039		T24	193
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3788902	1			T22	27		T23	1045		T24	25
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1479334	1			T22	3		T24	162		T25	24
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1946120	1			T22	24		T24	197		T25	27
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	400287	1			T22	3		T27	13		T30	9
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1473146	1			T22	7		T24	178		T25	32
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5369558	1			T22	26		T23	1034		T24	183
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3785828	1			T22	24		T23	1050		T24	29
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1483085	1			T24	196		T25	21		T27	36
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1937736	1			T22	36		T24	187		T25	32
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	403151	1			T22	12		T27	6		T30	15
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1468418	1			T24	160		T25	32		T27	61
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5363599	1			T22	58		T23	1057		T24	239
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3789141	1			T22	28		T23	1027		T24	29
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1483034	1			T24	171		T25	32		T27	62
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1945183	1			T22	10		T24	162		T25	20
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	401151	1			T22	2		T27	15		T30	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1465668	1			T24	154		T25	24		T27	57
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5372566	1			T22	24		T23	1078		T24	236
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3793364	1			T22	52		T23	1006		T24	29
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1484387	1			T24	182		T25	17		T27	50
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1937621	1			T22	6		T24	138		T25	24
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	398010	1			T22	12		T27	5		T30	21
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1461828	1			T22	4		T24	170		T25	28
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5368260	1			T22	39		T23	1008		T24	191
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3788254	1			T22	33		T23	1076		T24	23
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1480501	1			T24	161		T25	12		T27	97
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1944351	1			T22	2		T24	180		T25	31
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	401484	1			T22	13		T27	4		T30	9
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1464926	1			T22	11		T24	200		T25	28
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5377341	1			T22	44		T23	1064		T24	203
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3779754	1			T22	12		T23	1020		T24	29
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1483525	1			T24	155		T25	35		T27	41
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1939948	1			T22	30		T24	206		T25	22
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	401548	1			T22	6		T27	9		T30	11
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1465660	1			T22	6		T24	162		T25	26
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5370312	1			T22	21		T23	1043		T24	181
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3781531	1			T22	27		T23	1041		T24	29
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1485157	1			T24	198		T25	23		T27	42
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1936271	1			T22	23		T24	152		T25	34
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	403070	1			T22	14		T27	16		T32	10
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1471435	1			T22	13		T24	195		T25	34
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5363819	1			T22	55		T23	1066		T24	210
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3795168	1			T22	8		T23	1018		T24	22
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1488914	1			T22	3		T24	195		T25	22
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1934444	1			T22	32		T24	146		T25	24
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	396059	1			T27	10		T30	18		T32	13
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1469372	1			T24	182		T25	31		T27	22
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5368988	1			T22	26		T23	1030		T24	192
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3783368	1			T22	59		T23	1054		T24	22
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1483780	1			T24	205		T25	19		T27	25
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1939891	1			T22	2		T24	156		T25	26
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	401700	1			T22	9		T27	15		T30	23
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1470049	1			T22	2		T24	180		T25	18
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5369926	1			T22	58		T23	1028		T24	168
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3786074	1			T22	8		T23	1056		T24	27
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1486991	1			T24	224		T25	36		T27	57
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1937238	1			T22	14		T24	156		T25	20
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	398468	1			T22	3		T27	14		T30	9
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1469079	1			T22	15		T24	180		T25	36
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5378825	1			T22	27		T23	1022		T24	193
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3775975	1			T22	29		T23	1062		T24	17
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1481919	1			T24	177		T25	16		T27	70
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1934381	1			T22	18		T24	176		T25	32
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	401295	1			T22	19		T27	3		T30	16
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1475381	1			T22	5		T24	192		T25	20
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5366405	1			T22	54		T23	975		T24	248
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3785189	1			T22	10		T23	1109		T24	22
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1483285	1			T22	3		T24	193		T25	35
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1940139	1			T22	18		T24	140		T25	30
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	401493	1			T22	8		T27	10		T30	10
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1471265	1			T22	5		T24	152		T25	26
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5360529	1			T22	48		T23	1001		T24	229
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3790344	1			T22	43		T23	1083		T24	25
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1483459	1			T24	169		T25	30		T27	30
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1938611	1			T24	184		T25	20		T27	139
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	399788	1			T22	7		T27	16		T30	3
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1475045	1			T24	148		T25	31		T27	55
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5371252	1			T22	15		T23	1036		T24	191
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3781173	1			T22	27		T23	1048		T24	25
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1482798	1			T24	176		T25	26		T27	44
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1939881	1			T22	26		T24	194		T25	26
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	402420	1			T22	24		T27	7		T30	22
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1470252	1			T22	6		T24	169		T25	34
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5362518	1			T22	40		T23	1047		T24	196
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3786333	1			T22	49		T23	1037		T24	28
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1486314	1			T24	180		T25	41		T27	62
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1939651	1			T24	198		T25	20		T27	81
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	401419	1			T22	7		T27	17		T30	17
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1471541	1			T22	2		T24	153		T25	28
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5379230	1			T22	49		T23	1017		T24	197
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3786602	1			T22	3		T23	1067		T24	27
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1478410	1			T24	187		T25	17		T27	55
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1940266	1			T22	28		T24	182		T25	32
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	399509	1			T22	16		T27	10		T30	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1463759	1			T22	2		T24	162		T25	28
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5381784	1			T22	39		T23	1014		T24	235
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3780660	1			T22	17		T23	1070		T24	22
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1473943	1			T22	1		T24	230		T25	12
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1941887	1			T22	21		T24	122		T25	27
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	401960	1			T22	13		T27	3		T30	8
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1467542	1			T22	7		T24	146		T25	56
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5365767	1			T22	44		T23	1039		T24	201
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3797154	1			T22	29		T23	1045		T24	19
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1474887	1			T22	1		T24	195		T25	16
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1944536	1			T22	18		T24	190		T25	32
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	401383	1			T22	4		T27	3		T30	20
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1464049	1			T22	2		T24	150		T25	28
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5380465	1			T22	43		T23	1090		T24	216
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3780512	1			T22	28		T23	994		T24	26
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1478389	1			T22	2		T24	181		T25	42
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1943173	1			T22	20		T24	156		T25	24
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	401079	1			T22	3		T27	14		T30	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1464158	1			T22	2		T24	176		T25	19
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5388368	1			T22	45		T23	1062		T24	199
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3773980	1			T22	6		T23	1022		T24	23
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1478703	1			T22	1		T24	150		T25	42
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1941778	1			T22	28		T24	201		T25	18
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	403129	1			T22	17		T27	14		T30	11
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1461818	1			T22	1		T24	182		T25	18
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5376920	1			T22	23		T23	1066		T24	236
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3781665	1			T22	64		T23	1018		T24	22
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1476502	1			T24	174		T25	12		T27	38
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1945890	1			T22	8		T24	137		T25	40
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	400149	1			T22	3		T27	13		T30	2
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1466650	1			T24	186		T25	24		T27	40
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5384527	1			T22	47		T23	1055		T24	181
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3775593	1			T22	25		T23	1029		T24	26
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1474264	1			T24	184		T25	26		T27	38
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1945277	1			T22	11		T24	196		T25	33
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	401244	1			T22	13		T27	25		T30	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1466871	1			T22	2		T24	168		T25	14
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5391861	1			T22	44		T23	1033		T24	206
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3774547	1			T22	42		T23	1051		T24	26
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1477708	1			T24	167		T25	40		T27	29
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1937562	1			T24	182		T25	19		T27	127
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	400900	1			T22	11		T27	9		T30	6
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1465198	1			T22	1		T24	174		T25	16
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5377762	1			T22	22		T23	1037		T24	196
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3784754	1			T22	53		T23	1047		T24	24
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1478848	1			T24	195		T25	20		T27	72
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1938226	1			T22	15		T24	134		T25	26
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	401943	1			T22	5		T27	18		T30	18
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1466243	1			T22	3		T24	206		T25	37
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5370427	1			T22	18		T23	1031		T24	193
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3790898	1			T22	66		T23	1053		T24	23
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1476804	1			T24	187		T25	18		T27	34
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1943496	1			T22	1		T24	174		T25	40
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	402155	1			T22	11		T27	15		T30	17
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1463996	1			T22	2		T24	178		T25	23
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5371619	1			T22	49		T23	1060		T24	228
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3781297	1			T22	36		T23	1024		T24	32
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1480174	1			T22	1		T24	156		T25	19
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1944909	1			T22	8		T24	191		T25	34
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	400876	1			T22	4		T27	6		T30	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1468901	1			T24	148		T25	26		T27	52
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5368231	1			T22	55		T23	1026		T24	200
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3787858	1			T22	34		T23	1058		T24	25
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1480154	1			T24	154		T25	14		T27	46
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1943504	1			T22	3		T24	206		T25	25
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	400850	1			T22	3		T27	5		T30	11
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1467179	1			T22	3		T24	170		T25	14
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5370268	1			T22	34		T23	1065		T24	209
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3786202	1			T22	24		T23	1019		T24	27
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1479531	1			T24	179		T25	20		T27	33
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1944314	1			T22	20		T24	190		T25	27
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	401490	1			T22	15		T27	11		T30	9
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1465971	1			T22	5		T24	150		T25	16
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5370697	1			T22	49		T23	1052		T24	185
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3782241	1			T22	18		T23	1032		T24	30
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1478127	1			T24	212		T25	33		T27	68
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1948073	1			T22	17		T24	160		T25	16
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	401880	1			T22	10		T27	1		T30	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1466758	1			T22	4		T24	168		T25	28
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5372178	1			T22	41		T23	1074		T24	226
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3791115	1			T22	17		T23	1010		T24	20
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1478730	1			T24	157		T25	36		T27	43
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1945663	1			T22	34		T24	164		T25	23
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	400493	1			T22	5		T27	10		T30	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1459597	1			T22	1		T24	188		T25	28
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5360865	1			T22	25		T23	1069		T24	217
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3788142	1			T22	31		T23	1015		T24	25
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1478391	1			T24	157		T25	27		T27	29
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1948254	1			T22	10		T24	184		T25	22
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	400435	1			T22	24		T27	11		T30	17
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1471689	1			T22	8		T24	172		T25	34

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal