Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[1]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[2]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[3]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[4]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[5]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[6]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[7]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[8]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[9]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[10]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[11]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[12]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[13]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[14]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[15]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[16]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[17]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[18]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[19]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[20]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[21]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[22]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[23]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[24]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[25]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[26]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[27]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[28]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[29]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[30]	14447776	1			T22	98		T23	2084		T24	755
bins_for_gpio_bits[31]	14447776	1			T22	98		T23	2084		T24	755

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281416952

1

T22

1780

T23

33356

T24

17883

auto[1]

180911880

1

T22

1356

T23

33332

T24

6277

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281406742

1

T22

1774

T23

33356

T24

17880

auto[1]

180922090

1

T22

1362

T23

33332

T24

6280

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8530205	1			T22	86		T23	1038		T24	510
bins_for_gpio_bits[0]	auto[0]	auto[1]	263236	1			T24	45		T25	4		T27	6
bins_for_gpio_bits[0]	auto[1]	auto[0]	263571	1			T24	45		T25	4		T27	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	5390764	1			T22	12		T23	1046		T24	155
bins_for_gpio_bits[1]	auto[0]	auto[0]	8522142	1			T22	60		T23	1039		T24	508
bins_for_gpio_bits[1]	auto[0]	auto[1]	262973	1			T24	44		T25	10		T27	14
bins_for_gpio_bits[1]	auto[1]	auto[0]	263299	1			T22	1		T24	44		T25	10
bins_for_gpio_bits[1]	auto[1]	auto[1]	5399362	1			T22	37		T23	1045		T24	159
bins_for_gpio_bits[2]	auto[0]	auto[0]	8527370	1			T22	62		T23	1034		T24	520
bins_for_gpio_bits[2]	auto[0]	auto[1]	262736	1			T24	46		T25	7		T27	7
bins_for_gpio_bits[2]	auto[1]	auto[0]	263009	1			T24	46		T25	7		T27	7
bins_for_gpio_bits[2]	auto[1]	auto[1]	5394661	1			T22	36		T23	1050		T24	143
bins_for_gpio_bits[3]	auto[0]	auto[0]	8528581	1			T22	68		T23	1057		T24	529
bins_for_gpio_bits[3]	auto[0]	auto[1]	262959	1			T24	43		T25	7		T27	7
bins_for_gpio_bits[3]	auto[1]	auto[0]	263235	1			T24	43		T25	7		T27	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	5393001	1			T22	30		T23	1027		T24	140
bins_for_gpio_bits[4]	auto[0]	auto[0]	8532683	1			T22	30		T23	1078		T24	516
bins_for_gpio_bits[4]	auto[0]	auto[1]	261579	1			T24	40		T25	6		T27	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	261891	1			T24	40		T25	6		T27	11
bins_for_gpio_bits[4]	auto[1]	auto[1]	5391623	1			T22	68		T23	1006		T24	159
bins_for_gpio_bits[5]	auto[0]	auto[0]	8530706	1			T22	41		T23	1008		T24	485
bins_for_gpio_bits[5]	auto[0]	auto[1]	262067	1			T24	47		T25	6		T27	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	262406	1			T24	47		T25	6		T27	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	5392597	1			T22	57		T23	1076		T24	176
bins_for_gpio_bits[6]	auto[0]	auto[0]	8538127	1			T22	74		T23	1064		T24	522
bins_for_gpio_bits[6]	auto[0]	auto[1]	262346	1			T24	42		T25	10		T27	8
bins_for_gpio_bits[6]	auto[1]	auto[0]	262687	1			T24	42		T25	10		T27	8
bins_for_gpio_bits[6]	auto[1]	auto[1]	5384616	1			T22	24		T23	1020		T24	149
bins_for_gpio_bits[7]	auto[0]	auto[0]	8528359	1			T22	44		T23	1043		T24	479
bins_for_gpio_bits[7]	auto[0]	auto[1]	263048	1			T22	1		T24	51		T25	9
bins_for_gpio_bits[7]	auto[1]	auto[0]	263381	1			T24	52		T25	9		T27	11
bins_for_gpio_bits[7]	auto[1]	auto[1]	5392988	1			T22	53		T23	1041		T24	173
bins_for_gpio_bits[8]	auto[0]	auto[0]	8523813	1			T22	90		T23	1066		T24	505
bins_for_gpio_bits[8]	auto[0]	auto[1]	263016	1			T24	46		T25	7		T27	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	263364	1			T24	46		T25	8		T27	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	5397583	1			T22	8		T23	1018		T24	158
bins_for_gpio_bits[9]	auto[0]	auto[0]	8529536	1			T22	28		T23	1030		T24	503
bins_for_gpio_bits[9]	auto[0]	auto[1]	262781	1			T24	50		T25	6		T27	7
bins_for_gpio_bits[9]	auto[1]	auto[0]	263123	1			T24	50		T25	6		T27	8
bins_for_gpio_bits[9]	auto[1]	auto[1]	5392336	1			T22	70		T23	1054		T24	152
bins_for_gpio_bits[10]	auto[0]	auto[0]	8530883	1			T22	72		T23	1028		T24	505
bins_for_gpio_bits[10]	auto[0]	auto[1]	262980	1			T24	43		T25	7		T27	6
bins_for_gpio_bits[10]	auto[1]	auto[0]	263272	1			T24	43		T25	7		T27	6
bins_for_gpio_bits[10]	auto[1]	auto[1]	5390641	1			T22	26		T23	1056		T24	164
bins_for_gpio_bits[11]	auto[0]	auto[0]	8532036	1			T22	45		T23	1022		T24	498
bins_for_gpio_bits[11]	auto[0]	auto[1]	262774	1			T24	48		T25	6		T27	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	263089	1			T24	48		T25	6		T27	8
bins_for_gpio_bits[11]	auto[1]	auto[1]	5389877	1			T22	53		T23	1062		T24	161
bins_for_gpio_bits[12]	auto[0]	auto[0]	8526164	1			T22	75		T23	975		T24	541
bins_for_gpio_bits[12]	auto[0]	auto[1]	263314	1			T24	40		T25	7		T27	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	263665	1			T24	40		T25	7		T27	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	5394633	1			T22	23		T23	1109		T24	134
bins_for_gpio_bits[13]	auto[0]	auto[0]	8519129	1			T22	48		T23	1001		T24	537
bins_for_gpio_bits[13]	auto[0]	auto[1]	263134	1			T24	45		T25	8		T27	8
bins_for_gpio_bits[13]	auto[1]	auto[0]	263470	1			T24	45		T25	9		T27	8
bins_for_gpio_bits[13]	auto[1]	auto[1]	5402043	1			T22	50		T23	1083		T24	128
bins_for_gpio_bits[14]	auto[0]	auto[0]	8530545	1			T22	41		T23	1036		T24	515
bins_for_gpio_bits[14]	auto[0]	auto[1]	263059	1			T24	45		T25	8		T27	9
bins_for_gpio_bits[14]	auto[1]	auto[0]	263386	1			T24	46		T25	8		T27	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	5390786	1			T22	57		T23	1048		T24	149
bins_for_gpio_bits[15]	auto[0]	auto[0]	8525112	1			T22	40		T23	1047		T24	530
bins_for_gpio_bits[15]	auto[0]	auto[1]	263086	1			T24	43		T25	7		T27	11
bins_for_gpio_bits[15]	auto[1]	auto[0]	263371	1			T24	44		T25	7		T27	11
bins_for_gpio_bits[15]	auto[1]	auto[1]	5396207	1			T22	58		T23	1037		T24	138
bins_for_gpio_bits[16]	auto[0]	auto[0]	8535323	1			T22	77		T23	1017		T24	528
bins_for_gpio_bits[16]	auto[0]	auto[1]	262286	1			T24	38		T25	7		T27	9
bins_for_gpio_bits[16]	auto[1]	auto[0]	262583	1			T24	38		T25	7		T27	9
bins_for_gpio_bits[16]	auto[1]	auto[1]	5387584	1			T22	21		T23	1067		T24	151
bins_for_gpio_bits[17]	auto[0]	auto[0]	8533638	1			T22	61		T23	1014		T24	552
bins_for_gpio_bits[17]	auto[0]	auto[1]	263654	1			T24	35		T25	7		T27	8
bins_for_gpio_bits[17]	auto[1]	auto[0]	263976	1			T24	35		T25	7		T27	8
bins_for_gpio_bits[17]	auto[1]	auto[1]	5386508	1			T22	37		T23	1070		T24	133
bins_for_gpio_bits[18]	auto[0]	auto[0]	8521464	1			T22	62		T23	1039		T24	545
bins_for_gpio_bits[18]	auto[0]	auto[1]	263451	1			T24	41		T25	7		T27	9
bins_for_gpio_bits[18]	auto[1]	auto[0]	263726	1			T22	1		T24	41		T25	7
bins_for_gpio_bits[18]	auto[1]	auto[1]	5399135	1			T22	35		T23	1045		T24	128
bins_for_gpio_bits[19]	auto[0]	auto[0]	8539325	1			T22	65		T23	1090		T24	512
bins_for_gpio_bits[19]	auto[0]	auto[1]	262396	1			T24	41		T25	6		T27	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	262702	1			T24	41		T25	7		T27	6
bins_for_gpio_bits[19]	auto[1]	auto[1]	5383353	1			T22	33		T23	994		T24	161
bins_for_gpio_bits[20]	auto[0]	auto[0]	8546154	1			T22	73		T23	1062		T24	506
bins_for_gpio_bits[20]	auto[0]	auto[1]	262425	1			T24	44		T25	7		T27	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	262695	1			T22	1		T24	44		T25	7
bins_for_gpio_bits[20]	auto[1]	auto[1]	5376502	1			T22	24		T23	1022		T24	161
bins_for_gpio_bits[21]	auto[0]	auto[0]	8536108	1			T22	31		T23	1066		T24	508
bins_for_gpio_bits[21]	auto[0]	auto[1]	262864	1			T24	39		T25	7		T27	7
bins_for_gpio_bits[21]	auto[1]	auto[0]	263204	1			T24	39		T25	7		T27	7
bins_for_gpio_bits[21]	auto[1]	auto[1]	5385600	1			T22	67		T23	1018		T24	169
bins_for_gpio_bits[22]	auto[0]	auto[0]	8540757	1			T22	57		T23	1055		T24	515
bins_for_gpio_bits[22]	auto[0]	auto[1]	262966	1			T24	46		T25	4		T27	7
bins_for_gpio_bits[22]	auto[1]	auto[0]	263311	1			T22	1		T24	46		T25	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	5380742	1			T22	40		T23	1029		T24	148
bins_for_gpio_bits[23]	auto[0]	auto[0]	8544209	1			T22	44		T23	1033		T24	512
bins_for_gpio_bits[23]	auto[0]	auto[1]	262610	1			T24	43		T25	6		T27	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	262922	1			T24	43		T25	6		T27	8
bins_for_gpio_bits[23]	auto[1]	auto[1]	5378035	1			T22	54		T23	1051		T24	157
bins_for_gpio_bits[24]	auto[0]	auto[0]	8531618	1			T22	36		T23	1037		T24	484
bins_for_gpio_bits[24]	auto[0]	auto[1]	262874	1			T24	41		T25	7		T27	8
bins_for_gpio_bits[24]	auto[1]	auto[0]	263218	1			T22	1		T24	41		T25	8
bins_for_gpio_bits[24]	auto[1]	auto[1]	5390066	1			T22	61		T23	1047		T24	189
bins_for_gpio_bits[25]	auto[0]	auto[0]	8528125	1			T22	19		T23	1031		T24	513
bins_for_gpio_bits[25]	auto[0]	auto[1]	262272	1			T24	41		T25	4		T27	10
bins_for_gpio_bits[25]	auto[1]	auto[0]	262602	1			T24	41		T25	5		T27	10
bins_for_gpio_bits[25]	auto[1]	auto[1]	5394777	1			T22	79		T23	1053		T24	160
bins_for_gpio_bits[26]	auto[0]	auto[0]	8532342	1			T22	58		T23	1060		T24	537
bins_for_gpio_bits[26]	auto[0]	auto[1]	264036	1			T24	38		T25	8		T27	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	264360	1			T24	38		T25	8		T27	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	5387038	1			T22	40		T23	1024		T24	142
bins_for_gpio_bits[27]	auto[0]	auto[0]	8528185	1			T22	57		T23	1026		T24	516
bins_for_gpio_bits[27]	auto[0]	auto[1]	263383	1			T24	44		T25	4		T27	9
bins_for_gpio_bits[27]	auto[1]	auto[0]	263704	1			T22	1		T24	44		T25	4
bins_for_gpio_bits[27]	auto[1]	auto[1]	5392504	1			T22	40		T23	1058		T24	151
bins_for_gpio_bits[28]	auto[0]	auto[0]	8530349	1			T22	54		T23	1065		T24	533
bins_for_gpio_bits[28]	auto[0]	auto[1]	263456	1			T24	45		T25	5		T27	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	263764	1			T24	45		T25	5		T27	8
bins_for_gpio_bits[28]	auto[1]	auto[1]	5390207	1			T22	44		T23	1019		T24	132
bins_for_gpio_bits[29]	auto[0]	auto[0]	8532961	1			T22	66		T23	1052		T24	515
bins_for_gpio_bits[29]	auto[0]	auto[1]	263595	1			T24	42		T25	5		T27	6
bins_for_gpio_bits[29]	auto[1]	auto[0]	263936	1			T24	42		T25	5		T27	7
bins_for_gpio_bits[29]	auto[1]	auto[1]	5387284	1			T22	32		T23	1032		T24	156
bins_for_gpio_bits[30]	auto[0]	auto[0]	8533354	1			T22	74		T23	1074		T24	508
bins_for_gpio_bits[30]	auto[0]	auto[1]	262894	1			T24	39		T25	7		T27	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	263217	1			T22	1		T24	39		T25	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	5388311	1			T22	23		T23	1010		T24	169
bins_for_gpio_bits[31]	auto[0]	auto[0]	8523323	1			T22	35		T23	1069		T24	520
bins_for_gpio_bits[31]	auto[0]	auto[1]	263866	1			T24	38		T25	6		T27	5
bins_for_gpio_bits[31]	auto[1]	auto[0]	264187	1			T24	38		T25	6		T27	5
bins_for_gpio_bits[31]	auto[1]	auto[1]	5396400	1			T22	63		T23	1015		T24	159