Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8323130 |
1 |
|
|
T22 |
41 |
|
T23 |
1469 |
|
T24 |
403 |
| auto[1] |
6308596 |
1 |
|
|
T22 |
35 |
|
T23 |
1254 |
|
T29 |
188 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13821686 |
1 |
|
|
T22 |
76 |
|
T23 |
2482 |
|
T24 |
403 |
| auto[1] |
810040 |
1 |
|
|
T23 |
241 |
|
T29 |
4 |
|
T30 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8274123 |
1 |
|
|
T22 |
54 |
|
T23 |
1406 |
|
T24 |
403 |
| auto[1] |
6357603 |
1 |
|
|
T22 |
22 |
|
T23 |
1317 |
|
T29 |
155 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2780260 |
1 |
|
|
T22 |
12 |
|
T23 |
547 |
|
T29 |
58 |
| auto[1] |
auto[0] |
auto[1] |
406110 |
1 |
|
|
T23 |
121 |
|
T29 |
1 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2767303 |
1 |
|
|
T22 |
10 |
|
T23 |
529 |
|
T29 |
93 |
| auto[1] |
auto[1] |
auto[1] |
403930 |
1 |
|
|
T23 |
120 |
|
T29 |
3 |
|
T30 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8341686 |
1 |
|
|
T22 |
53 |
|
T23 |
1260 |
|
T24 |
403 |
| auto[1] |
6290040 |
1 |
|
|
T22 |
23 |
|
T23 |
1463 |
|
T29 |
184 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13832832 |
1 |
|
|
T22 |
76 |
|
T23 |
2484 |
|
T24 |
403 |
| auto[1] |
798894 |
1 |
|
|
T23 |
239 |
|
T29 |
12 |
|
T32 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8347562 |
1 |
|
|
T22 |
52 |
|
T23 |
1457 |
|
T24 |
403 |
| auto[1] |
6284164 |
1 |
|
|
T22 |
24 |
|
T23 |
1266 |
|
T29 |
192 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2763844 |
1 |
|
|
T22 |
21 |
|
T23 |
421 |
|
T29 |
91 |
| auto[1] |
auto[0] |
auto[1] |
403044 |
1 |
|
|
T23 |
86 |
|
T29 |
6 |
|
T32 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2721426 |
1 |
|
|
T22 |
3 |
|
T23 |
606 |
|
T29 |
89 |
| auto[1] |
auto[1] |
auto[1] |
395850 |
1 |
|
|
T23 |
153 |
|
T29 |
6 |
|
T1 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8304926 |
1 |
|
|
T22 |
45 |
|
T23 |
1237 |
|
T24 |
403 |
| auto[1] |
6326800 |
1 |
|
|
T22 |
31 |
|
T23 |
1486 |
|
T29 |
223 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13826978 |
1 |
|
|
T22 |
75 |
|
T23 |
2410 |
|
T24 |
403 |
| auto[1] |
804748 |
1 |
|
|
T22 |
1 |
|
T23 |
313 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8314098 |
1 |
|
|
T22 |
66 |
|
T23 |
1086 |
|
T24 |
403 |
| auto[1] |
6317628 |
1 |
|
|
T22 |
10 |
|
T23 |
1637 |
|
T29 |
147 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2768424 |
1 |
|
|
T22 |
6 |
|
T23 |
665 |
|
T29 |
70 |
| auto[1] |
auto[0] |
auto[1] |
403955 |
1 |
|
|
T22 |
1 |
|
T23 |
156 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2744456 |
1 |
|
|
T22 |
3 |
|
T23 |
659 |
|
T29 |
71 |
| auto[1] |
auto[1] |
auto[1] |
400793 |
1 |
|
|
T23 |
157 |
|
T29 |
4 |
|
T30 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8299619 |
1 |
|
|
T22 |
56 |
|
T23 |
1397 |
|
T24 |
403 |
| auto[1] |
6332107 |
1 |
|
|
T22 |
20 |
|
T23 |
1326 |
|
T29 |
225 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13823378 |
1 |
|
|
T22 |
76 |
|
T23 |
2438 |
|
T24 |
403 |
| auto[1] |
808348 |
1 |
|
|
T23 |
285 |
|
T29 |
8 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8289737 |
1 |
|
|
T22 |
57 |
|
T23 |
1213 |
|
T24 |
403 |
| auto[1] |
6341989 |
1 |
|
|
T22 |
19 |
|
T23 |
1510 |
|
T29 |
196 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2762383 |
1 |
|
|
T22 |
11 |
|
T23 |
615 |
|
T29 |
85 |
| auto[1] |
auto[0] |
auto[1] |
402363 |
1 |
|
|
T23 |
144 |
|
T29 |
3 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2771258 |
1 |
|
|
T22 |
8 |
|
T23 |
610 |
|
T29 |
103 |
| auto[1] |
auto[1] |
auto[1] |
405985 |
1 |
|
|
T23 |
141 |
|
T29 |
5 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8365538 |
1 |
|
|
T22 |
56 |
|
T23 |
1351 |
|
T24 |
403 |
| auto[1] |
6266188 |
1 |
|
|
T22 |
20 |
|
T23 |
1372 |
|
T29 |
271 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13826698 |
1 |
|
|
T22 |
76 |
|
T23 |
2379 |
|
T24 |
403 |
| auto[1] |
805028 |
1 |
|
|
T23 |
344 |
|
T29 |
8 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8312537 |
1 |
|
|
T22 |
65 |
|
T23 |
965 |
|
T24 |
403 |
| auto[1] |
6319189 |
1 |
|
|
T22 |
11 |
|
T23 |
1758 |
|
T29 |
233 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2787761 |
1 |
|
|
T22 |
7 |
|
T23 |
622 |
|
T29 |
70 |
| auto[1] |
auto[0] |
auto[1] |
407509 |
1 |
|
|
T23 |
158 |
|
T29 |
1 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2726400 |
1 |
|
|
T22 |
4 |
|
T23 |
792 |
|
T29 |
155 |
| auto[1] |
auto[1] |
auto[1] |
397519 |
1 |
|
|
T23 |
186 |
|
T29 |
7 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8279767 |
1 |
|
|
T22 |
60 |
|
T23 |
956 |
|
T24 |
403 |
| auto[1] |
6351959 |
1 |
|
|
T22 |
16 |
|
T23 |
1767 |
|
T29 |
204 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13825095 |
1 |
|
|
T22 |
75 |
|
T23 |
2476 |
|
T24 |
403 |
| auto[1] |
806631 |
1 |
|
|
T22 |
1 |
|
T23 |
247 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8305076 |
1 |
|
|
T22 |
54 |
|
T23 |
1441 |
|
T24 |
403 |
| auto[1] |
6326650 |
1 |
|
|
T22 |
22 |
|
T23 |
1282 |
|
T29 |
156 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2749469 |
1 |
|
|
T22 |
16 |
|
T23 |
421 |
|
T29 |
77 |
| auto[1] |
auto[0] |
auto[1] |
401612 |
1 |
|
|
T22 |
1 |
|
T23 |
96 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2770550 |
1 |
|
|
T22 |
5 |
|
T23 |
614 |
|
T29 |
73 |
| auto[1] |
auto[1] |
auto[1] |
405019 |
1 |
|
|
T23 |
151 |
|
T29 |
2 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8304408 |
1 |
|
|
T22 |
61 |
|
T23 |
1331 |
|
T24 |
403 |
| auto[1] |
6327318 |
1 |
|
|
T22 |
15 |
|
T23 |
1392 |
|
T29 |
171 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13825064 |
1 |
|
|
T22 |
76 |
|
T23 |
2490 |
|
T24 |
403 |
| auto[1] |
806662 |
1 |
|
|
T23 |
233 |
|
T29 |
4 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8303184 |
1 |
|
|
T22 |
56 |
|
T23 |
1455 |
|
T24 |
403 |
| auto[1] |
6328542 |
1 |
|
|
T22 |
20 |
|
T23 |
1268 |
|
T29 |
172 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2768289 |
1 |
|
|
T22 |
20 |
|
T23 |
508 |
|
T29 |
110 |
| auto[1] |
auto[0] |
auto[1] |
404535 |
1 |
|
|
T23 |
119 |
|
T29 |
4 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2753591 |
1 |
|
|
T23 |
527 |
|
T29 |
58 |
|
T30 |
10 |
| auto[1] |
auto[1] |
auto[1] |
402127 |
1 |
|
|
T23 |
114 |
|
T1 |
6 |
|
T2 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8296647 |
1 |
|
|
T22 |
57 |
|
T23 |
1586 |
|
T24 |
403 |
| auto[1] |
6335079 |
1 |
|
|
T22 |
19 |
|
T23 |
1137 |
|
T29 |
134 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13827055 |
1 |
|
|
T22 |
76 |
|
T23 |
2483 |
|
T24 |
403 |
| auto[1] |
804671 |
1 |
|
|
T23 |
240 |
|
T29 |
9 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8329505 |
1 |
|
|
T22 |
61 |
|
T23 |
1379 |
|
T24 |
403 |
| auto[1] |
6302221 |
1 |
|
|
T22 |
15 |
|
T23 |
1344 |
|
T29 |
194 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2740323 |
1 |
|
|
T22 |
15 |
|
T23 |
665 |
|
T29 |
115 |
| auto[1] |
auto[0] |
auto[1] |
401099 |
1 |
|
|
T23 |
140 |
|
T29 |
7 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2757227 |
1 |
|
|
T23 |
439 |
|
T29 |
70 |
|
T30 |
17 |
| auto[1] |
auto[1] |
auto[1] |
403572 |
1 |
|
|
T23 |
100 |
|
T29 |
2 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8302369 |
1 |
|
|
T22 |
55 |
|
T23 |
1156 |
|
T24 |
403 |
| auto[1] |
6329357 |
1 |
|
|
T22 |
21 |
|
T23 |
1567 |
|
T29 |
241 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13827595 |
1 |
|
|
T22 |
76 |
|
T23 |
2521 |
|
T24 |
403 |
| auto[1] |
804131 |
1 |
|
|
T23 |
202 |
|
T29 |
10 |
|
T30 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8317202 |
1 |
|
|
T22 |
63 |
|
T23 |
1713 |
|
T24 |
403 |
| auto[1] |
6314524 |
1 |
|
|
T22 |
13 |
|
T23 |
1010 |
|
T29 |
183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2767578 |
1 |
|
|
T22 |
6 |
|
T23 |
429 |
|
T29 |
67 |
| auto[1] |
auto[0] |
auto[1] |
405336 |
1 |
|
|
T23 |
105 |
|
T29 |
4 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2742815 |
1 |
|
|
T22 |
7 |
|
T23 |
379 |
|
T29 |
106 |
| auto[1] |
auto[1] |
auto[1] |
398795 |
1 |
|
|
T23 |
97 |
|
T29 |
6 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8299561 |
1 |
|
|
T22 |
49 |
|
T23 |
1150 |
|
T24 |
403 |
| auto[1] |
6332165 |
1 |
|
|
T22 |
27 |
|
T23 |
1573 |
|
T29 |
235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13831321 |
1 |
|
|
T22 |
76 |
|
T23 |
2404 |
|
T24 |
403 |
| auto[1] |
800405 |
1 |
|
|
T23 |
319 |
|
T29 |
13 |
|
T30 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8340980 |
1 |
|
|
T22 |
65 |
|
T23 |
990 |
|
T24 |
403 |
| auto[1] |
6290746 |
1 |
|
|
T22 |
11 |
|
T23 |
1733 |
|
T29 |
234 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2740542 |
1 |
|
|
T22 |
10 |
|
T23 |
617 |
|
T29 |
87 |
| auto[1] |
auto[0] |
auto[1] |
399174 |
1 |
|
|
T23 |
147 |
|
T29 |
2 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2749799 |
1 |
|
|
T22 |
1 |
|
T23 |
797 |
|
T29 |
134 |
| auto[1] |
auto[1] |
auto[1] |
401231 |
1 |
|
|
T23 |
172 |
|
T29 |
11 |
|
T30 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8317357 |
1 |
|
|
T22 |
60 |
|
T23 |
1178 |
|
T24 |
403 |
| auto[1] |
6314369 |
1 |
|
|
T22 |
16 |
|
T23 |
1545 |
|
T29 |
196 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13824254 |
1 |
|
|
T22 |
76 |
|
T23 |
2480 |
|
T24 |
403 |
| auto[1] |
807472 |
1 |
|
|
T23 |
243 |
|
T29 |
8 |
|
T32 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8298630 |
1 |
|
|
T22 |
55 |
|
T23 |
1416 |
|
T24 |
403 |
| auto[1] |
6333096 |
1 |
|
|
T22 |
21 |
|
T23 |
1307 |
|
T29 |
174 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2767310 |
1 |
|
|
T22 |
11 |
|
T23 |
473 |
|
T29 |
89 |
| auto[1] |
auto[0] |
auto[1] |
403143 |
1 |
|
|
T23 |
105 |
|
T29 |
6 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2758314 |
1 |
|
|
T22 |
10 |
|
T23 |
591 |
|
T29 |
77 |
| auto[1] |
auto[1] |
auto[1] |
404329 |
1 |
|
|
T23 |
138 |
|
T29 |
2 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8295225 |
1 |
|
|
T22 |
52 |
|
T23 |
1430 |
|
T24 |
403 |
| auto[1] |
6336501 |
1 |
|
|
T22 |
24 |
|
T23 |
1293 |
|
T29 |
209 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13824812 |
1 |
|
|
T22 |
76 |
|
T23 |
2498 |
|
T24 |
403 |
| auto[1] |
806914 |
1 |
|
|
T23 |
225 |
|
T29 |
7 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8299127 |
1 |
|
|
T22 |
69 |
|
T23 |
1506 |
|
T24 |
403 |
| auto[1] |
6332599 |
1 |
|
|
T22 |
7 |
|
T23 |
1217 |
|
T29 |
194 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2764181 |
1 |
|
|
T22 |
7 |
|
T23 |
427 |
|
T29 |
87 |
| auto[1] |
auto[0] |
auto[1] |
402987 |
1 |
|
|
T23 |
92 |
|
T29 |
5 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2761504 |
1 |
|
|
T23 |
565 |
|
T29 |
100 |
|
T30 |
19 |
| auto[1] |
auto[1] |
auto[1] |
403927 |
1 |
|
|
T23 |
133 |
|
T29 |
2 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8269656 |
1 |
|
|
T22 |
53 |
|
T23 |
1278 |
|
T24 |
403 |
| auto[1] |
6362070 |
1 |
|
|
T22 |
23 |
|
T23 |
1445 |
|
T29 |
211 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13824137 |
1 |
|
|
T22 |
76 |
|
T23 |
2490 |
|
T24 |
403 |
| auto[1] |
807589 |
1 |
|
|
T23 |
233 |
|
T29 |
12 |
|
T32 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8302450 |
1 |
|
|
T22 |
66 |
|
T23 |
1467 |
|
T24 |
403 |
| auto[1] |
6329276 |
1 |
|
|
T22 |
10 |
|
T23 |
1256 |
|
T29 |
244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2757764 |
1 |
|
|
T22 |
10 |
|
T23 |
510 |
|
T29 |
98 |
| auto[1] |
auto[0] |
auto[1] |
403952 |
1 |
|
|
T23 |
114 |
|
T29 |
4 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2763923 |
1 |
|
|
T23 |
513 |
|
T29 |
134 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[1] |
403637 |
1 |
|
|
T23 |
119 |
|
T29 |
8 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8325624 |
1 |
|
|
T22 |
40 |
|
T23 |
1274 |
|
T24 |
403 |
| auto[1] |
6306102 |
1 |
|
|
T22 |
36 |
|
T23 |
1449 |
|
T29 |
150 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13826816 |
1 |
|
|
T22 |
75 |
|
T23 |
2468 |
|
T24 |
403 |
| auto[1] |
804910 |
1 |
|
|
T22 |
1 |
|
T23 |
255 |
|
T29 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8306180 |
1 |
|
|
T22 |
53 |
|
T23 |
1406 |
|
T24 |
403 |
| auto[1] |
6325546 |
1 |
|
|
T22 |
23 |
|
T23 |
1317 |
|
T29 |
225 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2776336 |
1 |
|
|
T22 |
8 |
|
T23 |
460 |
|
T29 |
125 |
| auto[1] |
auto[0] |
auto[1] |
405806 |
1 |
|
|
T23 |
108 |
|
T29 |
5 |
|
T30 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2744300 |
1 |
|
|
T22 |
14 |
|
T23 |
602 |
|
T29 |
92 |
| auto[1] |
auto[1] |
auto[1] |
399104 |
1 |
|
|
T22 |
1 |
|
T23 |
147 |
|
T29 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8331817 |
1 |
|
|
T22 |
45 |
|
T23 |
1508 |
|
T24 |
403 |
| auto[1] |
6299909 |
1 |
|
|
T22 |
31 |
|
T23 |
1215 |
|
T29 |
207 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13831884 |
1 |
|
|
T22 |
75 |
|
T23 |
2410 |
|
T24 |
403 |
| auto[1] |
799842 |
1 |
|
|
T22 |
1 |
|
T23 |
313 |
|
T29 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8341813 |
1 |
|
|
T22 |
57 |
|
T23 |
1073 |
|
T24 |
403 |
| auto[1] |
6289913 |
1 |
|
|
T22 |
19 |
|
T23 |
1650 |
|
T29 |
211 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2764940 |
1 |
|
|
T22 |
12 |
|
T23 |
748 |
|
T29 |
97 |
| auto[1] |
auto[0] |
auto[1] |
403207 |
1 |
|
|
T23 |
166 |
|
T29 |
4 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2725131 |
1 |
|
|
T22 |
6 |
|
T23 |
589 |
|
T29 |
105 |
| auto[1] |
auto[1] |
auto[1] |
396635 |
1 |
|
|
T22 |
1 |
|
T23 |
147 |
|
T29 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8294904 |
1 |
|
|
T22 |
52 |
|
T23 |
1556 |
|
T24 |
403 |
| auto[1] |
6336822 |
1 |
|
|
T22 |
24 |
|
T23 |
1167 |
|
T29 |
158 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13831193 |
1 |
|
|
T22 |
76 |
|
T23 |
2502 |
|
T24 |
403 |
| auto[1] |
800533 |
1 |
|
|
T23 |
221 |
|
T29 |
7 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8335769 |
1 |
|
|
T22 |
58 |
|
T23 |
1543 |
|
T24 |
403 |
| auto[1] |
6295957 |
1 |
|
|
T22 |
18 |
|
T23 |
1180 |
|
T29 |
171 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2742629 |
1 |
|
|
T22 |
7 |
|
T23 |
515 |
|
T29 |
100 |
| auto[1] |
auto[0] |
auto[1] |
397864 |
1 |
|
|
T23 |
114 |
|
T29 |
6 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2752795 |
1 |
|
|
T22 |
11 |
|
T23 |
444 |
|
T29 |
64 |
| auto[1] |
auto[1] |
auto[1] |
402669 |
1 |
|
|
T23 |
107 |
|
T29 |
1 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8326951 |
1 |
|
|
T22 |
56 |
|
T23 |
1500 |
|
T24 |
403 |
| auto[1] |
6304775 |
1 |
|
|
T22 |
20 |
|
T23 |
1223 |
|
T29 |
188 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13827133 |
1 |
|
|
T22 |
76 |
|
T23 |
2478 |
|
T24 |
403 |
| auto[1] |
804593 |
1 |
|
|
T23 |
245 |
|
T29 |
5 |
|
T32 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8307778 |
1 |
|
|
T22 |
59 |
|
T23 |
1503 |
|
T24 |
403 |
| auto[1] |
6323948 |
1 |
|
|
T22 |
17 |
|
T23 |
1220 |
|
T29 |
154 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2770606 |
1 |
|
|
T22 |
14 |
|
T23 |
548 |
|
T29 |
76 |
| auto[1] |
auto[0] |
auto[1] |
405067 |
1 |
|
|
T23 |
134 |
|
T29 |
2 |
|
T32 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2748749 |
1 |
|
|
T22 |
3 |
|
T23 |
427 |
|
T29 |
73 |
| auto[1] |
auto[1] |
auto[1] |
399526 |
1 |
|
|
T23 |
111 |
|
T29 |
3 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8294979 |
1 |
|
|
T22 |
59 |
|
T23 |
1309 |
|
T24 |
403 |
| auto[1] |
6336747 |
1 |
|
|
T22 |
17 |
|
T23 |
1414 |
|
T29 |
242 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13827920 |
1 |
|
|
T22 |
76 |
|
T23 |
2468 |
|
T24 |
403 |
| auto[1] |
803806 |
1 |
|
|
T23 |
255 |
|
T29 |
11 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8308562 |
1 |
|
|
T22 |
58 |
|
T23 |
1349 |
|
T24 |
403 |
| auto[1] |
6323164 |
1 |
|
|
T22 |
18 |
|
T23 |
1374 |
|
T29 |
239 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2759176 |
1 |
|
|
T22 |
14 |
|
T23 |
554 |
|
T29 |
91 |
| auto[1] |
auto[0] |
auto[1] |
401255 |
1 |
|
|
T23 |
125 |
|
T29 |
3 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2760182 |
1 |
|
|
T22 |
4 |
|
T23 |
565 |
|
T29 |
137 |
| auto[1] |
auto[1] |
auto[1] |
402551 |
1 |
|
|
T23 |
130 |
|
T29 |
8 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8302437 |
1 |
|
|
T22 |
60 |
|
T23 |
1325 |
|
T24 |
403 |
| auto[1] |
6329289 |
1 |
|
|
T22 |
16 |
|
T23 |
1398 |
|
T29 |
173 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13826851 |
1 |
|
|
T22 |
76 |
|
T23 |
2444 |
|
T24 |
403 |
| auto[1] |
804875 |
1 |
|
|
T23 |
279 |
|
T29 |
8 |
|
T30 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8301936 |
1 |
|
|
T22 |
60 |
|
T23 |
1245 |
|
T24 |
403 |
| auto[1] |
6329790 |
1 |
|
|
T22 |
16 |
|
T23 |
1478 |
|
T29 |
150 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2759754 |
1 |
|
|
T22 |
16 |
|
T23 |
663 |
|
T29 |
91 |
| auto[1] |
auto[0] |
auto[1] |
401510 |
1 |
|
|
T23 |
152 |
|
T29 |
5 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2765161 |
1 |
|
|
T23 |
536 |
|
T29 |
51 |
|
T30 |
21 |
| auto[1] |
auto[1] |
auto[1] |
403365 |
1 |
|
|
T23 |
127 |
|
T29 |
3 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8326021 |
1 |
|
|
T22 |
56 |
|
T23 |
1259 |
|
T24 |
403 |
| auto[1] |
6305705 |
1 |
|
|
T22 |
20 |
|
T23 |
1464 |
|
T29 |
188 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13827244 |
1 |
|
|
T22 |
76 |
|
T23 |
2548 |
|
T24 |
403 |
| auto[1] |
804482 |
1 |
|
|
T23 |
175 |
|
T29 |
4 |
|
T30 |
1 |