Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8313433 |
1 |
|
|
T22 |
53 |
|
T23 |
1348 |
|
T24 |
403 |
| auto[1] |
6318293 |
1 |
|
|
T22 |
23 |
|
T23 |
1375 |
|
T29 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13824297 |
1 |
|
|
T22 |
76 |
|
T23 |
2423 |
|
T24 |
403 |
| auto[1] |
807429 |
1 |
|
|
T23 |
300 |
|
T29 |
18 |
|
T30 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8303129 |
1 |
|
|
T22 |
53 |
|
T23 |
1117 |
|
T24 |
403 |
| auto[1] |
6328597 |
1 |
|
|
T22 |
23 |
|
T23 |
1606 |
|
T29 |
277 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2767954 |
1 |
|
|
T22 |
15 |
|
T23 |
706 |
|
T29 |
132 |
| auto[1] |
auto[0] |
auto[1] |
405699 |
1 |
|
|
T23 |
163 |
|
T29 |
10 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2753214 |
1 |
|
|
T22 |
8 |
|
T23 |
600 |
|
T29 |
127 |
| auto[1] |
auto[1] |
auto[1] |
401730 |
1 |
|
|
T23 |
137 |
|
T29 |
8 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |