Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8346447 |
1 |
|
|
T22 |
39 |
|
T23 |
1376 |
|
T24 |
403 |
| auto[1] |
6285279 |
1 |
|
|
T22 |
37 |
|
T23 |
1347 |
|
T29 |
160 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13819472 |
1 |
|
|
T22 |
76 |
|
T23 |
2525 |
|
T24 |
403 |
| auto[1] |
812254 |
1 |
|
|
T23 |
198 |
|
T29 |
7 |
|
T1 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8263117 |
1 |
|
|
T22 |
61 |
|
T23 |
1686 |
|
T24 |
403 |
| auto[1] |
6368609 |
1 |
|
|
T22 |
15 |
|
T23 |
1037 |
|
T29 |
175 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2815579 |
1 |
|
|
T22 |
8 |
|
T23 |
463 |
|
T29 |
100 |
| auto[1] |
auto[0] |
auto[1] |
413375 |
1 |
|
|
T23 |
107 |
|
T29 |
2 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2740776 |
1 |
|
|
T22 |
7 |
|
T23 |
376 |
|
T29 |
68 |
| auto[1] |
auto[1] |
auto[1] |
398879 |
1 |
|
|
T23 |
91 |
|
T29 |
5 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |