Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8299619 |
1 |
|
|
T22 |
56 |
|
T23 |
1397 |
|
T24 |
403 |
| auto[1] |
6332107 |
1 |
|
|
T22 |
20 |
|
T23 |
1326 |
|
T29 |
225 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12076363 |
1 |
|
|
T22 |
64 |
|
T23 |
1959 |
|
T24 |
403 |
| auto[1] |
2555363 |
1 |
|
|
T22 |
12 |
|
T23 |
764 |
|
T29 |
119 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8317189 |
1 |
|
|
T22 |
57 |
|
T23 |
1281 |
|
T24 |
403 |
| auto[1] |
6314537 |
1 |
|
|
T22 |
19 |
|
T23 |
1442 |
|
T29 |
234 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1872797 |
1 |
|
|
T22 |
7 |
|
T23 |
280 |
|
T29 |
61 |
| auto[1] |
auto[0] |
auto[1] |
1276514 |
1 |
|
|
T22 |
9 |
|
T23 |
298 |
|
T29 |
50 |
| auto[1] |
auto[1] |
auto[0] |
1886377 |
1 |
|
|
T23 |
398 |
|
T29 |
54 |
|
T30 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1278849 |
1 |
|
|
T22 |
3 |
|
T23 |
466 |
|
T29 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |