Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8365538 |
1 |
|
|
T22 |
56 |
|
T23 |
1351 |
|
T24 |
403 |
| auto[1] |
6266188 |
1 |
|
|
T22 |
20 |
|
T23 |
1372 |
|
T29 |
271 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12072240 |
1 |
|
|
T22 |
62 |
|
T23 |
2052 |
|
T24 |
403 |
| auto[1] |
2559486 |
1 |
|
|
T22 |
14 |
|
T23 |
671 |
|
T29 |
97 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8301618 |
1 |
|
|
T22 |
55 |
|
T23 |
1430 |
|
T24 |
403 |
| auto[1] |
6330108 |
1 |
|
|
T22 |
21 |
|
T23 |
1293 |
|
T29 |
183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1902871 |
1 |
|
|
T22 |
4 |
|
T23 |
303 |
|
T29 |
29 |
| auto[1] |
auto[0] |
auto[1] |
1293187 |
1 |
|
|
T22 |
8 |
|
T23 |
341 |
|
T29 |
20 |
| auto[1] |
auto[1] |
auto[0] |
1867751 |
1 |
|
|
T22 |
3 |
|
T23 |
319 |
|
T29 |
57 |
| auto[1] |
auto[1] |
auto[1] |
1266299 |
1 |
|
|
T22 |
6 |
|
T23 |
330 |
|
T29 |
77 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |