Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8313043 |
1 |
|
|
T22 |
69 |
|
T23 |
1852 |
|
T24 |
403 |
| auto[1] |
6318683 |
1 |
|
|
T22 |
7 |
|
T23 |
871 |
|
T29 |
166 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2757885 |
1 |
|
|
T22 |
5 |
|
T23 |
378 |
|
T29 |
80 |
| auto[1] |
auto[0] |
auto[1] |
402513 |
1 |
|
|
T23 |
97 |
|
T29 |
1 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2756316 |
1 |
|
|
T22 |
2 |
|
T23 |
318 |
|
T29 |
82 |
| auto[1] |
auto[1] |
auto[1] |
401969 |
1 |
|
|
T23 |
78 |
|
T29 |
3 |
|
T1 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |